11. Bring Your Own Model

This section explains how to extend Tiny ML Tensorlab with custom models or use pre-trained models from external sources.

Contents

• 11.1. Adding Custom Models
  • 11.1.1. Overview
  • 11.1.2. Quick Summary
  • 11.1.3. Step 1: Choose the Right Model File
  • 11.1.4. Step 2: Create Your Model Class
  • 11.1.5. Available Layer Types
  • 11.1.6. Step 3: Add to __all__
  • 11.1.7. Step 4: Verify Your Model
  • 11.1.8. Step 5 (Optional): Add Device Performance Info
  • 11.1.9. Step 6 (Optional): Add GUI Model Description
  • 11.1.10. Using Your Custom Model
  • 11.1.11. Naming Conventions
  • 11.1.12. Configuring Model Layer Parameters
  • 11.1.13. Troubleshooting
  • 11.1.14. Summary Checklist
  • 11.1.15. Next Steps
• 11.2. Compilation Only
  • 11.2.1. Overview
  • 11.2.2. ONNX Model Requirements
  • 11.2.3. Compilation Configuration
  • 11.2.4. Running Compilation
  • 11.2.5. Model Formats
  • 11.2.6. Output Artifacts
  • 11.2.7. NPU Compilation
  • 11.2.8. Example: External PyTorch Model
  • 11.2.9. Example: TensorFlow Model
  • 11.2.10. Troubleshooting
  • 11.2.11. Best Practices
  • 11.2.12. Next Steps

11.3. Two Approaches

1. Add a Custom Model to ModelZoo

If you want to create a new neural network architecture that integrates fully with the training pipeline:

• Add your model class to tinyml_modelzoo/models/

• Register it in the module’s __all__ list

• Use it like any built-in model

See Adding Custom Models for step-by-step instructions.

2. Compile an Existing ONNX Model

If you already have a trained model (from PyTorch, TensorFlow, etc.) and just want to compile it for TI MCUs:

• Export your model to ONNX format

• Use Tiny ML Tensorlab’s compilation-only mode

• Skip the dataset and training steps

See Compilation Only for instructions.

11.4. Model Requirements

For NPU Devices (F28P55, AM13E2, MSPM0G5187):

Models must follow NPU constraints for hardware acceleration:

• All channels must be multiples of 4

• Convolution kernel heights ≤ 7 for GCONV layers

• MaxPool kernels ≤ 4

• FC layer inputs ≥ 16 features (8-bit) or ≥ 8 features (4-bit)

See NPU Guidelines for complete constraints.

For Non-NPU Devices:

More flexible architecture choices, but consider:

• Total parameter count (memory constraints)

• Layer types supported by the compiler

• Inference time requirements