SOC

The SOC driver provides API to configure SOC specific features like clocks.

Features Supported

API to enable/disable a module clock
API to set clock frequency for module
Generic utility API like get CPU clock, get core name string, control module MMR lock/unlock API

SysConfig Features

SOC driver is integrated with each of the drivers. User need not perform any explicit configuration for this driver

Features NOT Supported

NA

Important Usage Guidelines

Most of these APIs are already integrated with SysConfig tool and the generated code does the required call to enable a module, set the required clock and so on. User need to use these APIs in their application only for exceptional scenarios.

Example Usage

Include the below file to access the APIs

//! [include]
#include <drivers/soc.h>
//! [include]

Get Core Name String

//! [get_corename]
    const char *coreName;

    coreName = SOC_getCoreName(CSL_CORE_ID_R5FSS0_0);
    DebugP_log("Core name is: %s\r\n", coreName);
//! [get_corename]

Get CPU Clock Frequency

//! [get_selfcpuclk]
    uint64_t cpuClockRate;

    cpuClockRate = SOC_getSelfCpuClk();
    DebugP_log("CPU Clock Frequency: %u\r\n", cpuClockRate);
//! [get_selfcpuclk]

Set CPU Clock Frequency

//! [set_moduleclk]
    #include <drivers/sciclient.h> /* For the device and clock macros */

    uint32_t moduleId = TISCI_DEV_FSS0_OSPI_0;
    uint32_t clkId = TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK;
    uint64_t clkRate = 200000000U;

    SOC_moduleSetClockFrequency(moduleId, clkId, clkRate);
//! [set_moduleclk]

Set CPU Clock Frequency with a specific parent clock

//! [set_moduleclkwithparent]
    #include <drivers/sciclient.h> /* For the device and clock macros */

    uint32_t moduleId = TISCI_DEV_FSS0_OSPI_0;
    uint32_t clkId = TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK;
    uint32_t clkParentId = TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK;
    uint64_t clkRate = 200000000U;

    SOC_moduleSetClockFrequencyWithParent(moduleId, clkId, clkParentId, clkRate);
//! [set_moduleclkwithparent]

API

DRV_SOC_MODULE

API Reference

SOC Domain ID

SOC_DOMAIN_ID_MAIN

SOC_DOMAIN_ID_MCU

SOC_DOMAIN_ID_WKUP

Unnamed Group

SOC_PSC_DOMAIN_ID_MAIN: \ SOC PSC Domain ID

SOC_PSC_DOMAIN_ID_MCU

SOC PSC Module State

SOC_PSC_SYNCRESETDISABLE

SOC_PSC_SYNCRESET

SOC_PSC_DISABLE

SOC_PSC_ENABLE

SOC PSC Domain State

SOC_PSC_DOMAIN_OFF

SOC_PSC_DOMAIN_ON

Defines

SOC_BOOTMODE_MMCSD: Switch value for SD card boot mode.

Functions

int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable)

Enable clock to specified module.

Parameters:

moduleId – [in] see tisci_devices for list of device ID’s
enable – [in] 1: enable clock to the module, 0: disable clock to the module

Returns:

SystemP_SUCCESS Module clock is enabled

Returns:

SystemP_FAILURE Module clock could not be enabled

int32_t SOC_moduleSetClockFrequencyWithParent(uint32_t moduleId, uint32_t clkId, uint32_t clkParent, uint64_t clkRate)

Set module clock to specified frequency and with a specific parent.

Parameters:

moduleId – [in] see tisci_devices for list of module ID’s
clkId – [in] see tisci_clocks for list of clocks associated with the specified module ID
clkParent – [in] see tisci_clocks for list of clock parents associated with the specified module ID
clkRate – [in] Frequency to set in Hz

Returns:

SystemP_SUCCESS Module clock is enabled

Returns:

SystemP_FAILURE Module clock could not be enabled

int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate)

Set module clock to specified frequency.

Parameters:

moduleId – [in] see tisci_devices for list of module ID’s
clkId – [in] see tisci_clocks for list of clocks associated with the specified module ID
clkRate – [in] Frequency to set in Hz

Returns:

SystemP_SUCCESS Module clock is enabled

Returns:

SystemP_FAILURE Module clock could not be enabled

const char *SOC_getCoreName(uint16_t coreId)

Convert a core ID to a user readable name.

Parameters:: coreId – [in] see CSL_CoreID
Returns:: name as a string

uint32_t SOC_getCoreId(const char *coreName)

Convert a core ID to a user readable name.

Parameters:: coreName – [in] core Name
Returns:: coreID

uint64_t SOC_getSelfCpuClk(void)

Get the clock frequency in Hz of the CPU on which the driver is running.

Returns:: Clock frequency in Hz

void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable)

Enable or disable ePWM time base clock from Control MMR.

Parameters:

epwmInstance – [in] ePWM instance number [0 - (CSL_EPWM_PER_CNT-1)]
enable – [in] TRUE to enable and FALSE to disable

void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition)

Lock control module partition to prevent writes into control MMRs.

Parameters:

domainId – [in] See SOC_DomainId_t
partition – [in] Partition number to unlock

void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition)

Unlock control module partition to allow writes into control MMRs.

Parameters:

domainId – [in] See SOC_DomainId_t
partition – [in] Partition number to unlock

void SOC_unlockAllMMR(void): Unlocks all the control MMRs.

int32_t SOC_moduleGetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t *clkRate)

Get module clock frequency.

Parameters:

moduleId – [in] see tisci_devices for list of module ID’s
clkId – [in] see tisci_clocks for list of clocks associated with the specified module ID
clkRate – [out] Frequency of the clock

Returns:

SystemP_SUCCESS on success, else failure

void SOC_setDevStat(uint32_t bootMode)

Change boot mode by setting devstat register.

Parameters:: bootMode – [IN] Boot mode switch value

void SOC_triggerMcuLpmWakeup(void): Generates the MCU IPC interrupt to DM R5 to wakeup the main domain from MCU only LPM mode.

void SOC_generateSwWarmResetMainDomain(void): Generate SW Warm Reset Main Domain.

uint32_t SOC_getWarmResetCauseMainDomain(void)

Get the reset reason source for Main Domain.

Returns:: Reset Reason Source Main Domain

void SOC_generateSwWarmResetMcuDomain(void): Generate SW WARM Reset Mcu Domain.

void SOC_generateSwWarmResetMainDomainFromMcuDomain(void): Generate SW WARM Reset Main Domain from Mcu Domain.

void SOC_generateSwPORResetMainDomainFromMcuDomain(void): Generate SW POR Reset Main Domain from Mcu Domain.

uint32_t SOC_getWarmResetCauseMcuDomain(void)

Get the reset reason source for Mcu Domain.

Returns:: Reset Reason Source Mcu Domain

void SOC_clearResetCauseMainMcuDomain(uint32_t resetCause)

Clears reason for Warm and Main/Mcu Domain Power On Resets. CTRLMMR_RST_SRC is just a mirror of CTRLMMR_MCU_RST_SRC register. It is read only. So we need to write 1 to CTRLMMR_MCU_RST_SRC to clear the reset reason.

Parameters:: resetCause – [IN] Reset reason value to clear.

int32_t SOC_enableResetIsolation(uint32_t main2McuIsolation, uint32_t mcu2MainIsolation, uint32_t mcu2dmIsolation, uint32_t debugIsolationEnable)

Enable reset isolation of MCU domain for safety applications.

Parameters:

main2McuIsolation – [IN] Flag to enable isolation of mcu domain from main domain Setting this flag restricts the access of MCU resources by main domain
mcu2MainIsolation – [IN] Flag to enable isolation of MCU domain from DM Setting this flag restricts the access of MCU resources by DM
mcu2dmIsolation – [IN] Flag to enable isolation of DM from mcu domain Setting this flag restricts the access of DM resources by MCU domain
debugIsolationEnable – [IN] Enable debug isolation. Setting this would restrict JTAG access to MCU domain

void SOC_setMCUResetIsolationDone(uint32_t value)

Set MCU reset isolation done flag.

Parameters:: value – [IN] : 0 - Allow main domain reset to propogate : 1 - Do not allow main domain reset to propogate

void SOC_waitMainDomainReset(void): Wait for main domain reset to complete.

int32_t SOC_getPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t *domainState, uint32_t *moduleState)

Get PSC (Power Sleep Controller) state.

Parameters:

instNum – [IN] : PSC Instance. See SOC_PSCDomainId_t
domainNum – [IN] : Power domain number
moduleNum – [IN] : Module number
domainState – [OUT] : Domain state (1 : ON, 0 : OFF)
moduleState – [OUT] : Module State. See SOC_PSCModuleState_t

Returns:

SystemP_SUCCESS on success, else failure

int32_t SOC_setPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t pscState)

Set PSC (Power Sleep Controller) state.

Parameters:

instNum – [IN] : PSC Instance. See SOC_PSCDomainId_t
domainNum – [IN] : Power domain number
moduleNum – [IN] : Module number
pscState – [IN] : PSC module state. See SOC_PSCModuleState_t

Returns:

SystemP_SUCCESS on success, else failure

void SOC_setFSSCtrlFlashBootSize(void)

Update the boot block size for FSS subsystem.

Selects the size of the boot block to be used for the OSPI flash interface. Default value is 1’b0 - S0_BOOT_SIZE_64MB for the MMR register. Set 1’b1 - S0_BOOT_SIZE_128MB to update the value.

uint64_t Soc_getPhyAddr(uint64_t virtAddr)

Get Physical Address from virtual address.

Parameters:: virtAddr – [IN] : Virtual Address(Alias)
Returns:: Physical Address

void SOC_setAdcGPIEnable(void): Set ADC GPI Enable to use ADC pins as GPI.

uint64_t SOC_phyToVirtFxn(uint64_t phyAddr)

Get Virtual Address from Physical address.

Parameters:: phyAddr – [IN] : Physical Address
Returns:: Virtual Address

uint64_t SOC_phyToVirtFxnC7x(const void *virtAddr)

Get Physical Address from virtual address(Exclusively for C7X core).

Parameters:: virtAddr – [IN] : Virtual Address(Alias)
Returns:: Physical Address