AM273x MCU+ SDK  08.06.00
hwa/v0/hwa.h
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1 /*
2  * Copyright (C) 2021-23 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  */
33 
67 #ifndef HWA_H_
68 #define HWA_H_
69 
70 /* ========================================================================== */
71 /* Include Files */
72 /* ========================================================================== */
73 
74 #include <stdint.h>
75 #include <stddef.h>
76 #include <stdbool.h>
77 #include <drivers/hw_include/csl_complex_math_types.h>
78 #include <kernel/dpl/HwiP.h>
79 #include <drivers/hw_include/cslr_hwa.h>
80 
81 #ifdef __cplusplus
82 extern "C" {
83 #endif
84 
85 /* ========================================================================== */
86 /* Macros & Typedefs */
87 /* ========================================================================== */
88 
90 #define HWADRV_ADDR_TRANSLATE_CPU_TO_HWA(x) (uint32_t)((uint32_t)(x) & 0x000FFFFFU)
91 
99 #define HWA_ERRNO_BASE (-2800)
100 
101 #define HWA_EINVAL (HWA_ERRNO_BASE-1)
102 
103 #define HWA_ENOINIT (HWA_ERRNO_BASE-2)
104 
105 #define HWA_EOUTOFRANGE (HWA_ERRNO_BASE-3)
106 
107 #define HWA_EOUTOFMEM (HWA_ERRNO_BASE-4)
108 
109 #define HWA_ENOTSUPP (HWA_ERRNO_BASE-5)
110 
111 #define HWA_EINUSE (HWA_ERRNO_BASE-6)
112 
113 #define HWA_ENOTALIGNED (HWA_ERRNO_BASE-7)
114 
115 #define HWA_EINVAL_COMMON_REGISTER_PARAMSET (HWA_ERRNO_BASE-8)
116 
117 #define HWA_EINVAL_COMMON_REGISTER_PARAMSET_ALT (HWA_ERRNO_BASE-9)
118 
119 #define HWA_EINVAL_COMMON_REGISTER_FFTCONFIG (HWA_ERRNO_BASE-10)
120 
121 #define HWA_EINVAL_COMMON_REGISTER_DCEST (HWA_ERRNO_BASE-11)
122 
123 #define HWA_EINVAL_COMMON_REGISTER_CFAR (HWA_ERRNO_BASE-12)
124 
125 #define HWA_EINVAL_COMMON_REGISTER_INTERFERENCE (HWA_ERRNO_BASE-13)
126 
127 #define HWA_EINVAL_COMMON_REGISTER_COMPLEXMULT (HWA_ERRNO_BASE-14)
128 
129 #define HWA_EINVAL_COMMON_REGISTER_CHANCOMB (HWA_ERRNO_BASE-15)
130 
131 #define HWA_EINVAL_COMMON_REGISTER_ZEROINSERT (HWA_ERRNO_BASE-16)
132 
133 #define HWA_EINVAL_COMMON_REGISTER_ADVSTAT (HWA_ERRNO_BASE-17)
134 
135 #define HWA_EINVAL_COMMON_REGISTER_COMPRESS (HWA_ERRNO_BASE-18)
136 
137 #define HWA_EINVAL_COMMON_REGISTER_LOCALMAXIMUM (HWA_ERRNO_BASE-19)
138 
139 #define HWA_EINVAL_PARAMSET_GENERALCONFIG (HWA_ERRNO_BASE - 20)
140 
141 #define HWA_EINVAL_PARAMSET_SOURCE (HWA_ERRNO_BASE - 21)
142 
143 #define HWA_EINVAL_PARAMSET_DEST (HWA_ERRNO_BASE - 22)
144 
145 #define HWA_EINVAL_PARAMSET_SRCDST_ADDRESS (HWA_ERRNO_BASE - 23)
146 
147 #define HWA_EINVAL_PARAMSET_FFTMODE_GENERALCONFIG (HWA_ERRNO_BASE - 24)
148 
149 #define HWA_EINVAL_PARAMSET_FFTMODE_SIZE (HWA_ERRNO_BASE - 25)
150 
151 #define HWA_EINVAL_PARAMSET_FFTMODE_POSTPROC (HWA_ERRNO_BASE - 26)
152 
153 #define HWA_EINVAL_PARAMSET_FFTMODE_PREPROC (HWA_ERRNO_BASE - 27)
154 
155 #define HWA_EINVAL_PARAMSET_FFTMODE_PREPROC_INTERF (HWA_ERRNO_BASE - 28)
156 
157 #define HWA_EINVAL_PARAMSET_FFTMODE_PREPROC_COMPLEXMULT (HWA_ERRNO_BASE - 29)
158 
159 #define HWA_EINVAL_PARAMSET_CFARMODE_GENERALCONFIG (HWA_ERRNO_BASE - 30)
160 
161 #define HWA_EINVAL_PARAMSET_CFARMODE_OSCONFIG (HWA_ERRNO_BASE - 31)
162 
163 #define HWA_EINVAL_PARAMSET_CFARMODE_CACONFIG (HWA_ERRNO_BASE - 32)
164 
165 #define HWA_EINVAL_PARAMSET_COMPRESSMODE (HWA_ERRNO_BASE - 33)
166 
167 #define HWA_EINVAL_PARAMSET_LOCALMAXMODE (HWA_ERRNO_BASE - 34)
168 
169 #define HWA_PARAMSET_POLLINGNOTALLOWED (HWA_ERRNO_BASE - 35)
170 
171 #define HWA_EINVAL_COMMON_REGISTER_CFAR_DET_THR (HWA_ERRNO_BASE - 36)
172 
175 #define HWA_NUM_RXCHANNELS (12U)
176 
177 #define HWA_NUM_INTERFMITG_WINARRAY (5U)
178 
179 #define HWA_BPMPATTERN_LENGTH_INWORDS (8U)
180 
181 #define HWA_CHANCOMB_LENGTH_INWORDS (8U)
182 
183 #define HWA_ZEROINSERT_LENGTH_INWORDS (8U)
184 
185 #define HWA_NUM_RAMS (10U)
186 
187 #define HWA_MAXNUM_LOOPS (4095U)
188 
189 #define HWA_CMP_K_ARR_LEN (8U)
190 
204 #define HWA_DONE_INTERRUPT_PRIORITY (1U)
205 
206 #define HWA_ALTDONE_INTERRUPT_PRIORITY (1U)
207 
208 #define HWA_PARAMSETDONE_INTERRUPT1_PRIORITY (1U)
209 
210 #define HWA_PARAMSETDONE_INTERRUPT2_PRIORITY (1U)
211 
212 #define HWA_LOCAL_RAM_ERR_PRIORITY (1U)
213 
220 #define HWA_FEATURE_BIT_ENABLE ((uint8_t)1U)
221 #define HWA_FEATURE_BIT_DISABLE ((uint8_t)0U)
229 #define HWA_SAMPLES_WIDTH_16BIT ((uint8_t)0U)
230 #define HWA_SAMPLES_WIDTH_32BIT ((uint8_t)1U)
238 #define HWA_SAMPLES_FORMAT_COMPLEX ((uint8_t)0U)
239 #define HWA_SAMPLES_FORMAT_REAL ((uint8_t)1U)
247 #define HWA_SAMPLES_UNSIGNED ((uint8_t)0U)
248 #define HWA_SAMPLES_SIGNED ((uint8_t)1U)
256 #define HWA_FFT_WINDOW_NONSYMMETRIC ((uint8_t)0U)
257 #define HWA_FFT_WINDOW_SYMMETRIC ((uint8_t)1U)
269 #define HWA_FFT_WINDOW_INTERPOLATE_MODE_NONE ((uint8_t)0U)
270 #define HWA_FFT_WINDOW_INTERPOLATE_MODE_4K ((uint8_t)2U)
271 #define HWA_FFT_WINDOW_INTERPOLATE_MODE_8K ((uint8_t)1U)
279 #define HWA_FFT_MODE_MAGNITUDE_LOG2_DISABLED ((uint8_t)0U)
280 #define HWA_FFT_MODE_MAGNITUDE_ONLY_ENABLED ((uint8_t)2U)
281 #define HWA_FFT_MODE_MAGNITUDE_LOG2_ENABLED ((uint8_t)3U)
289 #define HWA_FFT_MODE_OUTPUT_DEFAULT ((uint8_t)0U)
290 #define HWA_FFT_MODE_OUTPUT_MAX_STATS ((uint8_t)2U)
291 #define HWA_FFT_MODE_OUTPUT_SUM_STATS ((uint8_t)3U)
299 #define HWA_NOISE_AVG_MODE_CFAR_CA ((uint8_t)0U)
300 #define HWA_NOISE_AVG_MODE_CFAR_CAGO ((uint8_t)1U)
301 #define HWA_NOISE_AVG_MODE_CFAR_CASO ((uint8_t)2U)
302 #define HWA_NOISE_AVG_MODE_CFAR_OS ((uint8_t)3U)
310 #define HWA_TRIG_MODE_IMMEDIATE ((uint8_t)0U)
311 #define HWA_TRIG_MODE_SOFTWARE ((uint8_t)1U)
312 #define HWA_TRIG_MODE_RESERVED1 ((uint8_t)2U)
313 #define HWA_TRIG_MODE_DMA ((uint8_t)3U)
314 #define HWA_TRIG_MODE_HARDWARE ((uint8_t)4U)
315 #define HWA_TRIG_MODE_RESERVED2 ((uint8_t)5U)
316 #define HWA_TRIG_MODE_RESERVED3 ((uint8_t)6U)
317 #define HWA_TRIG_MODE_SOFTWARE2 ((uint8_t)7U)
325 #define HWA_CONTEXTSWITCH_TRIG_MODE_DMA ((uint8_t)3U)
326 #define HWA_CONTEXTSWITCH_TRIG_MODE_HARDWARE ((uint8_t)4U)
327 #define HWA_CONTEXTSWITCH_TRIG_MODE_SOFTWARE ((uint8_t)5U)
335 #define HWA_THREAD_BACKGROUNDCONTEXT ((uint8_t)0U)
336 #define HWA_THREAD_ALTCONTEXT ((uint8_t)1U)
344 #define HWA_ACCELMODE_FFT ((uint8_t)0U)
345 #define HWA_ACCELMODE_CFAR ((uint8_t)1U)
346 #define HWA_ACCELMODE_COMPRESS ((uint8_t)2U)
347 #define HWA_ACCELMODE_LOCALMAX ((uint8_t)3U)
348 #define HWA_ACCELMODE_NONE ((uint8_t)7U)
368 #define HWA_CFAR_OPER_MODE_LOG_INPUT_REAL 0U
369 #define HWA_CFAR_OPER_MODE_LOG_INPUT_COMPLEX 1U
370 #define HWA_CFAR_OPER_MODE_MAG_INPUT_REAL 2U
371 #define HWA_CFAR_OPER_MODE_MAG_INPUT_COMPLEX 3U
372 #define HWA_CFAR_OPER_MODE_MAG_SQR_INPUT_REAL 4U
373 #define HWA_CFAR_OPER_MODE_MAG_SQR_INPUT_COMPLEX 5U
374 #define HWA_CFAR_OPER_MODE_LOG_INPUT_COMPLEX_LINEARCFAR 6U
392 #define HWA_CFAR_OUTPUT_MODE_I_nAVG_ALL_Q_CUT ((uint8_t)0U)
394 #define HWA_CFAR_OUTPUT_MODE_I_nAVG_ALL_Q_DET_FLAG ((uint8_t)1U)
396 #define HWA_CFAR_OUTPUT_MODE_I_PEAK_IDX_Q_NEIGHBOR_NOISE_VAL ((uint8_t)2U)
398 #define HWA_CFAR_OUTPUT_MODE_I_PEAK_IDX_Q_CUT ((uint8_t)3U)
400 #define HWA_CFAR_OUTPUT_MODE_FILTER_LARGE_PEAK ((uint8_t)4U)
409 #define HWA_RAM_TYPE_WINDOW_RAM ((uint8_t)0U)
410 #define HWA_RAM_TYPE_VECTORMULTIPLY_RAM ((uint8_t)1U)
411 #define HWA_RAM_TYPE_LUT_FREQ_DEROTATE_RAM ((uint8_t)2U)
412 #define HWA_RAM_TYPE_SHUFFLE_RAM ((uint8_t)3U)
413 #define HWA_RAM_TYPE_HIST_THRESH_RAM ((uint8_t)4U)
414 #define HWA_RAM_TYPE_2DSTAT_ITER_VAL ((uint8_t)5U)
415 #define HWA_RAM_TYPE_2DSTAT_ITER_IDX ((uint8_t)6U)
416 #define HWA_RAM_TYPE_2DSTAT_SAMPLE_VAL ((uint8_t)7U)
417 #define HWA_RAM_TYPE_2DSTAT_SAMPLE_IDX ((uint8_t)8U)
418 #define HWA_RAM_TYPE_HISTOGRAM_RAM ((uint8_t)9U)
426 #define HWA_CLIPREG_TYPE_DCACC ((uint8_t)0U)
427 #define HWA_CLIPREG_TYPE_DCEST ((uint8_t)1U)
428 #define HWA_CLIPREG_TYPE_DCSUB ((uint8_t)2U)
429 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGACC ((uint8_t)3U)
430 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGDIFFACC ((uint8_t)4U)
431 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGTHRESHOLD ((uint8_t)5U)
432 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGDIFFTHRESHOLD ((uint8_t)6U)
433 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGSUM ((uint8_t)7U)
434 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGDIFFSUM ((uint8_t)8U)
435 #define HWA_CLIPREG_TYPE_TWIDINCR_DELTAFRAC ((uint8_t)9U)
436 #define HWA_CLIPREG_TYPE_CHANCOMB ((uint8_t)10U)
437 #define HWA_CLIPREG_TYPE_FFT ((uint8_t)11U)
438 #define HWA_CLIPREG_TYPE_INPUTFORMAT ((uint8_t)12U)
439 #define HWA_CLIPREG_TYPE_OUTPUTFORMAT ((uint8_t)13U)
447 #define HWA_ACCUMULATORREG_TYPE_DC ((uint8_t)0U)
448 #define HWA_ACCUMULATORREG_TYPE_INTERF_MAG ((uint8_t)1U)
449 #define HWA_ACCUMULATORREG_TYPE_INTERF_MAGDIFF ((uint8_t)2U)
450 #define HWA_ACCUMULATORREG_TYPE_INTERF ((uint8_t)3U)
458 #define HWA_INTERFERENCE_THRESHOLD_TYPE_MAG ((uint8_t)0U)
459 #define HWA_INTERFERENCE_THRESHOLD_TYPE_MAGDIFF ((uint8_t)1U)
469 #define HWA_PARAMDONE_INTERRUPT_TYPE_CPU_INTR1 ((uint8_t)1U)
470 #define HWA_PARAMDONE_INTERRUPT_TYPE_CPU_INTR2 ((uint8_t)2U)
471 #define HWA_PARAMDONE_INTERRUPT_TYPE_DMA ((uint8_t)4U)
480 #define HWA_COMMONCONFIG_MASK_STATEMACHINE_CFG ((uint64_t)0x00000001U)
481 #define HWA_COMMONCONFIG_MASK_STATEMACHINE_CFG_ALT ((uint64_t)0x00000002U)
482 #define HWA_COMMONCONFIG_CONTEXTSWITCH_TRIG_CFG ((uint64_t)0x00000004U)
483 #define HWA_COMMONCONFIG_MASK_BPMCFG ((uint64_t)0x00000008U)
484 #define HWA_COMMONCONFIG_MASK_TWIDDITHERENABLE ((uint64_t)0x00000010U)
485 #define HWA_COMMONCONFIG_MASK_LFSRSEED ((uint64_t)0x00000020U)
486 #define HWA_COMMONCONFIG_MASK_FFTSUMDIV ((uint64_t)0x00000040U)
487 #define HWA_COMMONCONFIG_MASK_CFARTHRESHOLDSCALE ((uint64_t)0x00000080U)
488 #define HWA_COMMONCONFIG_MASK_DCEST_SCALESHIFT ((uint64_t)0x00000100U)
489 #define HWA_COMMONCONFIG_MASK_DCSUB_SWVAL ((uint64_t)0x00000200U)
490 #define HWA_COMMONCONFIG_MASK_INTERFMAG_THRESHOLD ((uint64_t)0x00000400U)
491 #define HWA_COMMONCONFIG_MASK_INTERFMAGDIFF_THRESHOLD ((uint64_t)0x00000800U)
492 #define HWA_COMMONCONFIG_MASK_INTERFSUM_MAG ((uint64_t)0x00001000U)
493 #define HWA_COMMONCONFIG_MASK_INTERFSUM_MAGDIFF ((uint64_t)0x00002000U)
494 #define HWA_COMMONCONFIG_MASK_COMPLEXMULT_SCALEARRAY ((uint64_t)0x00004000U)
497 #define HWA_COMMONCONFIG_MASK_COMPLEXMULT_SCALECONST ((uint64_t)0x00008000U)
500 #define HWA_COMMONCONFIG_MASK_RECWIN_RESET ((uint64_t)0x00010000U)
501 #define HWA_COMMONCONFIG_MASK_TWIDINCR_DELTA_FRAC ((uint64_t)0x00020000U)
503 #define HWA_COMMONCONFIG_MASK_CHANCOMB_VEC_SIZE ((uint64_t)0x00400000U)
504 #define HWA_COMMONCONFIG_MASK_ZEROINSERT_NUM_MASK ((uint64_t)0x00800000U)
505 #define HWA_COMMONCONFIG_MASK_MAX2D_OFFSETBOTHDIM ((uint64_t)0x01000000U)
506 #define HWA_COMMONCONFIG_MASK_CDFCNT_THRESHOLD ((uint64_t)0x02000000U)
507 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMB_THRESHOLDSW ((uint64_t)0x04000000U)
508 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMC_THRESHOLDSW ((uint64_t)0x08000000U)
509 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMBTHRESH_OFFSET ((uint64_t)0x10000000U)
510 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMCTHRESH_OFFSET ((uint64_t)0x20000000U)
511 #define HWA_COMMONCONFIG_MASK_INTERF_MITG_WINDOW_PARAM ((uint64_t)0x40000000U)
512 #define HWA_COMMONCONFIG_MASK_EGECOMRESS_KPARAM ((uint64_t)0x80000000U)
514 #define HWA_COMMONCONFIG_MASK_CFAR_DET_THR ((uint64_t)0x1000000000U)
515 #if defined (SOC_AWR294X)
516 #define HWA_COMMONCONFIG_MASK_CMP_LFSRSEED0 ((uint64_t)0x200000000U)
517 #define HWA_COMMONCONFIG_MASK_CMP_LFSRSEED1 ((uint64_t)0x400000000U)
518 #define HWA_COMMONCONFIG_MASK_SW_RESTART_LOOP ((uint64_t)0x800000000U)
519 #endif
520 
528 #define HWA_SRC_SHUFFLE_AB_MODE_DISABLE ((uint8_t)0U)
529 #define HWA_SRC_SHUFFLE_AB_MODE_ADIM ((uint8_t)1U)
530 #define HWA_SRC_SHUFFLE_AB_MODE_BDIM ((uint8_t)2U)
538 #define HWA_COMPLEX_MULTIPLY_MODE_DISABLE ((uint8_t)0U)
539 #define HWA_COMPLEX_MULTIPLY_MODE_FREQ_SHIFTER ((uint8_t)1U)
540 #define HWA_COMPLEX_MULTIPLY_MODE_SLOW_DFT ((uint8_t)2U)
541 #define HWA_COMPLEX_MULTIPLY_MODE_FFT_STITCHING ((uint8_t)3U)
542 #define HWA_COMPLEX_MULTIPLY_MODE_MAG_SQUARED ((uint8_t)4U)
543 #define HWA_COMPLEX_MULTIPLY_MODE_SCALAR_MULT ((uint8_t)5U)
544 #define HWA_COMPLEX_MULTIPLY_MODE_VECTOR_MULT ((uint8_t)6U)
545 #define HWA_COMPLEX_MULTIPLY_MODE_VECTOR_MULT_2 ((uint8_t)7U)
546 #define HWA_COMPLEX_MULTIPLY_MODE_RECURSIVE_WIN ((uint8_t)8U)
547 #define HWA_COMPLEX_MULTIPLY_MODE_LUT_FREQ_DEROTATE ((uint8_t)9U)
548 #define HWA_COMPLEX_MULTIPLY_MODE_FREQSHIFT_FREQINCREMENT ((uint8_t)10U)
557 #define HWA_FFT_STITCHING_TWID_PATTERN_4K ((uint8_t)1U)
558 #define HWA_FFT_STITCHING_TWID_PATTERN_8K ((uint8_t)2U)
567 #define HWA_RECURSIVE_WIN_MODE_SELECT_ITERATION_COUNT ((uint8_t)0U)
568 #define HWA_FFT_STITCHING_TWID_PATTERN_EXE_COUNT ((uint8_t)1U)
576 #define HWA_WINDOW_MODE_18BITREAL ((uint8_t)0U)
578 #define HWA_WINDOW_MODE_16BITREAL ((uint8_t)1U)
580 #define HWA_WINDOW_MODE_COMPLEX ((uint8_t)2U)
589 #define HWA_FFT3x_BFLY_SCALING_MSBSATURATED ((uint8_t)0U)
590 #define HWA_FFT3x_BFLY_SCALING_MSBSATLSBRND ((uint8_t)1U)
592 #define HWA_FFT3x_BFLY_SCALING_LSBROUNDED ((uint8_t)2U)
601 #define HWA_DCEST_INTERFSUM_RESET_MODE_NOUPDATE ((uint8_t)0U)
602 #define HWA_DCEST_INTERFSUM_RESET_MODE_SOFTWARERESET ((uint8_t)1U)
603 #define HWA_DCEST_INTERFSUM_RESET_MODE_PARAMRESET ((uint8_t)2U)
604 #define HWA_DCEST_INTERFSUM_RESET_MODE_PARAMRESET_ZEROLPCONT ((uint8_t)3U)
612 #define HWA_INTERFTHRESH_MODE_MAG_OR_MAGDIF ((uint8_t)0U)
613 #define HWA_INTERFTHRESH_MODE_MAGDIFF ((uint8_t)1U)
614 #define HWA_INTERFTHRESH_MODE_MAG ((uint8_t)2U)
615 #define HWA_INTERFTHRESH_MODE_MAG_AND_MAGDIFF ((uint8_t)3U)
623 #define HWA_DCSUB_SELECT_DCSW ((uint8_t)0U)
624 #define HWA_DCSUB_SELECT_DCEST ((uint8_t)1U)
632 #define HWA_INTERFTHRESH_SELECT_SW ((uint8_t)0U)
634 #define HWA_INTERFTHRESH_SELECT_EST_AVERAGE ((uint8_t)1U)
636 #define HWA_INTERFTHRESH_SELECT_EST_INDIVIDUAL ((uint8_t)2U)
645 #define HWA_INTERFMITIGATION_PATH_ZEROOUT ((uint8_t)0U)
646 #define HWA_INTERFMITIGATION_PATH_WINDOWZEROOUT ((uint8_t)1U)
647 #define HWA_INTERFMITIGATION_PATH_LINEARINTERPOLATION ((uint8_t)2U)
648 #define HWA_INTERFMITIGATION_PATH_UNUSED ((uint8_t)3U)
659 #define HWA_LUT_FREQ_DEROTATE_RAMIDX_AUTOINCR_WRAPAROUND ((uint8_t)0U)
660 #define HWA_LUT_FREQ_DEROTATE_RAMIDX_AUTOINCR_SATURATED ((uint8_t)1U)
661 #define HWA_LUT_FREQ_DEROTATE_RAMIDX_NONINCR ((uint8_t)2U)
669 #define HWA_HISTOGRAM_MODE_DISABLED ((uint8_t)0U)
670 #define HWA_HISTOGRAM_MODE_HISTOGRAM ((uint8_t)1U)
671 #define HWA_HISTOGRAM_MODE_CDF ((uint8_t)2U)
672 #define HWA_HISTOGRAM_MODE_CDF_THRESHOLD ((uint8_t)3U)
680 #define HWA_LOCALMAX_THRESH_BITMASK_BOTH_EN ((uint8_t)0U)
681 #define HWA_LOCALMAX_THRESH_BITMASK_CDIM_EN ((uint8_t)1U)
682 #define HWA_LOCALMAX_THRESH_BITMASK_BDIM_EN ((uint8_t)2U)
683 #define HWA_LOCALMAX_THRESH_BITMASK_BOTH_DIS ((uint8_t)3U)
691 #define HWA_LOCALMAX_THRESH_SELECT_DIMBREG_DIMCREG ((uint8_t)0U)
692 #define HWA_LOCALMAX_THRESH_SELECT_DIMBRAM_DIMCREG ((uint8_t)1U)
693 #define HWA_LOCALMAX_THRESH_SELECT_DIMBREG_DIMCRAM ((uint8_t)2U)
694 #define HWA_LOCALMAX_THRESH_SELECT_DIMBRAM_DIMCRAM ((uint8_t)3U)
702 #define HWA_COMPRESS_METHOD_EGE ((uint8_t)0U)
703 #define HWA_COMPRESS_METHOD_BFP ((uint8_t)1U)
711 #define HWA_CMP_DCMP_COMPRESS ((uint8_t)0U)
712 #define HWA_CMP_DCMP_DECOMPRESS ((uint8_t)1U)
720 #define HWA_COMPRESS_PATHSELECT_BOTHPASSES ((uint8_t)3U)
721 #define HWA_COMPRESS_PATHSELECT_SECONDPASS ((uint8_t)1U)
733 #define HWA_PARAMSET_CONTEXTSWITCH_DISABLE (0U)
734 
735 #define HWA_PARAMSET_CONTEXTSWITCH_NONFORCE_ENABLE (1U)
736 
738 #define HWA_PARAMSET_CONTEXTSWITCH_FORCE_ENABLE (2U)
739 
747 #define HWA_APP_MEMINIT_PARAM_RAM (1U << 8U)
748 
749 #define HWA_APP_MEMINIT_WINDOW_RAM (1U << 9U)
750 
751 #define HWA_APP_MEMINIT_PER_SAMPLE_MAX_VAL_EVEN_RAM (1U << 10U)
752 
753 #define HWA_APP_MEMINIT_PER_SAMPLE_MAX_VAL_ODD_RAM (1U << 11U)
754 
755 #define HWA_APP_MEMINIT_PER_ITER_MAX_VAL_RAM (1U << 12U)
756 
757 #define HWA_APP_MEMINIT_HIST_EVEN_RAM (1U << 13U)
758 
759 #define HWA_APP_MEMINIT_HIST_ODD_RAM (1U << 14U)
760 
761 #define HWA_APP_MEMINIT_MEMBANK_ALL (HWA_APP_MEMINIT_PARAM_RAM | \
762  HWA_APP_MEMINIT_WINDOW_RAM | \
763  HWA_APP_MEMINIT_PER_SAMPLE_MAX_VAL_EVEN_RAM | \
764  HWA_APP_MEMINIT_PER_SAMPLE_MAX_VAL_ODD_RAM | \
765  HWA_APP_MEMINIT_PER_ITER_MAX_VAL_RAM | \
766  HWA_APP_MEMINIT_HIST_EVEN_RAM | \
767  HWA_APP_MEMINIT_HIST_ODD_RAM )
768 
770 /* ========================================================================== */
771 /* Structures and Enums */
772 /* ========================================================================== */
773 
777 typedef void* HWA_Handle;
778 
785 typedef void (*HWA_ParamDone_IntHandlerFuncPTR)(uint32_t intrIdx, uint32_t paramSet, void * arg);
786 
793 typedef void (*HWA_Done_IntHandlerFuncPTR)(uint32_t threadIdx, void * arg);
794 
801 typedef struct HWA_Attrs_t {
802  uint32_t instanceNum;
803  volatile uint32_t ctrlBaseAddr;
804  volatile uint32_t paramBaseAddr;
805  volatile uint32_t ramBaseAddr;
806  volatile uint32_t dssBaseAddr;
807  uint32_t numHwaParamSets;
808  uint32_t intNum1ParamSet;
809  uint32_t intNum2ParamSet;
810  uint32_t intNumDone;
811  uint32_t intNumDoneALT;
812  uint32_t intNumLocalRamErr;
813  uint32_t numDmaChannels;
814  volatile uint32_t accelMemBaseAddr;
815  uint32_t accelMemSize;
816  bool isConcurrentAccessAllowed;
818 } HWA_Attrs;
819 
826 typedef struct HWA_RAMAttrs_t
827 {
828  uint32_t ramBaseAddress;
829  uint32_t ramSizeInBytes;
830 } HWA_RAMAttrs;
831 
843 typedef struct HWA_SrcDMAConfig_t {
844  uint32_t srcAddr;
845  uint32_t destAddr;
846  uint16_t aCnt;
847  uint16_t bCnt;
848  uint16_t cCnt;
850 
857 typedef struct HWA_CommonConfig_t {
858  uint64_t configMask;
861  uint16_t numLoops;
865  uint16_t paramStartIdx;
868  uint16_t paramStopIdx;
871  uint16_t numLoopsALT;
874  uint16_t paramStartIdxALT;
877  uint16_t paramStopIdxALT;
880  uint8_t contextswitchTriggerMode;
883  uint8_t contextswitchTriggerSrc;
887 #if defined (SOC_AWR294X)
888  /* This Field is applicable for only AWR294x ES2.0 devices */
889  uint8_t swRestartLoop;
891 #endif
892  struct {
893  uint16_t bpmRate;
897  uint32_t bpmPattern[HWA_BPMPATTERN_LENGTH_INWORDS];
903  uint8_t twidDitherEnable;
908  uint32_t lfsrSeed;
911  uint8_t fftSumDiv;
915  } fftConfig;
916 
917 
918  struct {
919  uint16_t scale;
925  uint8_t shift;
930  } dcEstimateConfig;
931 
932  struct
933  {
934  int32_t swIVal[HWA_NUM_RXCHANNELS];
939  int32_t swQVal[HWA_NUM_RXCHANNELS];
943  } dcSubtractConfig;
944 
945 
946  struct {
947 
948  uint32_t thresholdMagSw[HWA_NUM_RXCHANNELS];
956  uint32_t thresholdMagDiffSw[HWA_NUM_RXCHANNELS];
964  uint8_t sumMagScale;
971  int8_t sumMagShift;
976  uint8_t sumMagDiffScale;
981  int8_t sumMagDiffShift;
986  uint8_t mitigationWindowParam[HWA_NUM_INTERFMITG_WINARRAY];
992  } interfConfig;
993 
994 
995  struct {
996 
997  int32_t Iscale[HWA_NUM_RXCHANNELS];
1003  int32_t Qscale[HWA_NUM_RXCHANNELS];
1009  int16_t twiddleDeltaFrac;
1017  uint8_t recWindowReset;
1020  } complexMultiplyConfig;
1022  struct {
1023 
1024  uint8_t size;
1028  uint32_t vector[HWA_CHANCOMB_LENGTH_INWORDS];
1036  } chanCombConfig;
1038  struct {
1039 
1040  uint8_t number;
1044  uint32_t mask[HWA_ZEROINSERT_LENGTH_INWORDS];
1051  } zeroInsertConfig;
1053  struct {
1054 
1055  uint32_t thresholdScale;
1062  } cfarConfig;
1064  struct {
1065 
1066  uint32_t cfarDetthreshold;
1071  } cfarDetThresConfig;
1073  struct {
1074 
1075  int32_t max2DoffsetDim1;
1079  int32_t max2DoffsetDim2;
1084  uint16_t cdfCntThresh;
1090  } advStatConfig;
1092  struct {
1093 
1094  uint16_t dimBThreshold;
1099  uint16_t dimCThreshold;
1104  uint16_t dimBBaseAddress;
1109  uint16_t dimCBaseAddress;
1113  } localMaxConfig;
1115  struct {
1116 
1117  uint8_t EGEKparam[HWA_CMP_K_ARR_LEN];
1122 #if defined (SOC_AWR294X) /* These fields are applicable for only ES2.0 devices. */
1123  uint32_t cmpLfsrSeed0;
1125  uint32_t cmpLfsrSeed1;
1127 #endif
1128 
1129  } compressConfig;
1130 
1132 
1139 typedef struct HWA_SourceConfig_t {
1140  uint32_t srcAddr;
1145  uint16_t srcAcnt;
1149  int32_t srcAIdx;
1152  uint16_t srcBcnt;
1154  int32_t srcBIdx;
1158  uint16_t srcCcnt;
1160  int32_t srcCIdx;
1164  uint16_t srcAcircShift;
1168  uint8_t srcAcircShiftWrap;
1175  uint16_t srcBcircShift;
1178  uint8_t srcBcircShiftWrap;
1185  uint16_t srcCcircShift;
1189  uint8_t srcCcircShiftWrap;
1196  uint8_t srcCircShiftWrap3;
1200  uint8_t shuffleMode ;
1203  uint8_t srcRealComplex;
1206  uint8_t srcWidth;
1209  uint8_t srcSign;
1216  uint8_t srcConjugate;
1225  uint8_t srcScale;
1232  uint8_t srcIQSwap;
1235  uint32_t wrapComb;
1239  uint8_t shuffleStart;
1243 
1250 typedef struct HWA_DestConfig_t {
1251 
1252  uint32_t dstAddr;
1257  uint16_t dstAcnt;
1262  int32_t dstAIdx;
1266  int32_t dstBIdx;
1271  uint8_t dstRealComplex;
1275  uint8_t dstWidth;
1279  uint8_t dstSign;
1286  uint8_t dstConjugate;
1295  uint8_t dstScale;
1298  uint16_t dstSkipInit;
1304  uint8_t dstIQswap; /* See \ref HWA_FEATURE_BIT macros for correct values
1305  sets bits DST_IQSWAP of register DST in paramset */
1306 } HWA_DestConfig;
1307 
1314 typedef struct HWA_PostProcStat_t {
1315 
1316  uint8_t magLogEn;
1321  uint8_t fftOutMode;
1329  uint8_t max2Denable;
1333  uint8_t histogramMode;
1338  uint8_t histogramScaleSelect;
1343  uint8_t histogramSizeSelect;
1348 
1355 typedef struct HWA_ComplexMultiply_t {
1356 
1357  uint8_t cmultMode;
1362  union {
1363  struct
1364  {
1365  uint16_t freqShiftTwiddleIncr;
1368  } freqShift;
1370  struct
1371  {
1372  uint16_t startFreq;
1377  } slowDFT;
1379  struct
1380  {
1381  uint16_t twiddlePattern;
1386  uint8_t winInterpolateMode;
1392  } FFTstitching;
1394  struct
1395  {
1396  uint8_t scaleCmultScaleEn;
1406  } scalerMultiply;
1408  struct
1409  {
1410  uint8_t cmultScaleEn;
1417  uint16_t vecMultiMode1RamAddrOffset;
1419  } vectorMultiplyMode1;
1421  struct
1422  {
1423  uint16_t vecMultiMode2RamAddrOffset;
1427  } vectorMultiplyMode2;
1429  struct
1430  {
1431  uint8_t recwinModeSel;
1434  } recursiveWin;
1436  struct
1437  {
1438  uint16_t ramAddrOffset;
1440  uint8_t ramIdxIncrMode;
1443  } lutFreqDerotate;
1445  struct
1446  {
1447  uint16_t twiddleIncr;
1450  } freqShiftWithFreIncrement;
1451  } modeCfg ;
1453 
1460 typedef struct HWA_PreProcessing_t {
1461 
1462  uint8_t dcEstResetMode;
1467  uint8_t dcSubEnable;
1471  uint8_t dcSubSelect;
1474  struct {
1475  uint8_t thresholdEnable;
1479  uint8_t thresholdMode;
1483  uint8_t thresholdSelect;
1488  } interfLocalize;
1489 
1490  struct {
1491  uint8_t resetMode;
1496  } interfStat;
1498  struct {
1499 
1500  uint8_t enable;
1504  uint8_t countThreshold;
1509  uint8_t pathSelect;
1513  uint8_t leftHystOrder;
1517  uint8_t rightHystOrder;
1521  } interfMitigation;
1522 
1523  uint8_t chanCombEn;
1528  uint8_t zeroInsertEn;
1533  HWA_ComplexMultiply complexMultiply;
1536 
1543 typedef struct HWA_AccelModeFFT_t{
1544  uint8_t fftEn;
1549  uint8_t fftSize;
1556  uint16_t butterflyScaling;
1563  uint8_t windowEn;
1567  uint16_t windowStart;
1572  uint8_t winSymm;
1577  uint8_t windowMode;
1580  uint8_t fftSize3xEn;
1585  uint8_t fftSizeDim2;
1590  uint8_t butterflyScalingFFT3x;
1595  uint8_t bpmEnable;
1601  uint8_t bpmPhase;
1604  HWA_PostProcStat postProcCfg;
1606  HWA_PreProcessing preProcCfg;
1608 
1615 typedef struct HWA_AccelModeCFAR_t{
1616  uint8_t numNoiseSamplesLeft;
1622  uint8_t numNoiseSamplesRight;
1627  uint8_t numGuardCells;
1629  uint8_t nAvgDivFactor;
1635  uint8_t nAvgMode;
1639  uint8_t cfarOsKvalue;
1642  uint8_t cfarOsEdgeKScaleEn;
1646  uint8_t operMode;
1649  uint8_t outputMode;
1653  uint8_t cfarAdvOutMode;
1658  uint8_t peakGroupEn;
1667  uint8_t cyclicModeEn;
1673 
1680 typedef struct HWA_AccelModeLocalMax_t{
1681 
1682  uint8_t neighbourBitmask;
1686  uint8_t thresholdBitMask;
1690  uint8_t thresholdMode;
1693  uint8_t dimBNonCyclic;
1695  uint8_t dimCNonCyclic;
1698 
1705 typedef struct HWA_AccelModeCompress_t {
1706  uint8_t EGEKidx;
1709  uint8_t EGEKarrayLength;
1712  uint8_t scaleFactorBW;
1717  uint8_t BFPMantissaBW;
1720  uint8_t scaleFactor;
1722  uint8_t passSelect;
1724  uint8_t headerEnable;
1728  uint8_t method;
1731  uint8_t compressDecompress;
1733  uint8_t ditherEnable;
1736 #if defined (SOC_AWR294X)
1737  /* These fields are applicable for only AWR294x ES2.0 devices. */
1738  uint8_t decrImagBitw;
1740  uint8_t cmpRoundEn;
1742  uint8_t selLfsr;
1744 #endif
1746 
1753 typedef struct HWA_ParamConfig_t {
1754  uint8_t triggerMode;
1756  uint8_t triggerSrc;
1762  uint8_t accelMode;
1767  HWA_SourceConfig source;
1770  union {
1773  HWA_AccelModeLocalMax localMaxMode;
1774  HWA_AccelModeCompress compressMode;
1775  } accelModeArgs;
1776 
1777  uint8_t contextswitchCfg;
1779 } HWA_ParamConfig;
1780 
1787 typedef struct HWA_InterruptConfig_t {
1788  uint8_t interruptTypeFlag;
1794  struct {
1795  HWA_ParamDone_IntHandlerFuncPTR callbackFn;
1796  void *callbackArg;
1797  } cpu;
1798  struct {
1799  uint8_t dstChannel;
1801  } dma;
1803 
1810 typedef struct HWA_Stats_t {
1811  uint32_t maxValue;
1812  uint16_t maxIndex;
1813  uint8_t iSumMSB;
1814  uint8_t qSumMSB;
1815  uint32_t iSumLSB;
1816  uint32_t qSumLSB;
1817 } HWA_Stats;
1818 
1823 typedef struct HWA_AccmulatorVal_t {
1824  uint32_t accValLSB;
1825  uint16_t accValMSB;
1827 
1834 typedef struct HWA_DebugStats_t {
1835  uint8_t currentParamSet;
1840  uint8_t paramSetIdxCpuIntr0;
1841  uint8_t paramSetIdxCpuIntr1;
1852  uint8_t fsmStateInfo;
1853  uint16_t currentLoopCount;
1855  uint16_t otherThreadLoopCount;
1856  uint32_t trigStatus[2];
1857 } HWA_DebugStats;
1858 
1865 typedef struct HWA_MemInfo_t {
1866  uint32_t baseAddress;
1867  uint16_t bankSize;
1868  uint16_t numBanks;
1869 } HWA_MemInfo;
1870 
1877 typedef struct HWA_CdfThreshold_t {
1879  uint32_t pdfValue : 12;
1880  uint32_t cdfValue : 12;
1881  uint32_t binNumber : 6;
1882  uint32_t reserved : 2;
1885 
1890 typedef struct HWA_InterruptPriority_t {
1892  uint32_t backgroundDone;
1893  uint32_t ALTDone;
1894  uint32_t paramsetDone1;
1895  uint32_t paramsetDone2;
1896  uint32_t loalRamErr;
1899 
1904 typedef struct HWA_OpenConfig_t {
1905 
1906  HWA_InterruptPriority interruptPriority ;
1919 } HWA_OpenConfig;
1920  /* end of HWA_DRIVER_EXTERNAL_DATA_STRUCTURE*/
1922 
1923 /* ========================================================================== */
1924 /* Internal/Private Structure Declarations */
1925 /* ========================================================================== */
1926 
1935 typedef struct HWA_InterruptCtx_t {
1936  HWA_ParamDone_IntHandlerFuncPTR callbackFn;
1937  void *callbackArg;
1939 
1948 typedef struct HWA_DoneInterruptCtx_t {
1949  bool bIsEnabled;
1950  HWA_Done_IntHandlerFuncPTR callbackFn;
1951  void *callbackArg;
1953 
1957 typedef struct HWA_Driver_t {
1961  uint32_t instanceNum;
1965  uint32_t refCnt;
1970  uint8_t configInProgress;
1976  uint16_t paramSetMapInProgress;
1980  HWA_Attrs const *hwAttrs;
1981 
1985  HwiP_Object hwiHandleParamSet;
1986 
1990  HwiP_Object hwiHandleDone;
1991 
1995  HwiP_Object hwiHandleParamSetALT;
1996 
2000  HwiP_Object hwiHandleDoneALT;
2001 
2005  HwiP_Object hwiHandleLocalRamErr;
2006 
2010  HWA_InterruptCtx *interruptCtxParamSet; /*[NUM_HWA_PARAMSETS_PER_INSTANCE];*/
2011 
2015  uint64_t interrupt1ParamSetMask;
2016 
2020  uint64_t interrupt2ParamSetMask;
2021 
2022 
2026  HWA_DoneInterruptCtx interruptCtxDone;
2027 
2031  HWA_DoneInterruptCtx interruptCtxDoneALT;
2032 
2033 #if defined (SOC_AWR294X)
2034 
2037  bool isES2P0Device;
2038 #endif
2039 } HWA_Object;
2040 
2042 extern HWA_Attrs gHwaAttrs[];
2046 extern HWA_Object gHwaObject[];
2048 extern HWA_Object *gHwaObjectPtr[];
2050 extern uint32_t gHwaConfigNum;
2051 
2052 /* ========================================================================== */
2053 /* Global Variables Declarations */
2054 /* ========================================================================== */
2055 
2056 /* None */
2057 
2058 /* ========================================================================== */
2059 /* Function Declarations */
2060 /* ========================================================================== */
2061 
2072 extern void HWA_init(void);
2073 
2077 extern void HWA_deinit(void);
2078 
2096 extern HWA_Handle HWA_open(uint32_t index, HWA_OpenConfig * hwaCfg, int32_t* errCode);
2097 
2109 extern int32_t HWA_close(HWA_Handle handle);
2110 
2122 extern int32_t HWA_reset(HWA_Handle handle);
2123 
2145 extern int32_t HWA_initializeRAM(HWA_Handle handle, uint32_t ramMemBankMask);
2146 
2159 extern DSSHWACCRegs *HWA_getCommonCtrlAddr(HWA_Handle handle);
2160 
2175 extern DSSHWACCPARAMRegs *HWA_getParamSetAddr(HWA_Handle handle, uint8_t paramsetIdx);
2176 
2191 extern int32_t HWA_configCommon(HWA_Handle handle, HWA_CommonConfig *commonConfig);
2192 
2212 extern int32_t HWA_configParamSet(HWA_Handle handle, uint8_t paramsetIdx, HWA_ParamConfig *paramConfig, HWA_SrcDMAConfig *dmaConfig);
2213 
2236 extern int32_t HWA_getDMAconfig(HWA_Handle handle, uint8_t dmaTriggerSrc, HWA_SrcDMAConfig *dmaConfig);
2237 
2257 extern int32_t HWA_configRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx);
2258 
2268 extern uint32_t HWA_getRamAddress(uint8_t ramType);
2269 
2290 extern int32_t HWA_readRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx);
2291 
2310 extern int32_t HWA_readHistThresholdRam(HWA_Handle handle, HWA_CdfThreshold *cdfThresholdResult, uint8_t numSampleIndices, uint8_t startSampleIdx);
2311 
2329 extern int32_t HWA_enableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, HWA_InterruptConfig *intrConfig);
2330 
2347 extern int32_t HWA_paramSetDonePolling(HWA_Handle handle, uint8_t numParamSets, uint8_t *paramsetsArray);
2348 
2363 extern int32_t HWA_singleParamSetDonePolling(HWA_Handle handle, uint8_t paramsetIndex);
2364 
2382 extern int32_t HWA_enableDoneInterrupt(HWA_Handle handle, uint8_t threadIdx, HWA_Done_IntHandlerFuncPTR callbackFn, void * callbackArg);
2383 
2399 extern int32_t HWA_disableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, uint8_t interruptTypeFlag);
2400 
2414 extern int32_t HWA_disableDoneInterrupt(HWA_Handle handle, uint8_t threadIdx);
2415 
2430 extern int32_t HWA_enable(HWA_Handle handle, uint8_t flagEnDis);
2431 
2445 extern int32_t HWA_enableContextSwitch(HWA_Handle handle, uint8_t flagEnDis);
2446 
2463 extern int32_t HWA_setSoftwareTrigger(HWA_Handle handle, uint8_t swTriggerType);
2464 
2477 extern int32_t HWA_setContextswitchSoftwareTrigger(HWA_Handle handle);
2478 
2492 extern int32_t HWA_setContextswitchDMAManualTrigger(HWA_Handle handle,uint8_t idx);
2493 
2507 extern int32_t HWA_softwareResetAccumulators(HWA_Handle handle, uint8_t accumulatortype);
2508 
2520 extern int32_t HWA_softwareResetRecursiveWinKvalue(HWA_Handle handle);
2521 
2533 extern int32_t HWA_softwareResetTwidIncrDeltaFrac(HWA_Handle handle);
2534 
2548 extern int32_t HWA_setDMA2ACCManualTrig(HWA_Handle handle, uint8_t idx);
2549 
2565 extern int32_t HWA_setSourceAddress(HWA_Handle handle, uint16_t paramIdx, uint32_t sourceAddress);
2566 
2592 extern int32_t HWA_readClipStatus(HWA_Handle handle, uint16_t *clipStatusResult, uint8_t type);
2593 
2606 extern int32_t HWA_clearClipStatus(HWA_Handle handle, uint8_t type);
2607 
2626 extern int32_t HWA_readStatsReg(HWA_Handle handle, HWA_Stats *pStats, uint8_t numIter);
2627 
2645 extern int32_t HWA_readCFARPeakCountReg(HWA_Handle handle, uint8_t *pbuf, uint8_t size);
2646 
2661 extern int32_t HWA_readDebugReg(HWA_Handle handle, HWA_DebugStats *pStats);
2662 
2674 extern int32_t HWA_clearDebugReg(HWA_Handle handle);
2675 
2690 extern int32_t HWA_getHWAMemInfo(HWA_Handle handle, HWA_MemInfo *memInfo);
2691 
2709 extern int32_t HWA_getDMAChanIndex(HWA_Handle handle, uint8_t edmaChanId, uint8_t *hwaDestChan);
2710 
2726 extern int32_t HWA_getEDMAChanId(HWA_Handle handle, uint8_t hwaDMAdestChan);
2727 
2747 extern int32_t HWA_readDCEstimateReg(HWA_Handle handle, cmplx32ImRe_t *pbuf, uint8_t startIdx, uint8_t size);
2748 
2769 extern int32_t HWA_readIntfAccReg(HWA_Handle handle, uint64_t *accBuf, uint8_t type, uint8_t startIdx, uint8_t size);
2770 
2789 extern int32_t HWA_readDCAccReg(HWA_Handle handle, cmplx64ImRe_t *accbuf, uint8_t startIdx, uint8_t size);
2790 
2804 extern int32_t HWA_readInterfChirpCountReg(HWA_Handle handle, uint16_t *numInterfSamplesChirp);
2805 
2819 extern int32_t HWA_readInterfFrameCountReg(HWA_Handle handle, uint32_t *numInterfSamplesFrame);
2820 
2840 extern int32_t HWA_readInterfThreshReg(HWA_Handle handle, uint32_t *pbuf, uint8_t startIdx, uint8_t size, uint8_t type);
2841 
2854 extern int32_t HWA_controlPeripheralSuspendMode(HWA_Handle handle, uint8_t flagEnDis);
2855 
2868 extern int32_t HWA_configureSingleStep(HWA_Handle handle, uint8_t flagEnDis);
2869 
2881 extern int32_t HWA_triggerSingleStep(HWA_Handle handle);
2882  /* end of addgroup HWA_DRIVER_EXTERNAL_FUNCTION*/
2884 
2885 #ifdef __cplusplus
2886 }
2887 #endif
2888 
2889 #endif /* HWA_H_ */
2890 
2891 
HWA_CHANCOMB_LENGTH_INWORDS
#define HWA_CHANCOMB_LENGTH_INWORDS
The length of channel combining vector in words.
Definition: hwa/v0/hwa.h:181
HWA_SourceConfig
HWA Paramset Config for Input Formatter/Source block.
Definition: hwa/v0/hwa.h:1136
HWA_AccmulatorVal
HWA Accumulator register value data structure.
Definition: hwa/v0/hwa.h:1820
HWA_readInterfThreshReg
int32_t HWA_readInterfThreshReg(HWA_Handle handle, uint32_t *pbuf, uint8_t startIdx, uint8_t size, uint8_t type)
Function to read the interference statistics INTF_LOC_THRESH_MAG_VAL or INTF_LOC_THRESH_MAG_VAL regis...
HWA_enable
int32_t HWA_enable(HWA_Handle handle, uint8_t flagEnDis)
Function to enable the state machine of the HWA. This should be called after paramset and RAM have be...
HWA_disableDoneInterrupt
int32_t HWA_disableDoneInterrupt(HWA_Handle handle, uint8_t threadIdx)
Function to disable the CPU interrupt after all programmed paramSets have been completed.
HWA_reset
int32_t HWA_reset(HWA_Handle handle)
Function to reset the internal state machine of the HWA.
HWA_AccelModeFFT
HWA Paramset Config for FFT block.
Definition: hwa/v0/hwa.h:1540
HWA_setDMA2ACCManualTrig
int32_t HWA_setDMA2ACCManualTrig(HWA_Handle handle, uint8_t idx)
Function to manually trigger the execution of the state machine waiting on DMA via software.
HWA_configureSingleStep
int32_t HWA_configureSingleStep(HWA_Handle handle, uint8_t flagEnDis)
Function to enable/disable single-stepping approach which pauses the HWA execution after each param-s...
HWA_clearDebugReg
int32_t HWA_clearDebugReg(HWA_Handle handle)
Function to clear the debug registers (acc_trig_in_clr)
HWA_MemInfo
HWA Local memory Information.
Definition: hwa/v0/hwa.h:1862
gHwaConfigNum
uint32_t gHwaConfigNum
Externally defined driver configuration array size.
HWA_paramSetDonePolling
int32_t HWA_paramSetDonePolling(HWA_Handle handle, uint8_t numParamSets, uint8_t *paramsetsArray)
Function to poll the PARAM_DONE_SET_STATUS_0 and PARAM_DONE_SET_STATUS_1 registers to check if the sp...
HWA_open
HWA_Handle HWA_open(uint32_t index, HWA_OpenConfig *hwaCfg, int32_t *errCode)
Function to initialize HWA specified by the particular index value.
HWA_getDMAChanIndex
int32_t HWA_getDMAChanIndex(HWA_Handle handle, uint8_t edmaChanId, uint8_t *hwaDestChan)
Function to get the dma destination index with a given EDMA channel number This function assumes the ...
HWA_enableParamSetInterrupt
int32_t HWA_enableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, HWA_InterruptConfig *intrConfig)
Function to enable the CPU and/or DMA interrupt after a paramSet completion. The CPU interrupt for ev...
HWA_ComplexMultiply
HWA Paramset Config for ComplexMultiply block.
Definition: hwa/v0/hwa.h:1352
HWA_ParamDone_IntHandlerFuncPTR
void(* HWA_ParamDone_IntHandlerFuncPTR)(uint32_t intrIdx, uint32_t paramSet, void *arg)
HWA Interrupt callback function after every paramset completion.
Definition: hwa/v0/hwa.h:782
HWA_AccelModeCFAR
HWA Paramset Config for CFAR block.
Definition: hwa/v0/hwa.h:1612
HWA_init
void HWA_init(void)
Function to initialize the HWA module.
gHwaAttrs
HWA_Attrs gHwaAttrs[]
Externally defined driver configuration array.
HWA_CMP_K_ARR_LEN
#define HWA_CMP_K_ARR_LEN
The length of EGE compression/decompression K-paramseters array.
Definition: hwa/v0/hwa.h:189
HWA_OpenConfig
HWA configuration structure, which describes the configuration information, needed for hwa handle ope...
Definition: hwa/v0/hwa.h:1901
HWA_softwareResetTwidIncrDeltaFrac
int32_t HWA_softwareResetTwidIncrDeltaFrac(HWA_Handle handle)
Function resets the execution counter if complex multiply is configured as frequency shifter mode wit...
HWA_setContextswitchDMAManualTrigger
int32_t HWA_setContextswitchDMAManualTrigger(HWA_Handle handle, uint8_t idx)
Function to manually trigger the execution of the state machine via DMA trigger in context switch.
HWA_ZEROINSERT_LENGTH_INWORDS
#define HWA_ZEROINSERT_LENGTH_INWORDS
The length of zero insert mask in words.
Definition: hwa/v0/hwa.h:183
HWA_getDMAconfig
int32_t HWA_getDMAconfig(HWA_Handle handle, uint8_t dmaTriggerSrc, HWA_SrcDMAConfig *dmaConfig)
Function to get the config to program the DMA for a given DMA Trigger channel. Application should use...
HWA_DebugStats
HWA Debug statistics.
Definition: hwa/v0/hwa.h:1831
HWA_readInterfFrameCountReg
int32_t HWA_readInterfFrameCountReg(HWA_Handle handle, uint32_t *numInterfSamplesFrame)
Function to read the number of samples that exceeded the threshold in a frame.
HWA_close
int32_t HWA_close(HWA_Handle handle)
Function to close a HWA peripheral specified by the HWA handle.
HWA_readHistThresholdRam
int32_t HWA_readHistThresholdRam(HWA_Handle handle, HWA_CdfThreshold *cdfThresholdResult, uint8_t numSampleIndices, uint8_t startSampleIdx)
Function to read the HWA HWA_RAM_TYPE_HIST_THRESH_RAM RAM.
HWA_enableContextSwitch
int32_t HWA_enableContextSwitch(HWA_Handle handle, uint8_t flagEnDis)
Function to enable or disable the context switching in hwa.
HWA_readCFARPeakCountReg
int32_t HWA_readCFARPeakCountReg(HWA_Handle handle, uint8_t *pbuf, uint8_t size)
Function to read the PEAKCNT register.
HWA_getParamSetAddr
DSSHWACCPARAMRegs * HWA_getParamSetAddr(HWA_Handle handle, uint8_t paramsetIdx)
Function to returns the HWA paramSet base address.
HWA_readDCAccReg
int32_t HWA_readDCAccReg(HWA_Handle handle, cmplx64ImRe_t *accbuf, uint8_t startIdx, uint8_t size)
Function to read the DC estimation accumulator register,.
HWA_BPMPATTERN_LENGTH_INWORDS
#define HWA_BPMPATTERN_LENGTH_INWORDS
The length of BPM Pattern sequence in words.
Definition: hwa/v0/hwa.h:179
HWA_getEDMAChanId
int32_t HWA_getEDMAChanId(HWA_Handle handle, uint8_t hwaDMAdestChan)
Function to get the edma EDMA channel number from a given HWA paramset destination channel....
HWA_enableDoneInterrupt
int32_t HWA_enableDoneInterrupt(HWA_Handle handle, uint8_t threadIdx, HWA_Done_IntHandlerFuncPTR callbackFn, void *callbackArg)
Function to enable the CPU interrupt after all programmed paramSets have been completed in the backgr...
HWA_setSoftwareTrigger
int32_t HWA_setSoftwareTrigger(HWA_Handle handle, uint8_t swTriggerType)
Function to manually trigger the execution of the state machine via software, the software trigger th...
HWA_setContextswitchSoftwareTrigger
int32_t HWA_setContextswitchSoftwareTrigger(HWA_Handle handle)
Function to manually trigger the execution of the state machine via software in context switch,...
HWA_getCommonCtrlAddr
DSSHWACCRegs * HWA_getCommonCtrlAddr(HWA_Handle handle)
Function to returns the HWA common control base address.
gHwaRamCfg
HWA_RAMAttrs gHwaRamCfg[HWA_NUM_RAMS]
Externally defined driver RAM configuration array.
HWA_Done_IntHandlerFuncPTR
void(* HWA_Done_IntHandlerFuncPTR)(uint32_t threadIdx, void *arg)
HWA Interrupt callback function after all paramsets completion.
Definition: hwa/v0/hwa.h:790
HWA_PreProcessing
HWA Paramset Config for pre-processing block.
Definition: hwa/v0/hwa.h:1457
HWA_initializeRAM
int32_t HWA_initializeRAM(HWA_Handle handle, uint32_t ramMemBankMask)
Function to initialize RAM memory banks in HWA.
HWA_getRamAddress
uint32_t HWA_getRamAddress(uint8_t ramType)
Function to get the RAM starting address for one specified RAM type.
HWA_configCommon
int32_t HWA_configCommon(HWA_Handle handle, HWA_CommonConfig *commonConfig)
Function to set the common HWA configuration parameters needed for the next operations/iterations/par...
HwiP.h
HWA_NUM_RXCHANNELS
#define HWA_NUM_RXCHANNELS
Number of RX channels in pre-processing block.
Definition: hwa/v0/hwa.h:175
HWA_getHWAMemInfo
int32_t HWA_getHWAMemInfo(HWA_Handle handle, HWA_MemInfo *memInfo)
Function to get HWA processing Memory information including address, size and number of banks.
gHwaObject
HWA_Object gHwaObject[]
Externally defined driver object.
HWA_configRam
int32_t HWA_configRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx)
Function to set the HWA RAM : HWA_RAM_TYPE_WINDOW_RAM, HWA_RAM_TYPE_VECTORMULTIPLY_RAM,...
HWA_AccelModeLocalMax
HWA Paramset Config for Local maxima block.
Definition: hwa/v0/hwa.h:1677
HWA_InterruptPriority
HWA interrupt priority for HWA background thread done, ALT thread done, paramset done interrupt 1 and...
Definition: hwa/v0/hwa.h:1887
HWA_readClipStatus
int32_t HWA_readClipStatus(HWA_Handle handle, uint16_t *clipStatusResult, uint8_t type)
Function to read the Clip Status registers.
HWA_configParamSet
int32_t HWA_configParamSet(HWA_Handle handle, uint8_t paramsetIdx, HWA_ParamConfig *paramConfig, HWA_SrcDMAConfig *dmaConfig)
Function to set the HWA configuration parameters for a given paramSet.
HWA_InterruptConfig
HWA Interrupt Config.
Definition: hwa/v0/hwa.h:1784
HWA_SrcDMAConfig
Source trigger DMA parameters.
Definition: hwa/v0/hwa.h:840
HWA_DoneInterruptCtx
HWA Interrupt context structure for done interrupt.
Definition: hwa/v0/hwa.h:1945
HWA_CommonConfig
HWA Common Config.
Definition: hwa/v0/hwa.h:854
HWA_disableParamSetInterrupt
int32_t HWA_disableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, uint8_t interruptTypeFlag)
Function to disable the CPU and/or DMA interrupt after a paramSet completion.
HwiP_Object
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
HWA_ParamConfig
HWA Paramset Config.
Definition: hwa/v0/hwa.h:1750
HWA_readDCEstimateReg
int32_t HWA_readDCEstimateReg(HWA_Handle handle, cmplx32ImRe_t *pbuf, uint8_t startIdx, uint8_t size)
Function to read the DC_EST_I/Q register.
HWA_AccelModeCompress
HWA Paramset Config for compression and decompression.
Definition: hwa/v0/hwa.h:1702
HWA_singleParamSetDonePolling
int32_t HWA_singleParamSetDonePolling(HWA_Handle handle, uint8_t paramsetIndex)
Function to poll the PARAM_DONE_SET_STATUS_0 or PARAM_DONE_SET_STATUS_1 registers to check if one sin...
HWA_NUM_RAMS
#define HWA_NUM_RAMS
The number of RAM types in HWA.
Definition: hwa/v0/hwa.h:185
HWA_CdfThreshold
HWA Histogram Threshold RAM data structure.
Definition: hwa/v0/hwa.h:1874
HWA_softwareResetRecursiveWinKvalue
int32_t HWA_softwareResetRecursiveWinKvalue(HWA_Handle handle)
Function resets the paramset counter used in recurise windowing mode with REC_WIN_MODE_SEL is set to ...
HWA_NUM_INTERFMITG_WINARRAY
#define HWA_NUM_INTERFMITG_WINARRAY
Number of programmable array of window parameters in interference mitigation block.
Definition: hwa/v0/hwa.h:177
HWA_triggerSingleStep
int32_t HWA_triggerSingleStep(HWA_Handle handle)
Function to Trigger single-step. This triggers state machine to execute one parameter-set at a time a...
HWA_InterruptCtx
HWA Interrupt context structure for paramset done interrupt.
Definition: hwa/v0/hwa.h:1932
HWA_clearClipStatus
int32_t HWA_clearClipStatus(HWA_Handle handle, uint8_t type)
Function to clear the Clip Status registers.
HWA_RAMAttrs
HWA RAM Parameters.
Definition: hwa/v0/hwa.h:824
HWA_readDebugReg
int32_t HWA_readDebugReg(HWA_Handle handle, HWA_DebugStats *pStats)
Function to read the debug registers (paramcurr, loopcou, acc_trig_in_stat)
HWA_PostProcStat
HWA Paramset Config for post-processing and the statistics control registers.
Definition: hwa/v0/hwa.h:1311
HWA_DestConfig
HWA Paramset Config for Output Formatter/Destination block.
Definition: hwa/v0/hwa.h:1247
HWA_readRam
int32_t HWA_readRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx)
Function to read the HWA 2D statistics output RAM, including HWA_RAM_TYPE_2DSTAT_ITER_VAL,...
HWA_controlPeripheralSuspendMode
int32_t HWA_controlPeripheralSuspendMode(HWA_Handle handle, uint8_t flagEnDis)
Function to control the suspend mode of the peripheral when the controlling processor (where this dri...
HWA_readInterfChirpCountReg
int32_t HWA_readInterfChirpCountReg(HWA_Handle handle, uint16_t *numInterfSamplesChirp)
Function to read the number of samples that exceeded the threshold in a chirp.
HWA_Handle
void * HWA_Handle
A handle that is returned from a HWA_open() call.
Definition: hwa/v0/hwa.h:774
HWA_Stats
HWA Statistics from the STATISTICS block.
Definition: hwa/v0/hwa.h:1807
HWA_setSourceAddress
int32_t HWA_setSourceAddress(HWA_Handle handle, uint16_t paramIdx, uint32_t sourceAddress)
Function to set the source address for one paramset.
HWA_deinit
void HWA_deinit(void)
Function to deinitialize the HWA module.
HWA_readStatsReg
int32_t HWA_readStatsReg(HWA_Handle handle, HWA_Stats *pStats, uint8_t numIter)
Function to read the 4 sets of 'MAX' statistics register.
HWA_Object
HWA driver internal Config.
Definition: hwa/v0/hwa.h:1954
HWA_Attrs
HWA H/W Parameters.
Definition: hwa/v0/hwa.h:798
HWA_readIntfAccReg
int32_t HWA_readIntfAccReg(HWA_Handle handle, uint64_t *accBuf, uint8_t type, uint8_t startIdx, uint8_t size)
Function to read the interference threshold MAG or MAGDIFF Accumulator register.
gHwaObjectPtr
HWA_Object * gHwaObjectPtr[]
Externally defined driver object pointer.
HWA_softwareResetAccumulators
int32_t HWA_softwareResetAccumulators(HWA_Handle handle, uint8_t accumulatortype)
Function for sofware to reset the DC accumulators or interference statistics accumulators.