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AM273x MCU+ SDK
08.06.00
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77 #include <drivers/hw_include/csl_complex_math_types.h>
79 #include <drivers/hw_include/cslr_hwa.h>
90 #define HWADRV_ADDR_TRANSLATE_CPU_TO_HWA(x) (uint32_t)((uint32_t)(x) & 0x000FFFFFU)
99 #define HWA_ERRNO_BASE (-2800)
101 #define HWA_EINVAL (HWA_ERRNO_BASE-1)
103 #define HWA_ENOINIT (HWA_ERRNO_BASE-2)
105 #define HWA_EOUTOFRANGE (HWA_ERRNO_BASE-3)
107 #define HWA_EOUTOFMEM (HWA_ERRNO_BASE-4)
109 #define HWA_ENOTSUPP (HWA_ERRNO_BASE-5)
111 #define HWA_EINUSE (HWA_ERRNO_BASE-6)
113 #define HWA_ENOTALIGNED (HWA_ERRNO_BASE-7)
115 #define HWA_EINVAL_COMMON_REGISTER_PARAMSET (HWA_ERRNO_BASE-8)
117 #define HWA_EINVAL_COMMON_REGISTER_PARAMSET_ALT (HWA_ERRNO_BASE-9)
119 #define HWA_EINVAL_COMMON_REGISTER_FFTCONFIG (HWA_ERRNO_BASE-10)
121 #define HWA_EINVAL_COMMON_REGISTER_DCEST (HWA_ERRNO_BASE-11)
123 #define HWA_EINVAL_COMMON_REGISTER_CFAR (HWA_ERRNO_BASE-12)
125 #define HWA_EINVAL_COMMON_REGISTER_INTERFERENCE (HWA_ERRNO_BASE-13)
127 #define HWA_EINVAL_COMMON_REGISTER_COMPLEXMULT (HWA_ERRNO_BASE-14)
129 #define HWA_EINVAL_COMMON_REGISTER_CHANCOMB (HWA_ERRNO_BASE-15)
131 #define HWA_EINVAL_COMMON_REGISTER_ZEROINSERT (HWA_ERRNO_BASE-16)
133 #define HWA_EINVAL_COMMON_REGISTER_ADVSTAT (HWA_ERRNO_BASE-17)
135 #define HWA_EINVAL_COMMON_REGISTER_COMPRESS (HWA_ERRNO_BASE-18)
137 #define HWA_EINVAL_COMMON_REGISTER_LOCALMAXIMUM (HWA_ERRNO_BASE-19)
139 #define HWA_EINVAL_PARAMSET_GENERALCONFIG (HWA_ERRNO_BASE - 20)
141 #define HWA_EINVAL_PARAMSET_SOURCE (HWA_ERRNO_BASE - 21)
143 #define HWA_EINVAL_PARAMSET_DEST (HWA_ERRNO_BASE - 22)
145 #define HWA_EINVAL_PARAMSET_SRCDST_ADDRESS (HWA_ERRNO_BASE - 23)
147 #define HWA_EINVAL_PARAMSET_FFTMODE_GENERALCONFIG (HWA_ERRNO_BASE - 24)
149 #define HWA_EINVAL_PARAMSET_FFTMODE_SIZE (HWA_ERRNO_BASE - 25)
151 #define HWA_EINVAL_PARAMSET_FFTMODE_POSTPROC (HWA_ERRNO_BASE - 26)
153 #define HWA_EINVAL_PARAMSET_FFTMODE_PREPROC (HWA_ERRNO_BASE - 27)
155 #define HWA_EINVAL_PARAMSET_FFTMODE_PREPROC_INTERF (HWA_ERRNO_BASE - 28)
157 #define HWA_EINVAL_PARAMSET_FFTMODE_PREPROC_COMPLEXMULT (HWA_ERRNO_BASE - 29)
159 #define HWA_EINVAL_PARAMSET_CFARMODE_GENERALCONFIG (HWA_ERRNO_BASE - 30)
161 #define HWA_EINVAL_PARAMSET_CFARMODE_OSCONFIG (HWA_ERRNO_BASE - 31)
163 #define HWA_EINVAL_PARAMSET_CFARMODE_CACONFIG (HWA_ERRNO_BASE - 32)
165 #define HWA_EINVAL_PARAMSET_COMPRESSMODE (HWA_ERRNO_BASE - 33)
167 #define HWA_EINVAL_PARAMSET_LOCALMAXMODE (HWA_ERRNO_BASE - 34)
169 #define HWA_PARAMSET_POLLINGNOTALLOWED (HWA_ERRNO_BASE - 35)
171 #define HWA_EINVAL_COMMON_REGISTER_CFAR_DET_THR (HWA_ERRNO_BASE - 36)
175 #define HWA_NUM_RXCHANNELS (12U)
177 #define HWA_NUM_INTERFMITG_WINARRAY (5U)
179 #define HWA_BPMPATTERN_LENGTH_INWORDS (8U)
181 #define HWA_CHANCOMB_LENGTH_INWORDS (8U)
183 #define HWA_ZEROINSERT_LENGTH_INWORDS (8U)
185 #define HWA_NUM_RAMS (10U)
187 #define HWA_MAXNUM_LOOPS (4095U)
189 #define HWA_CMP_K_ARR_LEN (8U)
204 #define HWA_DONE_INTERRUPT_PRIORITY (1U)
206 #define HWA_ALTDONE_INTERRUPT_PRIORITY (1U)
208 #define HWA_PARAMSETDONE_INTERRUPT1_PRIORITY (1U)
210 #define HWA_PARAMSETDONE_INTERRUPT2_PRIORITY (1U)
212 #define HWA_LOCAL_RAM_ERR_PRIORITY (1U)
220 #define HWA_FEATURE_BIT_ENABLE ((uint8_t)1U)
221 #define HWA_FEATURE_BIT_DISABLE ((uint8_t)0U)
229 #define HWA_SAMPLES_WIDTH_16BIT ((uint8_t)0U)
230 #define HWA_SAMPLES_WIDTH_32BIT ((uint8_t)1U)
238 #define HWA_SAMPLES_FORMAT_COMPLEX ((uint8_t)0U)
239 #define HWA_SAMPLES_FORMAT_REAL ((uint8_t)1U)
247 #define HWA_SAMPLES_UNSIGNED ((uint8_t)0U)
248 #define HWA_SAMPLES_SIGNED ((uint8_t)1U)
256 #define HWA_FFT_WINDOW_NONSYMMETRIC ((uint8_t)0U)
257 #define HWA_FFT_WINDOW_SYMMETRIC ((uint8_t)1U)
269 #define HWA_FFT_WINDOW_INTERPOLATE_MODE_NONE ((uint8_t)0U)
270 #define HWA_FFT_WINDOW_INTERPOLATE_MODE_4K ((uint8_t)2U)
271 #define HWA_FFT_WINDOW_INTERPOLATE_MODE_8K ((uint8_t)1U)
279 #define HWA_FFT_MODE_MAGNITUDE_LOG2_DISABLED ((uint8_t)0U)
280 #define HWA_FFT_MODE_MAGNITUDE_ONLY_ENABLED ((uint8_t)2U)
281 #define HWA_FFT_MODE_MAGNITUDE_LOG2_ENABLED ((uint8_t)3U)
289 #define HWA_FFT_MODE_OUTPUT_DEFAULT ((uint8_t)0U)
290 #define HWA_FFT_MODE_OUTPUT_MAX_STATS ((uint8_t)2U)
291 #define HWA_FFT_MODE_OUTPUT_SUM_STATS ((uint8_t)3U)
299 #define HWA_NOISE_AVG_MODE_CFAR_CA ((uint8_t)0U)
300 #define HWA_NOISE_AVG_MODE_CFAR_CAGO ((uint8_t)1U)
301 #define HWA_NOISE_AVG_MODE_CFAR_CASO ((uint8_t)2U)
302 #define HWA_NOISE_AVG_MODE_CFAR_OS ((uint8_t)3U)
310 #define HWA_TRIG_MODE_IMMEDIATE ((uint8_t)0U)
311 #define HWA_TRIG_MODE_SOFTWARE ((uint8_t)1U)
312 #define HWA_TRIG_MODE_RESERVED1 ((uint8_t)2U)
313 #define HWA_TRIG_MODE_DMA ((uint8_t)3U)
314 #define HWA_TRIG_MODE_HARDWARE ((uint8_t)4U)
315 #define HWA_TRIG_MODE_RESERVED2 ((uint8_t)5U)
316 #define HWA_TRIG_MODE_RESERVED3 ((uint8_t)6U)
317 #define HWA_TRIG_MODE_SOFTWARE2 ((uint8_t)7U)
325 #define HWA_CONTEXTSWITCH_TRIG_MODE_DMA ((uint8_t)3U)
326 #define HWA_CONTEXTSWITCH_TRIG_MODE_HARDWARE ((uint8_t)4U)
327 #define HWA_CONTEXTSWITCH_TRIG_MODE_SOFTWARE ((uint8_t)5U)
335 #define HWA_THREAD_BACKGROUNDCONTEXT ((uint8_t)0U)
336 #define HWA_THREAD_ALTCONTEXT ((uint8_t)1U)
344 #define HWA_ACCELMODE_FFT ((uint8_t)0U)
345 #define HWA_ACCELMODE_CFAR ((uint8_t)1U)
346 #define HWA_ACCELMODE_COMPRESS ((uint8_t)2U)
347 #define HWA_ACCELMODE_LOCALMAX ((uint8_t)3U)
348 #define HWA_ACCELMODE_NONE ((uint8_t)7U)
368 #define HWA_CFAR_OPER_MODE_LOG_INPUT_REAL 0U
369 #define HWA_CFAR_OPER_MODE_LOG_INPUT_COMPLEX 1U
370 #define HWA_CFAR_OPER_MODE_MAG_INPUT_REAL 2U
371 #define HWA_CFAR_OPER_MODE_MAG_INPUT_COMPLEX 3U
372 #define HWA_CFAR_OPER_MODE_MAG_SQR_INPUT_REAL 4U
373 #define HWA_CFAR_OPER_MODE_MAG_SQR_INPUT_COMPLEX 5U
374 #define HWA_CFAR_OPER_MODE_LOG_INPUT_COMPLEX_LINEARCFAR 6U
392 #define HWA_CFAR_OUTPUT_MODE_I_nAVG_ALL_Q_CUT ((uint8_t)0U)
394 #define HWA_CFAR_OUTPUT_MODE_I_nAVG_ALL_Q_DET_FLAG ((uint8_t)1U)
396 #define HWA_CFAR_OUTPUT_MODE_I_PEAK_IDX_Q_NEIGHBOR_NOISE_VAL ((uint8_t)2U)
398 #define HWA_CFAR_OUTPUT_MODE_I_PEAK_IDX_Q_CUT ((uint8_t)3U)
400 #define HWA_CFAR_OUTPUT_MODE_FILTER_LARGE_PEAK ((uint8_t)4U)
409 #define HWA_RAM_TYPE_WINDOW_RAM ((uint8_t)0U)
410 #define HWA_RAM_TYPE_VECTORMULTIPLY_RAM ((uint8_t)1U)
411 #define HWA_RAM_TYPE_LUT_FREQ_DEROTATE_RAM ((uint8_t)2U)
412 #define HWA_RAM_TYPE_SHUFFLE_RAM ((uint8_t)3U)
413 #define HWA_RAM_TYPE_HIST_THRESH_RAM ((uint8_t)4U)
414 #define HWA_RAM_TYPE_2DSTAT_ITER_VAL ((uint8_t)5U)
415 #define HWA_RAM_TYPE_2DSTAT_ITER_IDX ((uint8_t)6U)
416 #define HWA_RAM_TYPE_2DSTAT_SAMPLE_VAL ((uint8_t)7U)
417 #define HWA_RAM_TYPE_2DSTAT_SAMPLE_IDX ((uint8_t)8U)
418 #define HWA_RAM_TYPE_HISTOGRAM_RAM ((uint8_t)9U)
426 #define HWA_CLIPREG_TYPE_DCACC ((uint8_t)0U)
427 #define HWA_CLIPREG_TYPE_DCEST ((uint8_t)1U)
428 #define HWA_CLIPREG_TYPE_DCSUB ((uint8_t)2U)
429 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGACC ((uint8_t)3U)
430 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGDIFFACC ((uint8_t)4U)
431 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGTHRESHOLD ((uint8_t)5U)
432 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGDIFFTHRESHOLD ((uint8_t)6U)
433 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGSUM ((uint8_t)7U)
434 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGDIFFSUM ((uint8_t)8U)
435 #define HWA_CLIPREG_TYPE_TWIDINCR_DELTAFRAC ((uint8_t)9U)
436 #define HWA_CLIPREG_TYPE_CHANCOMB ((uint8_t)10U)
437 #define HWA_CLIPREG_TYPE_FFT ((uint8_t)11U)
438 #define HWA_CLIPREG_TYPE_INPUTFORMAT ((uint8_t)12U)
439 #define HWA_CLIPREG_TYPE_OUTPUTFORMAT ((uint8_t)13U)
447 #define HWA_ACCUMULATORREG_TYPE_DC ((uint8_t)0U)
448 #define HWA_ACCUMULATORREG_TYPE_INTERF_MAG ((uint8_t)1U)
449 #define HWA_ACCUMULATORREG_TYPE_INTERF_MAGDIFF ((uint8_t)2U)
450 #define HWA_ACCUMULATORREG_TYPE_INTERF ((uint8_t)3U)
458 #define HWA_INTERFERENCE_THRESHOLD_TYPE_MAG ((uint8_t)0U)
459 #define HWA_INTERFERENCE_THRESHOLD_TYPE_MAGDIFF ((uint8_t)1U)
469 #define HWA_PARAMDONE_INTERRUPT_TYPE_CPU_INTR1 ((uint8_t)1U)
470 #define HWA_PARAMDONE_INTERRUPT_TYPE_CPU_INTR2 ((uint8_t)2U)
471 #define HWA_PARAMDONE_INTERRUPT_TYPE_DMA ((uint8_t)4U)
480 #define HWA_COMMONCONFIG_MASK_STATEMACHINE_CFG ((uint64_t)0x00000001U)
481 #define HWA_COMMONCONFIG_MASK_STATEMACHINE_CFG_ALT ((uint64_t)0x00000002U)
482 #define HWA_COMMONCONFIG_CONTEXTSWITCH_TRIG_CFG ((uint64_t)0x00000004U)
483 #define HWA_COMMONCONFIG_MASK_BPMCFG ((uint64_t)0x00000008U)
484 #define HWA_COMMONCONFIG_MASK_TWIDDITHERENABLE ((uint64_t)0x00000010U)
485 #define HWA_COMMONCONFIG_MASK_LFSRSEED ((uint64_t)0x00000020U)
486 #define HWA_COMMONCONFIG_MASK_FFTSUMDIV ((uint64_t)0x00000040U)
487 #define HWA_COMMONCONFIG_MASK_CFARTHRESHOLDSCALE ((uint64_t)0x00000080U)
488 #define HWA_COMMONCONFIG_MASK_DCEST_SCALESHIFT ((uint64_t)0x00000100U)
489 #define HWA_COMMONCONFIG_MASK_DCSUB_SWVAL ((uint64_t)0x00000200U)
490 #define HWA_COMMONCONFIG_MASK_INTERFMAG_THRESHOLD ((uint64_t)0x00000400U)
491 #define HWA_COMMONCONFIG_MASK_INTERFMAGDIFF_THRESHOLD ((uint64_t)0x00000800U)
492 #define HWA_COMMONCONFIG_MASK_INTERFSUM_MAG ((uint64_t)0x00001000U)
493 #define HWA_COMMONCONFIG_MASK_INTERFSUM_MAGDIFF ((uint64_t)0x00002000U)
494 #define HWA_COMMONCONFIG_MASK_COMPLEXMULT_SCALEARRAY ((uint64_t)0x00004000U)
497 #define HWA_COMMONCONFIG_MASK_COMPLEXMULT_SCALECONST ((uint64_t)0x00008000U)
500 #define HWA_COMMONCONFIG_MASK_RECWIN_RESET ((uint64_t)0x00010000U)
501 #define HWA_COMMONCONFIG_MASK_TWIDINCR_DELTA_FRAC ((uint64_t)0x00020000U)
503 #define HWA_COMMONCONFIG_MASK_CHANCOMB_VEC_SIZE ((uint64_t)0x00400000U)
504 #define HWA_COMMONCONFIG_MASK_ZEROINSERT_NUM_MASK ((uint64_t)0x00800000U)
505 #define HWA_COMMONCONFIG_MASK_MAX2D_OFFSETBOTHDIM ((uint64_t)0x01000000U)
506 #define HWA_COMMONCONFIG_MASK_CDFCNT_THRESHOLD ((uint64_t)0x02000000U)
507 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMB_THRESHOLDSW ((uint64_t)0x04000000U)
508 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMC_THRESHOLDSW ((uint64_t)0x08000000U)
509 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMBTHRESH_OFFSET ((uint64_t)0x10000000U)
510 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMCTHRESH_OFFSET ((uint64_t)0x20000000U)
511 #define HWA_COMMONCONFIG_MASK_INTERF_MITG_WINDOW_PARAM ((uint64_t)0x40000000U)
512 #define HWA_COMMONCONFIG_MASK_EGECOMRESS_KPARAM ((uint64_t)0x80000000U)
514 #define HWA_COMMONCONFIG_MASK_CFAR_DET_THR ((uint64_t)0x1000000000U)
515 #if defined (SOC_AWR294X)
516 #define HWA_COMMONCONFIG_MASK_CMP_LFSRSEED0 ((uint64_t)0x200000000U)
517 #define HWA_COMMONCONFIG_MASK_CMP_LFSRSEED1 ((uint64_t)0x400000000U)
518 #define HWA_COMMONCONFIG_MASK_SW_RESTART_LOOP ((uint64_t)0x800000000U)
528 #define HWA_SRC_SHUFFLE_AB_MODE_DISABLE ((uint8_t)0U)
529 #define HWA_SRC_SHUFFLE_AB_MODE_ADIM ((uint8_t)1U)
530 #define HWA_SRC_SHUFFLE_AB_MODE_BDIM ((uint8_t)2U)
538 #define HWA_COMPLEX_MULTIPLY_MODE_DISABLE ((uint8_t)0U)
539 #define HWA_COMPLEX_MULTIPLY_MODE_FREQ_SHIFTER ((uint8_t)1U)
540 #define HWA_COMPLEX_MULTIPLY_MODE_SLOW_DFT ((uint8_t)2U)
541 #define HWA_COMPLEX_MULTIPLY_MODE_FFT_STITCHING ((uint8_t)3U)
542 #define HWA_COMPLEX_MULTIPLY_MODE_MAG_SQUARED ((uint8_t)4U)
543 #define HWA_COMPLEX_MULTIPLY_MODE_SCALAR_MULT ((uint8_t)5U)
544 #define HWA_COMPLEX_MULTIPLY_MODE_VECTOR_MULT ((uint8_t)6U)
545 #define HWA_COMPLEX_MULTIPLY_MODE_VECTOR_MULT_2 ((uint8_t)7U)
546 #define HWA_COMPLEX_MULTIPLY_MODE_RECURSIVE_WIN ((uint8_t)8U)
547 #define HWA_COMPLEX_MULTIPLY_MODE_LUT_FREQ_DEROTATE ((uint8_t)9U)
548 #define HWA_COMPLEX_MULTIPLY_MODE_FREQSHIFT_FREQINCREMENT ((uint8_t)10U)
557 #define HWA_FFT_STITCHING_TWID_PATTERN_4K ((uint8_t)1U)
558 #define HWA_FFT_STITCHING_TWID_PATTERN_8K ((uint8_t)2U)
567 #define HWA_RECURSIVE_WIN_MODE_SELECT_ITERATION_COUNT ((uint8_t)0U)
568 #define HWA_FFT_STITCHING_TWID_PATTERN_EXE_COUNT ((uint8_t)1U)
576 #define HWA_WINDOW_MODE_18BITREAL ((uint8_t)0U)
578 #define HWA_WINDOW_MODE_16BITREAL ((uint8_t)1U)
580 #define HWA_WINDOW_MODE_COMPLEX ((uint8_t)2U)
589 #define HWA_FFT3x_BFLY_SCALING_MSBSATURATED ((uint8_t)0U)
590 #define HWA_FFT3x_BFLY_SCALING_MSBSATLSBRND ((uint8_t)1U)
592 #define HWA_FFT3x_BFLY_SCALING_LSBROUNDED ((uint8_t)2U)
601 #define HWA_DCEST_INTERFSUM_RESET_MODE_NOUPDATE ((uint8_t)0U)
602 #define HWA_DCEST_INTERFSUM_RESET_MODE_SOFTWARERESET ((uint8_t)1U)
603 #define HWA_DCEST_INTERFSUM_RESET_MODE_PARAMRESET ((uint8_t)2U)
604 #define HWA_DCEST_INTERFSUM_RESET_MODE_PARAMRESET_ZEROLPCONT ((uint8_t)3U)
612 #define HWA_INTERFTHRESH_MODE_MAG_OR_MAGDIF ((uint8_t)0U)
613 #define HWA_INTERFTHRESH_MODE_MAGDIFF ((uint8_t)1U)
614 #define HWA_INTERFTHRESH_MODE_MAG ((uint8_t)2U)
615 #define HWA_INTERFTHRESH_MODE_MAG_AND_MAGDIFF ((uint8_t)3U)
623 #define HWA_DCSUB_SELECT_DCSW ((uint8_t)0U)
624 #define HWA_DCSUB_SELECT_DCEST ((uint8_t)1U)
632 #define HWA_INTERFTHRESH_SELECT_SW ((uint8_t)0U)
634 #define HWA_INTERFTHRESH_SELECT_EST_AVERAGE ((uint8_t)1U)
636 #define HWA_INTERFTHRESH_SELECT_EST_INDIVIDUAL ((uint8_t)2U)
645 #define HWA_INTERFMITIGATION_PATH_ZEROOUT ((uint8_t)0U)
646 #define HWA_INTERFMITIGATION_PATH_WINDOWZEROOUT ((uint8_t)1U)
647 #define HWA_INTERFMITIGATION_PATH_LINEARINTERPOLATION ((uint8_t)2U)
648 #define HWA_INTERFMITIGATION_PATH_UNUSED ((uint8_t)3U)
659 #define HWA_LUT_FREQ_DEROTATE_RAMIDX_AUTOINCR_WRAPAROUND ((uint8_t)0U)
660 #define HWA_LUT_FREQ_DEROTATE_RAMIDX_AUTOINCR_SATURATED ((uint8_t)1U)
661 #define HWA_LUT_FREQ_DEROTATE_RAMIDX_NONINCR ((uint8_t)2U)
669 #define HWA_HISTOGRAM_MODE_DISABLED ((uint8_t)0U)
670 #define HWA_HISTOGRAM_MODE_HISTOGRAM ((uint8_t)1U)
671 #define HWA_HISTOGRAM_MODE_CDF ((uint8_t)2U)
672 #define HWA_HISTOGRAM_MODE_CDF_THRESHOLD ((uint8_t)3U)
680 #define HWA_LOCALMAX_THRESH_BITMASK_BOTH_EN ((uint8_t)0U)
681 #define HWA_LOCALMAX_THRESH_BITMASK_CDIM_EN ((uint8_t)1U)
682 #define HWA_LOCALMAX_THRESH_BITMASK_BDIM_EN ((uint8_t)2U)
683 #define HWA_LOCALMAX_THRESH_BITMASK_BOTH_DIS ((uint8_t)3U)
691 #define HWA_LOCALMAX_THRESH_SELECT_DIMBREG_DIMCREG ((uint8_t)0U)
692 #define HWA_LOCALMAX_THRESH_SELECT_DIMBRAM_DIMCREG ((uint8_t)1U)
693 #define HWA_LOCALMAX_THRESH_SELECT_DIMBREG_DIMCRAM ((uint8_t)2U)
694 #define HWA_LOCALMAX_THRESH_SELECT_DIMBRAM_DIMCRAM ((uint8_t)3U)
702 #define HWA_COMPRESS_METHOD_EGE ((uint8_t)0U)
703 #define HWA_COMPRESS_METHOD_BFP ((uint8_t)1U)
711 #define HWA_CMP_DCMP_COMPRESS ((uint8_t)0U)
712 #define HWA_CMP_DCMP_DECOMPRESS ((uint8_t)1U)
720 #define HWA_COMPRESS_PATHSELECT_BOTHPASSES ((uint8_t)3U)
721 #define HWA_COMPRESS_PATHSELECT_SECONDPASS ((uint8_t)1U)
733 #define HWA_PARAMSET_CONTEXTSWITCH_DISABLE (0U)
735 #define HWA_PARAMSET_CONTEXTSWITCH_NONFORCE_ENABLE (1U)
738 #define HWA_PARAMSET_CONTEXTSWITCH_FORCE_ENABLE (2U)
747 #define HWA_APP_MEMINIT_PARAM_RAM (1U << 8U)
749 #define HWA_APP_MEMINIT_WINDOW_RAM (1U << 9U)
751 #define HWA_APP_MEMINIT_PER_SAMPLE_MAX_VAL_EVEN_RAM (1U << 10U)
753 #define HWA_APP_MEMINIT_PER_SAMPLE_MAX_VAL_ODD_RAM (1U << 11U)
755 #define HWA_APP_MEMINIT_PER_ITER_MAX_VAL_RAM (1U << 12U)
757 #define HWA_APP_MEMINIT_HIST_EVEN_RAM (1U << 13U)
759 #define HWA_APP_MEMINIT_HIST_ODD_RAM (1U << 14U)
761 #define HWA_APP_MEMINIT_MEMBANK_ALL (HWA_APP_MEMINIT_PARAM_RAM | \
762 HWA_APP_MEMINIT_WINDOW_RAM | \
763 HWA_APP_MEMINIT_PER_SAMPLE_MAX_VAL_EVEN_RAM | \
764 HWA_APP_MEMINIT_PER_SAMPLE_MAX_VAL_ODD_RAM | \
765 HWA_APP_MEMINIT_PER_ITER_MAX_VAL_RAM | \
766 HWA_APP_MEMINIT_HIST_EVEN_RAM | \
767 HWA_APP_MEMINIT_HIST_ODD_RAM )
801 typedef struct HWA_Attrs_t {
802 uint32_t instanceNum;
803 volatile uint32_t ctrlBaseAddr;
804 volatile uint32_t paramBaseAddr;
805 volatile uint32_t ramBaseAddr;
806 volatile uint32_t dssBaseAddr;
807 uint32_t numHwaParamSets;
808 uint32_t intNum1ParamSet;
809 uint32_t intNum2ParamSet;
811 uint32_t intNumDoneALT;
812 uint32_t intNumLocalRamErr;
813 uint32_t numDmaChannels;
814 volatile uint32_t accelMemBaseAddr;
815 uint32_t accelMemSize;
816 bool isConcurrentAccessAllowed;
826 typedef struct HWA_RAMAttrs_t
828 uint32_t ramBaseAddress;
829 uint32_t ramSizeInBytes;
843 typedef struct HWA_SrcDMAConfig_t {
857 typedef struct HWA_CommonConfig_t {
865 uint16_t paramStartIdx;
868 uint16_t paramStopIdx;
871 uint16_t numLoopsALT;
874 uint16_t paramStartIdxALT;
877 uint16_t paramStopIdxALT;
880 uint8_t contextswitchTriggerMode;
883 uint8_t contextswitchTriggerSrc;
887 #if defined (SOC_AWR294X)
889 uint8_t swRestartLoop;
903 uint8_t twidDitherEnable;
976 uint8_t sumMagDiffScale;
981 int8_t sumMagDiffShift;
1009 int16_t twiddleDeltaFrac;
1017 uint8_t recWindowReset;
1020 } complexMultiplyConfig;
1055 uint32_t thresholdScale;
1066 uint32_t cfarDetthreshold;
1071 } cfarDetThresConfig;
1075 int32_t max2DoffsetDim1;
1079 int32_t max2DoffsetDim2;
1084 uint16_t cdfCntThresh;
1094 uint16_t dimBThreshold;
1099 uint16_t dimCThreshold;
1104 uint16_t dimBBaseAddress;
1109 uint16_t dimCBaseAddress;
1122 #if defined (SOC_AWR294X)
1123 uint32_t cmpLfsrSeed0;
1125 uint32_t cmpLfsrSeed1;
1139 typedef struct HWA_SourceConfig_t {
1164 uint16_t srcAcircShift;
1168 uint8_t srcAcircShiftWrap;
1175 uint16_t srcBcircShift;
1178 uint8_t srcBcircShiftWrap;
1185 uint16_t srcCcircShift;
1189 uint8_t srcCcircShiftWrap;
1196 uint8_t srcCircShiftWrap3;
1200 uint8_t shuffleMode ;
1203 uint8_t srcRealComplex;
1216 uint8_t srcConjugate;
1239 uint8_t shuffleStart;
1250 typedef struct HWA_DestConfig_t {
1271 uint8_t dstRealComplex;
1286 uint8_t dstConjugate;
1298 uint16_t dstSkipInit;
1314 typedef struct HWA_PostProcStat_t {
1329 uint8_t max2Denable;
1333 uint8_t histogramMode;
1338 uint8_t histogramScaleSelect;
1343 uint8_t histogramSizeSelect;
1355 typedef struct HWA_ComplexMultiply_t {
1365 uint16_t freqShiftTwiddleIncr;
1381 uint16_t twiddlePattern;
1386 uint8_t winInterpolateMode;
1396 uint8_t scaleCmultScaleEn;
1410 uint8_t cmultScaleEn;
1417 uint16_t vecMultiMode1RamAddrOffset;
1419 } vectorMultiplyMode1;
1423 uint16_t vecMultiMode2RamAddrOffset;
1427 } vectorMultiplyMode2;
1431 uint8_t recwinModeSel;
1438 uint16_t ramAddrOffset;
1440 uint8_t ramIdxIncrMode;
1447 uint16_t twiddleIncr;
1450 } freqShiftWithFreIncrement;
1460 typedef struct HWA_PreProcessing_t {
1462 uint8_t dcEstResetMode;
1467 uint8_t dcSubEnable;
1471 uint8_t dcSubSelect;
1475 uint8_t thresholdEnable;
1479 uint8_t thresholdMode;
1483 uint8_t thresholdSelect;
1504 uint8_t countThreshold;
1513 uint8_t leftHystOrder;
1517 uint8_t rightHystOrder;
1528 uint8_t zeroInsertEn;
1543 typedef struct HWA_AccelModeFFT_t{
1556 uint16_t butterflyScaling;
1567 uint16_t windowStart;
1580 uint8_t fftSize3xEn;
1585 uint8_t fftSizeDim2;
1590 uint8_t butterflyScalingFFT3x;
1615 typedef struct HWA_AccelModeCFAR_t{
1616 uint8_t numNoiseSamplesLeft;
1622 uint8_t numNoiseSamplesRight;
1627 uint8_t numGuardCells;
1629 uint8_t nAvgDivFactor;
1639 uint8_t cfarOsKvalue;
1642 uint8_t cfarOsEdgeKScaleEn;
1653 uint8_t cfarAdvOutMode;
1658 uint8_t peakGroupEn;
1667 uint8_t cyclicModeEn;
1680 typedef struct HWA_AccelModeLocalMax_t{
1682 uint8_t neighbourBitmask;
1686 uint8_t thresholdBitMask;
1690 uint8_t thresholdMode;
1693 uint8_t dimBNonCyclic;
1695 uint8_t dimCNonCyclic;
1705 typedef struct HWA_AccelModeCompress_t {
1709 uint8_t EGEKarrayLength;
1712 uint8_t scaleFactorBW;
1717 uint8_t BFPMantissaBW;
1720 uint8_t scaleFactor;
1724 uint8_t headerEnable;
1731 uint8_t compressDecompress;
1733 uint8_t ditherEnable;
1736 #if defined (SOC_AWR294X)
1738 uint8_t decrImagBitw;
1753 typedef struct HWA_ParamConfig_t {
1754 uint8_t triggerMode;
1777 uint8_t contextswitchCfg;
1787 typedef struct HWA_InterruptConfig_t {
1788 uint8_t interruptTypeFlag;
1810 typedef struct HWA_Stats_t {
1823 typedef struct HWA_AccmulatorVal_t {
1834 typedef struct HWA_DebugStats_t {
1835 uint8_t currentParamSet;
1840 uint8_t paramSetIdxCpuIntr0;
1841 uint8_t paramSetIdxCpuIntr1;
1852 uint8_t fsmStateInfo;
1853 uint16_t currentLoopCount;
1855 uint16_t otherThreadLoopCount;
1856 uint32_t trigStatus[2];
1865 typedef struct HWA_MemInfo_t {
1866 uint32_t baseAddress;
1877 typedef struct HWA_CdfThreshold_t {
1879 uint32_t pdfValue : 12;
1880 uint32_t cdfValue : 12;
1881 uint32_t binNumber : 6;
1882 uint32_t reserved : 2;
1890 typedef struct HWA_InterruptPriority_t {
1892 uint32_t backgroundDone;
1894 uint32_t paramsetDone1;
1895 uint32_t paramsetDone2;
1896 uint32_t loalRamErr;
1904 typedef struct HWA_OpenConfig_t {
1935 typedef struct HWA_InterruptCtx_t {
1948 typedef struct HWA_DoneInterruptCtx_t {
1957 typedef struct HWA_Driver_t {
1961 uint32_t instanceNum;
1970 uint8_t configInProgress;
1976 uint16_t paramSetMapInProgress;
2015 uint64_t interrupt1ParamSetMask;
2020 uint64_t interrupt2ParamSetMask;
2033 #if defined (SOC_AWR294X)
2257 extern int32_t
HWA_configRam(
HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx);
2290 extern int32_t
HWA_readRam(
HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx);
#define HWA_CHANCOMB_LENGTH_INWORDS
The length of channel combining vector in words.
Definition: hwa/v0/hwa.h:181
HWA Paramset Config for Input Formatter/Source block.
Definition: hwa/v0/hwa.h:1136
HWA Accumulator register value data structure.
Definition: hwa/v0/hwa.h:1820
int32_t HWA_readInterfThreshReg(HWA_Handle handle, uint32_t *pbuf, uint8_t startIdx, uint8_t size, uint8_t type)
Function to read the interference statistics INTF_LOC_THRESH_MAG_VAL or INTF_LOC_THRESH_MAG_VAL regis...
int32_t HWA_enable(HWA_Handle handle, uint8_t flagEnDis)
Function to enable the state machine of the HWA. This should be called after paramset and RAM have be...
int32_t HWA_disableDoneInterrupt(HWA_Handle handle, uint8_t threadIdx)
Function to disable the CPU interrupt after all programmed paramSets have been completed.
int32_t HWA_reset(HWA_Handle handle)
Function to reset the internal state machine of the HWA.
HWA Paramset Config for FFT block.
Definition: hwa/v0/hwa.h:1540
int32_t HWA_setDMA2ACCManualTrig(HWA_Handle handle, uint8_t idx)
Function to manually trigger the execution of the state machine waiting on DMA via software.
int32_t HWA_configureSingleStep(HWA_Handle handle, uint8_t flagEnDis)
Function to enable/disable single-stepping approach which pauses the HWA execution after each param-s...
int32_t HWA_clearDebugReg(HWA_Handle handle)
Function to clear the debug registers (acc_trig_in_clr)
HWA Local memory Information.
Definition: hwa/v0/hwa.h:1862
uint32_t gHwaConfigNum
Externally defined driver configuration array size.
int32_t HWA_paramSetDonePolling(HWA_Handle handle, uint8_t numParamSets, uint8_t *paramsetsArray)
Function to poll the PARAM_DONE_SET_STATUS_0 and PARAM_DONE_SET_STATUS_1 registers to check if the sp...
HWA_Handle HWA_open(uint32_t index, HWA_OpenConfig *hwaCfg, int32_t *errCode)
Function to initialize HWA specified by the particular index value.
int32_t HWA_getDMAChanIndex(HWA_Handle handle, uint8_t edmaChanId, uint8_t *hwaDestChan)
Function to get the dma destination index with a given EDMA channel number This function assumes the ...
int32_t HWA_enableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, HWA_InterruptConfig *intrConfig)
Function to enable the CPU and/or DMA interrupt after a paramSet completion. The CPU interrupt for ev...
HWA Paramset Config for ComplexMultiply block.
Definition: hwa/v0/hwa.h:1352
void(* HWA_ParamDone_IntHandlerFuncPTR)(uint32_t intrIdx, uint32_t paramSet, void *arg)
HWA Interrupt callback function after every paramset completion.
Definition: hwa/v0/hwa.h:782
HWA Paramset Config for CFAR block.
Definition: hwa/v0/hwa.h:1612
void HWA_init(void)
Function to initialize the HWA module.
HWA_Attrs gHwaAttrs[]
Externally defined driver configuration array.
#define HWA_CMP_K_ARR_LEN
The length of EGE compression/decompression K-paramseters array.
Definition: hwa/v0/hwa.h:189
HWA configuration structure, which describes the configuration information, needed for hwa handle ope...
Definition: hwa/v0/hwa.h:1901
int32_t HWA_softwareResetTwidIncrDeltaFrac(HWA_Handle handle)
Function resets the execution counter if complex multiply is configured as frequency shifter mode wit...
int32_t HWA_setContextswitchDMAManualTrigger(HWA_Handle handle, uint8_t idx)
Function to manually trigger the execution of the state machine via DMA trigger in context switch.
#define HWA_ZEROINSERT_LENGTH_INWORDS
The length of zero insert mask in words.
Definition: hwa/v0/hwa.h:183
int32_t HWA_getDMAconfig(HWA_Handle handle, uint8_t dmaTriggerSrc, HWA_SrcDMAConfig *dmaConfig)
Function to get the config to program the DMA for a given DMA Trigger channel. Application should use...
HWA Debug statistics.
Definition: hwa/v0/hwa.h:1831
int32_t HWA_readInterfFrameCountReg(HWA_Handle handle, uint32_t *numInterfSamplesFrame)
Function to read the number of samples that exceeded the threshold in a frame.
int32_t HWA_close(HWA_Handle handle)
Function to close a HWA peripheral specified by the HWA handle.
int32_t HWA_readHistThresholdRam(HWA_Handle handle, HWA_CdfThreshold *cdfThresholdResult, uint8_t numSampleIndices, uint8_t startSampleIdx)
Function to read the HWA HWA_RAM_TYPE_HIST_THRESH_RAM RAM.
int32_t HWA_enableContextSwitch(HWA_Handle handle, uint8_t flagEnDis)
Function to enable or disable the context switching in hwa.
int32_t HWA_readCFARPeakCountReg(HWA_Handle handle, uint8_t *pbuf, uint8_t size)
Function to read the PEAKCNT register.
DSSHWACCPARAMRegs * HWA_getParamSetAddr(HWA_Handle handle, uint8_t paramsetIdx)
Function to returns the HWA paramSet base address.
int32_t HWA_readDCAccReg(HWA_Handle handle, cmplx64ImRe_t *accbuf, uint8_t startIdx, uint8_t size)
Function to read the DC estimation accumulator register,.
#define HWA_BPMPATTERN_LENGTH_INWORDS
The length of BPM Pattern sequence in words.
Definition: hwa/v0/hwa.h:179
int32_t HWA_getEDMAChanId(HWA_Handle handle, uint8_t hwaDMAdestChan)
Function to get the edma EDMA channel number from a given HWA paramset destination channel....
int32_t HWA_enableDoneInterrupt(HWA_Handle handle, uint8_t threadIdx, HWA_Done_IntHandlerFuncPTR callbackFn, void *callbackArg)
Function to enable the CPU interrupt after all programmed paramSets have been completed in the backgr...
int32_t HWA_setSoftwareTrigger(HWA_Handle handle, uint8_t swTriggerType)
Function to manually trigger the execution of the state machine via software, the software trigger th...
int32_t HWA_setContextswitchSoftwareTrigger(HWA_Handle handle)
Function to manually trigger the execution of the state machine via software in context switch,...
DSSHWACCRegs * HWA_getCommonCtrlAddr(HWA_Handle handle)
Function to returns the HWA common control base address.
HWA_RAMAttrs gHwaRamCfg[HWA_NUM_RAMS]
Externally defined driver RAM configuration array.
void(* HWA_Done_IntHandlerFuncPTR)(uint32_t threadIdx, void *arg)
HWA Interrupt callback function after all paramsets completion.
Definition: hwa/v0/hwa.h:790
HWA Paramset Config for pre-processing block.
Definition: hwa/v0/hwa.h:1457
int32_t HWA_initializeRAM(HWA_Handle handle, uint32_t ramMemBankMask)
Function to initialize RAM memory banks in HWA.
uint32_t HWA_getRamAddress(uint8_t ramType)
Function to get the RAM starting address for one specified RAM type.
int32_t HWA_configCommon(HWA_Handle handle, HWA_CommonConfig *commonConfig)
Function to set the common HWA configuration parameters needed for the next operations/iterations/par...
#define HWA_NUM_RXCHANNELS
Number of RX channels in pre-processing block.
Definition: hwa/v0/hwa.h:175
int32_t HWA_getHWAMemInfo(HWA_Handle handle, HWA_MemInfo *memInfo)
Function to get HWA processing Memory information including address, size and number of banks.
HWA_Object gHwaObject[]
Externally defined driver object.
int32_t HWA_configRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx)
Function to set the HWA RAM : HWA_RAM_TYPE_WINDOW_RAM, HWA_RAM_TYPE_VECTORMULTIPLY_RAM,...
HWA Paramset Config for Local maxima block.
Definition: hwa/v0/hwa.h:1677
HWA interrupt priority for HWA background thread done, ALT thread done, paramset done interrupt 1 and...
Definition: hwa/v0/hwa.h:1887
int32_t HWA_readClipStatus(HWA_Handle handle, uint16_t *clipStatusResult, uint8_t type)
Function to read the Clip Status registers.
int32_t HWA_configParamSet(HWA_Handle handle, uint8_t paramsetIdx, HWA_ParamConfig *paramConfig, HWA_SrcDMAConfig *dmaConfig)
Function to set the HWA configuration parameters for a given paramSet.
HWA Interrupt Config.
Definition: hwa/v0/hwa.h:1784
Source trigger DMA parameters.
Definition: hwa/v0/hwa.h:840
HWA Interrupt context structure for done interrupt.
Definition: hwa/v0/hwa.h:1945
HWA Common Config.
Definition: hwa/v0/hwa.h:854
int32_t HWA_disableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, uint8_t interruptTypeFlag)
Function to disable the CPU and/or DMA interrupt after a paramSet completion.
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
HWA Paramset Config.
Definition: hwa/v0/hwa.h:1750
int32_t HWA_readDCEstimateReg(HWA_Handle handle, cmplx32ImRe_t *pbuf, uint8_t startIdx, uint8_t size)
Function to read the DC_EST_I/Q register.
HWA Paramset Config for compression and decompression.
Definition: hwa/v0/hwa.h:1702
int32_t HWA_singleParamSetDonePolling(HWA_Handle handle, uint8_t paramsetIndex)
Function to poll the PARAM_DONE_SET_STATUS_0 or PARAM_DONE_SET_STATUS_1 registers to check if one sin...
#define HWA_NUM_RAMS
The number of RAM types in HWA.
Definition: hwa/v0/hwa.h:185
HWA Histogram Threshold RAM data structure.
Definition: hwa/v0/hwa.h:1874
int32_t HWA_softwareResetRecursiveWinKvalue(HWA_Handle handle)
Function resets the paramset counter used in recurise windowing mode with REC_WIN_MODE_SEL is set to ...
#define HWA_NUM_INTERFMITG_WINARRAY
Number of programmable array of window parameters in interference mitigation block.
Definition: hwa/v0/hwa.h:177
int32_t HWA_triggerSingleStep(HWA_Handle handle)
Function to Trigger single-step. This triggers state machine to execute one parameter-set at a time a...
HWA Interrupt context structure for paramset done interrupt.
Definition: hwa/v0/hwa.h:1932
int32_t HWA_clearClipStatus(HWA_Handle handle, uint8_t type)
Function to clear the Clip Status registers.
HWA RAM Parameters.
Definition: hwa/v0/hwa.h:824
int32_t HWA_readDebugReg(HWA_Handle handle, HWA_DebugStats *pStats)
Function to read the debug registers (paramcurr, loopcou, acc_trig_in_stat)
HWA Paramset Config for post-processing and the statistics control registers.
Definition: hwa/v0/hwa.h:1311
HWA Paramset Config for Output Formatter/Destination block.
Definition: hwa/v0/hwa.h:1247
int32_t HWA_readRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx)
Function to read the HWA 2D statistics output RAM, including HWA_RAM_TYPE_2DSTAT_ITER_VAL,...
int32_t HWA_controlPeripheralSuspendMode(HWA_Handle handle, uint8_t flagEnDis)
Function to control the suspend mode of the peripheral when the controlling processor (where this dri...
int32_t HWA_readInterfChirpCountReg(HWA_Handle handle, uint16_t *numInterfSamplesChirp)
Function to read the number of samples that exceeded the threshold in a chirp.
void * HWA_Handle
A handle that is returned from a HWA_open() call.
Definition: hwa/v0/hwa.h:774
HWA Statistics from the STATISTICS block.
Definition: hwa/v0/hwa.h:1807
int32_t HWA_setSourceAddress(HWA_Handle handle, uint16_t paramIdx, uint32_t sourceAddress)
Function to set the source address for one paramset.
void HWA_deinit(void)
Function to deinitialize the HWA module.
int32_t HWA_readStatsReg(HWA_Handle handle, HWA_Stats *pStats, uint8_t numIter)
Function to read the 4 sets of 'MAX' statistics register.
HWA driver internal Config.
Definition: hwa/v0/hwa.h:1954
HWA H/W Parameters.
Definition: hwa/v0/hwa.h:798
int32_t HWA_readIntfAccReg(HWA_Handle handle, uint64_t *accBuf, uint8_t type, uint8_t startIdx, uint8_t size)
Function to read the interference threshold MAG or MAGDIFF Accumulator register.
HWA_Object * gHwaObjectPtr[]
Externally defined driver object pointer.
int32_t HWA_softwareResetAccumulators(HWA_Handle handle, uint8_t accumulatortype)
Function for sofware to reset the DC accumulators or interference statistics accumulators.