SDL DCC Example

Introduction

This example demonstrates how to configure the DCC and use it to monitor clocks in the two supported modes (continuous and single-shot modes). It also demonstrates how to receive errors generated by DCC in the MCU and Main domain.

This example displays:

* Initializing the ESM to detect the DCC error event(s)
* Registration of application callback for notification of ESM error events for the MCU ESM instance
* Configuration of one MCU DCC instance to monitor a single clock in continuous mode
* Forcing of an error to create a DCC error event

The following methods can be used as a trigger for the DCC error event:

* Change ratio criterion for stable clocks
* Use Sciclient API to change clock dividers (with ratio criterion stable) to speed up clock
* Use Sciclient API to change clock dividers (with ratio criterion stable) to slow down clock
* Turn off power for the monitored input clock

Use Cases

Use Case	Reference Clock	Description
UC-1	HFOSC0	Configuration of MCU DCC instance in continuous mode and error event is forced
UC-2	HFOSC0	Configuration of MCU DCC instance in single-shot mode and completion with no errors
UC-3	HFOSC0	Configuration of MCU DCC instance in continuous mode and completion with no errors
UC-4	RC OSC	Configuration of MCU DCC instance in single-shot mode and completion with no errors
UC-5	RC OSC	Configuration of DCC instance in continuous mode and error event is forced
UC-6	RC OSC	Configuration of DCC instance in continuous mode and error event is forced
UC-7	HFOSC0	Configuration of DCC instance in continuous mode and error event is forced
UC-8	RC OSC	Configuration of DCC instance in continuous mode and completion with no errors
UC-9	HFOSC0	Configuration of DCC instance in single-shot mode and completion with no errors
UC-10	FICLK	Configuration of DCC instance in single-shot mode and completion with no errors

Supported Combinations

Parameter      | Value
---------------|-----------
CPU + OS       | mcu-r5fss0-0 nortos
Toolchain      | ti-arm-clang
Board          | {{ VAR_BOARD_NAME_LOWER }}
Example folder | examples/sdl/dcc/dcc_app/

Steps to Run the Example

When using CCS projects to build, import the CCS project for the required combination and build it using the CCS project menu (see Using SDK with CCS Projects).
When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles)
Launch a CCS debug session and run the executable, see CCS Launch, Load and Run

See Also

Sample Output

Shown below is a sample output when the application is run,

 DCC Example Test Application

DCC_Test_init: Init WKUP ESM complete


USECASE: 0
Source clock: HFOSC0
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt
SDL DCC EXAMPLE TEST: Indicating clock drift/change
UC-0 Completed Successfully

USECASE: 1
Source clock: HFOSC0
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC Generated completion interrupt
SDL DCC EXAMPLE TEST: No Clock Drift was observed
UC-1 Completed Successfully

USECASE: 2
Source clock: HFOSC0
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and running for some time
UC-2 Completed Successfully

USECASE: 3
Source clock: RC OSC
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC Generated completion interrupt
SDL DCC EXAMPLE TEST: No Clock Drift was observed
UC-3 Completed Successfully

USECASE: 4
Source clock: RC OSC
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt
SDL DCC EXAMPLE TEST: Indicating clock drift/change
UC-4 Completed Successfully

USECASE: 5
Source clock: RC OSC
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt
SDL DCC EXAMPLE TEST: Indicating clock drift/change
UC-5 Completed Successfully

USECASE: 6
Source clock: RC OSC
Test clock: SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt
SDL DCC EXAMPLE TEST: Indicating clock drift/change
UC-6 Completed Successfully

USECASE: 7
Source clock: HFOSC0
Test clock: MAIN_SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt
SDL DCC EXAMPLE TEST: Indicating clock drift/change
UC-7 Completed Successfully

USECASE: 8
Source clock: RC OSC
Test clock: MAIN_SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and running for some time
UC-8 Completed Successfully

USECASE: 9
Source clock: HFOSC0
Test clock: FICLK

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC Generated completion interrupt
SDL DCC EXAMPLE TEST: No Clock Drift was observed
UC-9 Completed Successfully

USECASE: 10
Source clock: FICLK
Test clock: MAIN_SYSCLK0

SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC Generated completion interrupt
SDL DCC EXAMPLE TEST: No Clock Drift was observed
UC-10 Completed Successfully

 All tests have passed.