Cache

Features Supported

  • APIs to perform below cache operations

    • region based writeback

    • region based invalidate

    • region based writeback invalidate

    • enable and disable APIs for I cache and D cache

    • full cache writeback, write invalidte

Features NOT Supported

NA

Important Usage Guidelines

  • The region based cache APIs, CacheP_wb, CacheP_wbInv, CacheP_inv, operate on a CPU cache line, hence its strongly recommended to make sure ‘addr’ is cache line aliged and ‘size` is a multiple of cache line size

    • Start address is calculated as follows, start_addr = floor(addr, CPU_CACHE_LINE)

    • End address is calculated as follows, end_addr = ceil(addr + size, CPU_CACHE_LINE)

    • No error is returned, for unaligned addr and size

  • On R5F,

    • Valid values for CacheP_Type for CacheP_enable and CacheP_disable are CacheP_TYPE_L1D, CacheP_TYPE_L1P, CacheP_TYPE_ALL

    • Valid values for CacheP_Type for CacheP_wb, CacheP_wbInv, CacheP_inv, CacheP_wbAll, CacheP_wbInvAll are CacheP_TYPE_L1D, CacheP_TYPE_ALL

  • CPU cache lines sizes for reference

    • R5F: 32B

  • On R5F, It is recommended to enable both program and data cache in R5F in all applications. In R5F for cache to be enabled MPU needs to be enabled.

  • On M4F, the CPU does not support cache so these APIs when used with M4F, will be blank and will have no effect

Example Usage

Include the below file to access the APIs,

Example usage for cache write back invalidate:

Example usage for cache invalidate:

API Reference

Cache Type

Values defined for CacheP types

CacheP_TYPE_L1P

L1 program cache

CacheP_TYPE_L1D

L1 data cache

CacheP_TYPE_L2P

L2 program cache

CacheP_TYPE_L2D

L2 data cache

CacheP_TYPE_L1

All L1 cache’s

CacheP_TYPE_L2

All L2 cache’s

CacheP_TYPE_ALLP

All program cache’s

CacheP_TYPE_ALLD

All data cache’s

CacheP_TYPE_ALL

All cache’s

Defines

CacheP_CACHELINE_ALIGNMENT

Cache line size for alignment of buffers. Actual CPU defined cache line can be smaller that this value, this define is a utility macro to keep application portable across different CPU’s.

Functions

void CacheP_enable(uint32_t type)

Cache enable.

Parameters:

type –

[in] cache type’s to enable

R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported

void CacheP_disable(uint32_t type)

Cache disable.

Parameters:

type –

[in] cache type’s to disable

R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported

uint32_t CacheP_getEnabled(void)

Get cache enabled bits.

Returns:

cache type’s that are enabled

void CacheP_wbAll(uint32_t type)

Cache writeback for full cache.

Parameters:

type –

[in] cache type’s to writeback

R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported

void CacheP_wbInvAll(uint32_t type)

Cache writeback and invalidate for full cache.

Parameters:

type –

[in] cache type’s to writeback and invalidate

R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported

void CacheP_wb(void *addr, uint32_t size, uint32_t type)

Cache writeback for a specified region.

Parameters:

  • addr – [in] region address. Recommend to specify address that is cache line aligned

  • size – [in] region size in bytes. Recommend to specify size that is multiple of cache line size

  • type –

    [in] cache type’s to writeback

    R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported

void CacheP_inv(void *addr, uint32_t size, uint32_t type)

Cache invalidate for a specified region.

Parameters:

  • addr – [in] region address. Recommend to specify address that is cache line aligned

  • size – [in] region size in bytes. Recommend to specify size that is multiple of cache line size

  • type –

    [in] cache type’s to invalidate

    R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported

void CacheP_wbInv(void *addr, uint32_t size, uint32_t type)

Cache writeback and invalidate for a specified region.

Parameters:

  • addr – [in] region address. Recommend to specify address that is cache line aligned

  • size – [in] region size in bytes. Recommend to specify size that is multiple of cache line size

  • type –

    [in] cache type’s to writeback and invalidate

    R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported

void CacheP_init(void)

Initialize Cache sub-system, called by SysConfig, not to be called by end users.

Variables

CacheP_Config gCacheConfig

Externally defined Cache configuration.

struct CacheP_Config
#include <CacheP.h>

Cache config structure, this used by SysConfig and not to be used by end-users directly.

Public Members

uint32_t enable

0: cache disabled, 1: cache enabled

uint32_t enableForceWrThru

0: force write through disabled, 1: force write through enabled