HW Interrupts

Attention

See also FreeRTOS, NO RTOS for list of CPU specific supported and unsupported features.

Features Supported

  • Register a interrupt callback to a specific CPU number

  • Ability to pass user specific argument to the interrupt callback

  • Enable, disable, restore and clear specific CPU interrupts

  • Enable, disable, restore global CPU interrupt

  • For ARM R5,

    • Ability to specify interrupt as FIQ or IRQ, level or pulse

    • Ability to specify interrupt priority

Features NOT Supported

See also FreeRTOS, NO RTOS for list of unsupported features.

Important Usage Guidelines

  • For ARM R5,

    • TI VIM is the interrupt controller that is supported.

    • HwiP_disable, HwiP_restore, HwiP_enable only affect state of IRQ. FIQ state is not changed

    • Refer ARMv7-R Architecture reference manual and SOC TRM for more details.

  • On AM62DX,

    CPU type

    Valid interrupt numbers

    Valid interrupt priorities

    R5F

    0 .. 511

    0 (highest) .. 15 (lowest)

    A53

    0 .. 255

    0 (highest) .. 14 (lowest)

  • On C75,

    • The C75 CPU supports 64 interrupts.

    • The CLEC event ID can be mapped to any of C75 interrupts.

    • If you are configuring software interrupt, then set eventId to HWIP_INVALID_EVENT_ID.

    • While mapping CLEC event ID to interrupt number, refer the below table and avoid overlapping interrupts.

      Module

      Interrupt number used

      EQEP

      5 .. 7

      TIMER

      8 .. 15

      I2C

      16 .. 20

      GPIO

      21

      UART

      22 .. 30

      ECAP

      25 .. 27

      UDMA

      32 .. 48

      EPWM

      49 .. 51

      MCASP

      53 .. 58

      IPC

      59 .. 62

      MCSPI

      1, 2, 31, 52, 63

  • On AM62DX,

    CPU type

    Valid interrupt numbers

    Valid interrupt priorities

    R5F

    0 .. 511

    0 (highest) .. 15 (lowest)

  • On C75,

    • The C75 CPU supports 64 interrupts.

    • The CLEC event ID can be mapped to any of C75 interrupts.

    • If you are configuring software interrupt, then set eventId to HWIP_INVALID_EVENT_ID.

    • While mapping CLEC event ID to interrupt number, refer the below table and avoid overlapping interrupts.

      Module

      Interrupt number used

      TIMER

      2 .. 6

      IPC

      7 .. 11

      OSPI

      13

      MMCSD

      14

      I2C

      15 .. 19

      MCSPI

      20 .. 24

      ECAP

      25 .. 30

      UART

      22, 32 .. 38

      MCASP

      39 .. 48

      EPWM

      49 .. 51

      UDMA

      52 .. 61

      WDT

      62 .. 63

      ASRC

      20 .. 29

      Not Used

      12, 31

Example Usage

Include the below file to access the APIs,


//! [include]
#include <stdio.h>
#include <kernel/dpl/HwiP.h>
//! [include]

//! [isr]
void myISR(void *args)
{
    /* my ISR */

Example ISR:

//! [isr]

void samples()
{
{
//! [register]
    HwiP_Params hwiParams;
    HwiP_Object hwiObj;

    HwiP_Params_init(&hwiParams);
    /* for R5F, interrupt #10 at VIM */
    hwiParams.intNum = 10;
    /* for M4F, external interrupt #10 at NVIC is
       16 internal interrupts + external interrupt number at NVIC

Example to register a ISR for CPU interrupt 10:

     */
    /* for C75, CLEC event ID can be mapped to any of the internal interrupt number
       set both event ID and interrupt number
       to configure harware clec event #10
           hwiParams.eventId = 10;
           hwiParams.intNum = 31;
       to configure software interrupt #31
           hwiParams.eventId = HWIP_INVALID_EVENT_ID;
           hwiParams.intNum = 31;

Example to disable and restore interrupts across a critical section:

     */
    hwiParams.callback = myISR;
    hwiParams.args = NULL;

    HwiP_construct(&hwiObj, &hwiParams);
//! [register]
}
{
//! [disable]
    uintptr_t oldIntState;

    oldIntState = HwiP_disable();

    /* critical section */

API Reference

Defines

HWIP_INVALID_EVENT_ID
HwiP_OBJECT_SIZE_MAX

Max size of Hwi object across no-RTOS and all OS’s.

Typedefs

typedef void (*HwiP_FxnCallback)(void *args)

Callback that is called when a HW interrupt is received.

Param args:

[in] user argument passed during HwiP_construct

Functions

void HwiP_Params_init(HwiP_Params *params)

Set default values to HwiP_Params.

Strongly recommended to be called before seting values in HwiP_Params

Parameters:

params – [out] parameter structure to set to default

int32_t HwiP_construct(HwiP_Object *obj, HwiP_Params *params)

Create a Hwi object.

Parameters:

  • obj – [out] created object

  • params – [in] parameter structure

Returns:

SystemP_SUCCESS on success, SystemP_FAILURE on error

int32_t HwiP_setArgs(HwiP_Object *obj, void *args)

Set argument to pass to the ISR.

Parameters:

  • obj – [out] created object

  • args – [in] argument to pass to the ISR

Returns:

SystemP_SUCCESS on success, SystemP_FAILURE on error

void HwiP_destruct(HwiP_Object *obj)

Cleanup, delete, destruct a Hwi object.

Parameters:

obj – [in] Hwi object

void HwiP_enableInt(uint32_t intNum)

Enable a specific interrupt.

Parameters:

intNum – [in] Interrupt number

uint32_t HwiP_disableInt(uint32_t intNum)

Disable a specific interrupt.

The return value is typically used with HwiP_restoreInt to restore the interrupt state to old value.

Parameters:

intNum – [in] Interrupt number

Returns:

old interrupt state,

0: interrupt was disabled previously,

1: interrupt was enabled previously

void HwiP_restoreInt(uint32_t intNum, uint32_t oldIntState)

Restore a specific interrupt.

The oldIntState value typically returned by HwiP_disableInt is used to restore the interrupt state to old value.

Parameters:

  • intNum – [in] Interrupt number

  • oldIntState – [in] 0: disable interrupt, 1: enable interrupt

void HwiP_clearInt(uint32_t intNum)

Clear a pending specific interrupt.

Parameters:

intNum – [in] Interrupt number

void HwiP_post(uint32_t intNum)

Force trigger a specific interrupt.

Parameters:

intNum – [in] Interrupt number

uintptr_t HwiP_disable(void)

Disable all interrupts.

Note

In case of ARM R5F, ARM M4F, this only disables IRQ.

FIQ is not disabled.

In case of ARM M4F, this only disables interrupts which has priority between 1-7.

Returns:

interrupt state before disable, typically used by HwiP_restore later

void HwiP_enable(void)

Enable all interrupts.

Note

In case of ARM R5F, ARM M4F, this only enables IRQ.

FIQ is not enabled.

void HwiP_restore(uintptr_t oldIntState)

Restores all interrupts to a given state.

Note

In case of ARM R5F, ARM M4F, this only restores IRQ state.

FIQ state is not changed.

Parameters:

oldIntState – [in] interrupt state, typically returned by HwiP_disable earlier

uint32_t HwiP_inISR(void)

Check if the caller of this function is inside a ISR or not.

In some cases, like with freertos, some functions cannot be called from within the OS ISR handler, this API allows the user and some driver porting layer (DPL) APIs to check and call the appropiate ISR safe API when in ISR handler mode.

To get the exact CPU mode of the executing CPU, use the low level CPU specific system calls/registers.

Note

In case of ARM R5F, this only checks if caller is not inside inside system mode or not. This means when HwiP_inISR returns 1, CPU is in IRQ mode or FIQ or abort mode. And when HwiP_inISR return 0, CPU is not in system mode.

Returns:

0 not in interrupt mode, 1 in interrupt mode

void HwiP_init(void)

Initialize Hwi module.

  • Disables all individual interrupts

  • Clears all individual interrupts

  • Enables global interrupts

Note

MUST be called during system intialization before any HwiP_construct API calls.

Note

In case of ARM R5F, ARM M4F, this initializes and enables both FIQ and IRQ

int32_t HwiP_registerNmiHandler(HwiP_FxnCallback nmiHandler, void *args)

This API registers the NMI handler.

Parameters:

  • nmiHandler – [in] Callback function to be called for NMI

  • args – [in] Args passed for the NMI callback

Returns:

SystemP_SUCCESS on success, SystemP_FAILURE on error

int32_t HwiP_unregisterNmiHandler(void)

This API unregisters the current NMI handler.

Returns:

SystemP_SUCCESS on success, SystemP_FAILURE on error

struct HwiP_Config
#include <HwiP.h>

HwiP config parameters, setup as part of SysConfig, not to be set by end-users directly.

Public Members

uint32_t intcBaseAddr

For R5F, this is VIM base addr

struct HwiP_Params
#include <HwiP.h>

Parameters passed during HwiP_construct.

Public Members

uint32_t intNum

CPU interrupt number.

HwiP_FxnCallback callback

Callback to call when interrupt is received

void *args

Arguments to pass to the callback

uint16_t eventId

Event ID to register against, only used with c6x with event combiner and c7x clec configurer

uint8_t priority

Interrupt priority, only used with ARM R5, ARM M4

uint8_t isFIQ

0: Map interrupt as ISR, 1: map interrupt as FIQ, only used with ARM R5

uint8_t isPulse

0: Map interrupt as level interrupt, 1: Map interrupt as pulse interrupt, only used with ARM R5, ARM M4

struct HwiP_Object
#include <HwiP.h>

Opaque Hwi object used with the Hwi APIs.

Public Members

uint32_t rsv[HwiP_OBJECT_SIZE_MAX / sizeof(uint32_t)]

reserved, should NOT be modified by end users

struct AIFSR
#include <HwiP.h>

Provide additional information about data and instruction parity, ECC, and external TCM errors.

Note

Refer to ARMv7-R architecture manual for more details

Public Members

uint32_t index
uint32_t side_ext
uint32_t recoverable_error
uint32_t cacheway
struct IFSR
#include <HwiP.h>

Holds status information regarding the source of the last instruction abort.

Note

Refer to ARMv7-R architecture manual for more details

Public Members

uint32_t status
uint32_t sd
struct ADFSR
#include <HwiP.h>

Provide additional information about data and instruction parity, ECC, and external TCM errors.

Note

Refer to ARMv7-R architecture manual for more details

Public Members

uint32_t index
uint32_t side_ext
uint32_t recoverable_error
uint32_t cacheway
struct DFSR
#include <HwiP.h>

Holds status information regarding the source of the last data abort.

Note

Refer to ARMv7-R architecture manual for more details

Public Members

uint32_t status
uint32_t sd
uint32_t rw