EVTSVT

Instance: EVTSVT
Component: EVTSVT
Base address: 0x40025000


This is top module of Event Fabric for LOKI

TOP:EVTSVT Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

DESC

RO

32

0x3045 1010

0x0000 0000

0x4002 5000

DESCEX

RO

32

0x03A0 3D39

0x0000 0004

0x4002 5004

DTB

RW

32

0x0000 0000

0x0000 0064

0x4002 5064

NMI

RW

32

0x0000 0000

0x0000 0400

0x4002 5400

CPUIRQ0SEL

RW

32

0x0000 0000

0x0000 0404

0x4002 5404

CPUIRQ1SEL

RW

32

0x0000 0000

0x0000 0408

0x4002 5408

CPUIRQ2SEL

RW

32

0x0000 0000

0x0000 040C

0x4002 540C

CPUIRQ3SEL

RW

32

0x0000 0000

0x0000 0410

0x4002 5410

CPUIRQ4SEL

RW

32

0x0000 0000

0x0000 0414

0x4002 5414

CPUIRQ5SEL

RO

32

0x0000 0011

0x0000 0418

0x4002 5418

CPUIRQ6SEL

RO

32

0x0000 0014

0x0000 041C

0x4002 541C

CPUIRQ7SEL

RO

32

0x0000 0015

0x0000 0420

0x4002 5420

CPUIRQ8SEL

RO

32

0x0000 001C

0x0000 0424

0x4002 5424

CPUIRQ9SEL

RO

32

0x0000 001E

0x0000 0428

0x4002 5428

CPUIRQ10SEL

RO

32

0x0000 0017

0x0000 042C

0x4002 542C

CPUIRQ11SEL

RO

32

0x0000 001F

0x0000 0430

0x4002 5430

CPUIRQ12SEL

RO

32

0x0000 0020

0x0000 0434

0x4002 5434

CPUIRQ13SEL

RO

32

0x0000 001A

0x0000 0438

0x4002 5438

CPUIRQ14SEL

RO

32

0x0000 001B

0x0000 043C

0x4002 543C

CPUIRQ15SEL

RO

32

0x0000 0018

0x0000 0440

0x4002 5440

CPUIRQ16SEL

RW

32

0x0000 0000

0x0000 0444

0x4002 5444

CPUIRQ17SEL

RW

32

0x0000 0000

0x0000 0448

0x4002 5448

CPUIRQ18SEL

RO

32

0x0000 0039

0x0000 044C

0x4002 544C

CPUIRQ19SEL

RO

32

0x0000 003F

0x0000 0450

0x4002 5450

CPUIRQ20SEL

RO

32

0x0000 0042

0x0000 0454

0x4002 5454

CPUIRQ21SEL

RO

32

0x0000 0043

0x0000 0458

0x4002 5458

CPUIRQ22SEL

RO

32

0x0000 0035

0x0000 045C

0x4002 545C

CPUIRQ23SEL

RO

32

0x0000 0045

0x0000 0460

0x4002 5460

CPUIRQ24SEL

RO

32

0x0000 0046

0x0000 0464

0x4002 5464

CPUIRQ25SEL

RO

32

0x0000 0047

0x0000 0468

0x4002 5468

CPUIRQ26SEL

RO

32

0x0000 0048

0x0000 046C

0x4002 546C

CPUIRQ27SEL

RO

32

0x0000 0049

0x0000 0470

0x4002 5470

CPUIRQ28SEL

RO

32

0x0000 0002

0x0000 0474

0x4002 5474

CPUIRQ29SEL

RO

32

0x0000 0003

0x0000 0478

0x4002 5478

CPUIRQ30SEL

RO

32

0x0000 0004

0x0000 047C

0x4002 547C

CPUIRQ31SEL

RO

32

0x0000 0006

0x0000 0480

0x4002 5480

CPUIRQ32SEL

RO

32

0x0000 0007

0x0000 0484

0x4002 5484

SYSTIMC0SEL

RO

32

0x0000 0004

0x0000 0488

0x4002 5488

SYSTIMC1SEL

RW

32

0x0000 0000

0x0000 048C

0x4002 548C

SYSTIMC2SEL

RO

32

0x0000 0032

0x0000 0490

0x4002 5490

SYSTIMC3SEL

RO

32

0x0000 0033

0x0000 0494

0x4002 5494

SYSTIMC4SEL

RO

32

0x0000 0034

0x0000 0498

0x4002 5498

SYSTIMC5SEL

RW

32

0x0000 0000

0x0000 049C

0x4002 549C

ADCTRGSEL

RW

32

0x0000 0000

0x0000 04A0

0x4002 54A0

LGPTSYNCSEL

RW

32

0x0000 0000

0x0000 04A4

0x4002 54A4

LGPT0IN0SEL

RW

32

0x0000 0000

0x0000 04A8

0x4002 54A8

LGPT0IN1SEL

RW

32

0x0000 0000

0x0000 04AC

0x4002 54AC

LGPT0IN2SEL

RW

32

0x0000 0000

0x0000 04B0

0x4002 54B0

LGPT0TENSEL

RW

32

0x0000 0000

0x0000 04B4

0x4002 54B4

LGPT1IN0SEL

RW

32

0x0000 0000

0x0000 04B8

0x4002 54B8

LGPT1IN1SEL

RW

32

0x0000 0000

0x0000 04BC

0x4002 54BC

LGPT1IN2SEL

RW

32

0x0000 0000

0x0000 04C0

0x4002 54C0

LGPT1TENSEL

RW

32

0x0000 0000

0x0000 04C4

0x4002 54C4

LGPT2IN0SEL

RW

32

0x0000 0000

0x0000 04C8

0x4002 54C8

LGPT2IN1SEL

RW

32

0x0000 0000

0x0000 04CC

0x4002 54CC

LGPT2IN2SEL

RW

32

0x0000 0000

0x0000 04D0

0x4002 54D0

LGPT2TENSEL

RW

32

0x0000 0000

0x0000 04D4

0x4002 54D4

LGPT3IN0SEL

RW

32

0x0000 0000

0x0000 04D8

0x4002 54D8

LGPT3IN1SEL

RW

32

0x0000 0000

0x0000 04DC

0x4002 54DC

LGPT3IN2SEL

RW

32

0x0000 0000

0x0000 04E0

0x4002 54E0

LGPT3TENSEL

RW

32

0x0000 0000

0x0000 04E4

0x4002 54E4

LRFDIN0SEL

RO

32

0x0000 0025

0x0000 04E8

0x4002 54E8

LRFDIN1SEL

RO

32

0x0000 0026

0x0000 04EC

0x4002 54EC

LRFDIN2SEL

RO

32

0x0000 0027

0x0000 04F0

0x4002 54F0

I2SSTMPSEL

RW

32

0x0000 0000

0x0000 04F4

0x4002 54F4

DMACH0SEL

RW

32

0x0000 0000

0x0000 0C00

0x4002 5C00

DMACH1SEL

RW

32

0x0000 0000

0x0000 0C04

0x4002 5C04

DMACH2SEL

RW

32

0x0000 0000

0x0000 0C08

0x4002 5C08

DMACH3SEL

RW

32

0x0000 0000

0x0000 0C0C

0x4002 5C0C

DMACH4SEL

RW

32

0x0000 0000

0x0000 0C10

0x4002 5C10

DMACH5SEL

RW

32

0x0000 0000

0x0000 0C14

0x4002 5C14

DMACH6SEL

RW

32

0x0000 0000

0x0000 0C18

0x4002 5C18

DMACH7SEL

RW

32

0x0000 0000

0x0000 0C1C

0x4002 5C1C

DMACH10SEL

RW

32

0x0000 0000

0x0000 0C20

0x4002 5C20

DMACH11SEL

RW

32

0x0000 0000

0x0000 0C24

0x4002 5C24

DMACH8SEL

RW

32

0x0000 0000

0x0000 0C28

0x4002 5C28

DMACH9SEL

RW

32

0x0000 0000

0x0000 0C2C

0x4002 5C2C

TOP:EVTSVT Register Descriptions

TOP:EVTSVT:DESC

Address Offset 0x0000 0000
Physical Address 0x4002 5000 Instance 0x4002 5000
Description This register identifies the peripheral
Type RO
Bits Field Name Description Type Reset
31:16 MODID Module identifier RO 0x3045
15:12 STDIPOFF 64 B Standard IP MMR block
0: STDIP MMRs do not exist
1:15: These MMRs begin at offset 64*STDIPOFF from IP base address		 RO 0x1
11:8 INSTIDX IP Instance number RO 0x0
7:4 MAJREV Major revision RO 0x1
3:0 MINREV Minor revision RO 0x0

TOP:EVTSVT:DESCEX

Address Offset 0x0000 0004
Physical Address 0x4002 5004 Instance 0x4002 5004
Description This register identifies the configuration of the peripheral
Type RO
Bits Field Name Description Type Reset
31:22 IDMA Nember of DMA input channels RO 0b00 0000 1110
21:17 NDMA Number of DMA output channels RO 0b1 0000
16 PD Power Domain.
0 : SVT
1 : ULL		 RO 0
15:8 NSUB Number of Subscribers RO 0x3D
7:0 NPUB Number of Publishers RO 0x39

TOP:EVTSVT:DTB

Address Offset 0x0000 0064
Physical Address 0x4002 5064 Instance 0x4002 5064
Description This bit field is used to select DTB mux digital inputs
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 SEL DTB Selection RW 0b00

TOP:EVTSVT:NMI

Address Offset 0x0000 0400
Physical Address 0x4002 5400 Instance 0x4002 5400
Description CPU NMI Interrupt Register
Type RW
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
16 SRAM_EVT_SET Writing a value of 1'b1 sets the corresponding NMI status flag WO 0
15:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
0 SRAM_EVT_STA Read value indicates the current state of NMI flops.
Writing a value of 1'b1 clears the NMI status when set.		 RW 0

TOP:EVTSVT:CPUIRQ0SEL

Address Offset 0x0000 0404
Physical Address 0x4002 5404 Instance 0x4002 5404
Description Output Selection for CPU Interrupt CPUIRQ0
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:CPUIRQ1SEL

Address Offset 0x0000 0408
Physical Address 0x4002 5408 Instance 0x4002 5408
Description Output Selection for CPU Interrupt CPUIRQ1
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:CPUIRQ2SEL

Address Offset 0x0000 040C
Physical Address 0x4002 540C Instance 0x4002 540C
Description Output Selection for CPU Interrupt CPUIRQ2
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:CPUIRQ3SEL

Address Offset 0x0000 0410
Physical Address 0x4002 5410 Instance 0x4002 5410
Description Output Selection for CPU Interrupt CPUIRQ3
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:CPUIRQ4SEL

Address Offset 0x0000 0414
Physical Address 0x4002 5414 Instance 0x4002 5414
Description Output Selection for CPU Interrupt CPUIRQ4
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:CPUIRQ5SEL

Address Offset 0x0000 0418
Physical Address 0x4002 5418 Instance 0x4002 5418
Description Output Selection for CPU Interrupt CPUIRQ5
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
RO 0b001 0001

TOP:EVTSVT:CPUIRQ6SEL

Address Offset 0x0000 041C
Physical Address 0x4002 541C Instance 0x4002 541C
Description Output Selection for CPU Interrupt CPUIRQ6
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
RO 0b001 0100

TOP:EVTSVT:CPUIRQ7SEL

Address Offset 0x0000 0420
Physical Address 0x4002 5420 Instance 0x4002 5420
Description Output Selection for CPU Interrupt CPUIRQ7
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
RO 0b001 0101

TOP:EVTSVT:CPUIRQ8SEL

Address Offset 0x0000 0424
Physical Address 0x4002 5424 Instance 0x4002 5424
Description Output Selection for CPU Interrupt CPUIRQ8
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
RO 0b001 1100

TOP:EVTSVT:CPUIRQ9SEL

Address Offset 0x0000 0428
Physical Address 0x4002 5428 Instance 0x4002 5428
Description Output Selection for CPU Interrupt CPUIRQ9
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
RO 0b001 1110

TOP:EVTSVT:CPUIRQ10SEL

Address Offset 0x0000 042C
Physical Address 0x4002 542C Instance 0x4002 542C
Description Output Selection for CPU Interrupt CPUIRQ10
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
RO 0b001 0111

TOP:EVTSVT:CPUIRQ11SEL

Address Offset 0x0000 0430
Physical Address 0x4002 5430 Instance 0x4002 5430
Description Output Selection for CPU Interrupt CPUIRQ11
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
RO 0b001 1111

TOP:EVTSVT:CPUIRQ12SEL

Address Offset 0x0000 0434
Physical Address 0x4002 5434 Instance 0x4002 5434
Description Output Selection for CPU Interrupt CPUIRQ12
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
RO 0b010 0000

TOP:EVTSVT:CPUIRQ13SEL

Address Offset 0x0000 0438
Physical Address 0x4002 5438 Instance 0x4002 5438
Description Output Selection for CPU Interrupt CPUIRQ13
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
RO 0b001 1010

TOP:EVTSVT:CPUIRQ14SEL

Address Offset 0x0000 043C
Physical Address 0x4002 543C Instance 0x4002 543C
Description Output Selection for CPU Interrupt CPUIRQ14
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
RO 0b001 1011

TOP:EVTSVT:CPUIRQ15SEL

Address Offset 0x0000 0440
Physical Address 0x4002 5440 Instance 0x4002 5440
Description Output Selection for CPU Interrupt CPUIRQ15
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
RO 0b001 1000

TOP:EVTSVT:CPUIRQ16SEL

Address Offset 0x0000 0444
Physical Address 0x4002 5444 Instance 0x4002 5444
Description Output Selection for CPU Interrupt CPUIRQ16
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:CPUIRQ17SEL

Address Offset 0x0000 0448
Physical Address 0x4002 5448 Instance 0x4002 5448
Description Output Selection for CPU Interrupt CPUIRQ17
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:CPUIRQ18SEL

Address Offset 0x0000 044C
Physical Address 0x4002 544C Instance 0x4002 544C
Description Output Selection for CPU Interrupt CPUIRQ18
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
RO 0b011 1001

TOP:EVTSVT:CPUIRQ19SEL

Address Offset 0x0000 0450
Physical Address 0x4002 5450 Instance 0x4002 5450
Description Output Selection for CPU Interrupt CPUIRQ19
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
RO 0b011 1111

TOP:EVTSVT:CPUIRQ20SEL

Address Offset 0x0000 0454
Physical Address 0x4002 5454 Instance 0x4002 5454
Description Output Selection for CPU Interrupt CPUIRQ20
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
RO 0b100 0010

TOP:EVTSVT:CPUIRQ21SEL

Address Offset 0x0000 0458
Physical Address 0x4002 5458 Instance 0x4002 5458
Description Output Selection for CPU Interrupt CPUIRQ21
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
RO 0b100 0011

TOP:EVTSVT:CPUIRQ22SEL

Address Offset 0x0000 045C
Physical Address 0x4002 545C Instance 0x4002 545C
Description Output Selection for CPU Interrupt CPUIRQ22
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
RO 0b011 0101

TOP:EVTSVT:CPUIRQ23SEL

Address Offset 0x0000 0460
Physical Address 0x4002 5460 Instance 0x4002 5460
Description Output Selection for CPU Interrupt CPUIRQ23
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
RO 0b100 0101

TOP:EVTSVT:CPUIRQ24SEL

Address Offset 0x0000 0464
Physical Address 0x4002 5464 Instance 0x4002 5464
Description Output Selection for CPU Interrupt CPUIRQ24
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x46 VCE_IRQ VCE IRQ
RO 0b100 0110

TOP:EVTSVT:CPUIRQ25SEL

Address Offset 0x0000 0468
Physical Address 0x4002 5468 Instance 0x4002 5468
Description Output Selection for CPU Interrupt CPUIRQ25
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x47 HSM_SEC_IRQ HSM Secure IRQ
RO 0b100 0111

TOP:EVTSVT:CPUIRQ26SEL

Address Offset 0x0000 046C
Physical Address 0x4002 546C Instance 0x4002 546C
Description Output Selection for CPU Interrupt CPUIRQ26
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x48 HSM_NONSEC_IRQ HSM Non-secure IRQ
RO 0b100 1000

TOP:EVTSVT:CPUIRQ27SEL

Address Offset 0x0000 0470
Physical Address 0x4002 5470 Instance 0x4002 5470
Description Output Selection for CPU Interrupt CPUIRQ27
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x49 HSM_OTP_IRQ HSM OTP IRQ
RO 0b100 1001

TOP:EVTSVT:CPUIRQ28SEL

Address Offset 0x0000 0474
Physical Address 0x4002 5474 Instance 0x4002 5474
Description Output Selection for CPU Interrupt CPUIRQ28
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
RO 0b000 0010

TOP:EVTSVT:CPUIRQ29SEL

Address Offset 0x0000 0478
Physical Address 0x4002 5478 Instance 0x4002 5478
Description Output Selection for CPU Interrupt CPUIRQ29
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
RO 0b000 0011

TOP:EVTSVT:CPUIRQ30SEL

Address Offset 0x0000 047C
Physical Address 0x4002 547C Instance 0x4002 547C
Description Output Selection for CPU Interrupt CPUIRQ30
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
RO 0b000 0100

TOP:EVTSVT:CPUIRQ31SEL

Address Offset 0x0000 0480
Physical Address 0x4002 5480 Instance 0x4002 5480
Description Output Selection for CPU Interrupt CPUIRQ31
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
RO 0b000 0110

TOP:EVTSVT:CPUIRQ32SEL

Address Offset 0x0000 0484
Physical Address 0x4002 5484 Instance 0x4002 5484
Description Output Selection for CPU Interrupt CPUIRQ32
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
RO 0b000 0111

TOP:EVTSVT:SYSTIMC0SEL

Address Offset 0x0000 0488
Physical Address 0x4002 5488 Instance 0x4002 5488
Description Output Selection for CPU Interrupt SYSTIMC0
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
RO 0b000 0100

TOP:EVTSVT:SYSTIMC1SEL

Address Offset 0x0000 048C
Physical Address 0x4002 548C Instance 0x4002 548C
Description Output Selection for CPU Interrupt SYSTIMC1
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:SYSTIMC2SEL

Address Offset 0x0000 0490
Physical Address 0x4002 5490 Instance 0x4002 5490
Description Output Selection for CPU Interrupt SYSTIMC2
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
RO 0b011 0010

TOP:EVTSVT:SYSTIMC3SEL

Address Offset 0x0000 0494
Physical Address 0x4002 5494 Instance 0x4002 5494
Description Output Selection for CPU Interrupt SYSTIMC3
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
RO 0b011 0011

TOP:EVTSVT:SYSTIMC4SEL

Address Offset 0x0000 0498
Physical Address 0x4002 5498 Instance 0x4002 5498
Description Output Selection for CPU Interrupt SYSTIMC4
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
RO 0b011 0100

TOP:EVTSVT:SYSTIMC5SEL

Address Offset 0x0000 049C
Physical Address 0x4002 549C Instance 0x4002 549C
Description Output Selection for CPU Interrupt SYSTIMC5
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:ADCTRGSEL

Address Offset 0x0000 04A0
Physical Address 0x4002 54A0 Instance 0x4002 54A0
Description Output Selection for CPU Interrupt ADCTRG
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPTSYNCSEL

Address Offset 0x0000 04A4
Physical Address 0x4002 54A4 Instance 0x4002 54A4
Description Output Selection for CPU Interrupt LGPTSYNC
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT0IN0SEL

Address Offset 0x0000 04A8
Physical Address 0x4002 54A8 Instance 0x4002 54A8
Description Output Selection for CPU Interrupt LGPT0IN0
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT0IN1SEL

Address Offset 0x0000 04AC
Physical Address 0x4002 54AC Instance 0x4002 54AC
Description Output Selection for CPU Interrupt LGPT0IN1
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT0IN2SEL

Address Offset 0x0000 04B0
Physical Address 0x4002 54B0 Instance 0x4002 54B0
Description Output Selection for CPU Interrupt LGPT0IN2
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT0TENSEL

Address Offset 0x0000 04B4
Physical Address 0x4002 54B4 Instance 0x4002 54B4
Description Output Selection for CPU Interrupt LGPT0TEN
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT1IN0SEL

Address Offset 0x0000 04B8
Physical Address 0x4002 54B8 Instance 0x4002 54B8
Description Output Selection for CPU Interrupt LGPT1IN0
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT1IN1SEL

Address Offset 0x0000 04BC
Physical Address 0x4002 54BC Instance 0x4002 54BC
Description Output Selection for CPU Interrupt LGPT1IN1
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT1IN2SEL

Address Offset 0x0000 04C0
Physical Address 0x4002 54C0 Instance 0x4002 54C0
Description Output Selection for CPU Interrupt LGPT1IN2
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT1TENSEL

Address Offset 0x0000 04C4
Physical Address 0x4002 54C4 Instance 0x4002 54C4
Description Output Selection for CPU Interrupt LGPT1TEN
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT2IN0SEL

Address Offset 0x0000 04C8
Physical Address 0x4002 54C8 Instance 0x4002 54C8
Description Output Selection for CPU Interrupt LGPT2IN0
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT2IN1SEL

Address Offset 0x0000 04CC
Physical Address 0x4002 54CC Instance 0x4002 54CC
Description Output Selection for CPU Interrupt LGPT2IN1
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT2IN2SEL

Address Offset 0x0000 04D0
Physical Address 0x4002 54D0 Instance 0x4002 54D0
Description Output Selection for CPU Interrupt LGPT2IN2
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT2TENSEL

Address Offset 0x0000 04D4
Physical Address 0x4002 54D4 Instance 0x4002 54D4
Description Output Selection for CPU Interrupt LGPT2TEN
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT3IN0SEL

Address Offset 0x0000 04D8
Physical Address 0x4002 54D8 Instance 0x4002 54D8
Description Output Selection for CPU Interrupt LGPT3IN0
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT3IN1SEL

Address Offset 0x0000 04DC
Physical Address 0x4002 54DC Instance 0x4002 54DC
Description Output Selection for CPU Interrupt LGPT3IN1
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT3IN2SEL

Address Offset 0x0000 04E0
Physical Address 0x4002 54E0 Instance 0x4002 54E0
Description Output Selection for CPU Interrupt LGPT3IN2
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LGPT3TENSEL

Address Offset 0x0000 04E4
Physical Address 0x4002 54E4 Instance 0x4002 54E4
Description Output Selection for CPU Interrupt LGPT3TEN
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:LRFDIN0SEL

Address Offset 0x0000 04E8
Physical Address 0x4002 54E8 Instance 0x4002 54E8
Description Output Selection for CPU Interrupt LRFDIN0
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
RO 0b010 0101

TOP:EVTSVT:LRFDIN1SEL

Address Offset 0x0000 04EC
Physical Address 0x4002 54EC Instance 0x4002 54EC
Description Output Selection for CPU Interrupt LRFDIN1
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
RO 0b010 0110

TOP:EVTSVT:LRFDIN2SEL

Address Offset 0x0000 04F0
Physical Address 0x4002 54F0 Instance 0x4002 54F0
Description Output Selection for CPU Interrupt LRFDIN2
Type RO
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read only selection value
Value ENUM Name Description
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
RO 0b010 0111

TOP:EVTSVT:I2SSTMPSEL

Address Offset 0x0000 04F4
Physical Address 0x4002 54F4 Instance 0x4002 54F4
Description Output Selection for CPU Interrupt I2SSTMP
Type RW
Bits Field Name Description Type Reset
31:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000
21:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:DMACH0SEL

Address Offset 0x0000 0C00
Physical Address 0x4002 5C00 Instance 0x4002 5C00
Description Output Selection for DMA CH0
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b0 0000 0000 0000 0000 0000 0000
3:0 IPID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 SPI0TXTRG Selects spi0txtrg as channel source
0xD UART1RXTRG Selects uart1rxtrg as channel source
RW 0x0

TOP:EVTSVT:DMACH1SEL

Address Offset 0x0000 0C04
Physical Address 0x4002 5C04 Instance 0x4002 5C04
Description Output Selection for DMA CH1
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b0 0000 0000 0000 0000 0000 0000
3:0 IPID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x1 SPI0RXTRG Selects spi0rxtrg as channel source
0xC UART1TXTRG Selects uart1txtrg as channel source
RW 0x0

TOP:EVTSVT:DMACH2SEL

Address Offset 0x0000 0C08
Physical Address 0x4002 5C08 Instance 0x4002 5C08
Description Output Selection for DMA CH2
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b0 0000 0000 0000 0000 0000 0000
3:0 IPID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x2 LRFDTRG Selects lrfdtrg as channel source
0x6 UART0TXTRG Selects uart0txtrg as channel source
RW 0x0

TOP:EVTSVT:DMACH3SEL

Address Offset 0x0000 0C0C
Physical Address 0x4002 5C0C Instance 0x4002 5C0C
Description Output Selection for DMA CH3
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b0 0000 0000 0000 0000 0000 0000
3:0 IPID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x5 ADC0TRG Selects adc0trg as channel source
0x7 UART0RXTRG Selects uart0rxtrg as channel source
RW 0x0

TOP:EVTSVT:DMACH4SEL

Address Offset 0x0000 0C10
Physical Address 0x4002 5C10 Instance 0x4002 5C10
Description Output Selection for DMA CH4
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b0 0000 0000 0000 0000 0000 0000
3:0 IPID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x2 LRFDTRG Selects lrfdtrg as channel source
0x3 LAESTRGA Selects laestrga as channel source
RW 0x0

TOP:EVTSVT:DMACH5SEL

Address Offset 0x0000 0C14
Physical Address 0x4002 5C14 Instance 0x4002 5C14
Description Output Selection for DMA CH5
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b0 0000 0000 0000 0000 0000 0000
3:0 IPID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x4 LAESTRGB Selects laestrgb as channel source
0x5 ADC0TRG Selects adc0trg as channel source
RW 0x0

TOP:EVTSVT:DMACH6SEL

Address Offset 0x0000 0C18
Physical Address 0x4002 5C18 Instance 0x4002 5C18
Description Output Selection for DMA CH6
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b0 0000 0000 0000 0000 0000 0000
3:0 IPID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x8 CANTRGA Selects cantrga as channel source
0xA SPI1TXTRG Selects spi1txtrg as channel source
RW 0x0

TOP:EVTSVT:DMACH7SEL

Address Offset 0x0000 0C1C
Physical Address 0x4002 5C1C Instance 0x4002 5C1C
Description Output Selection for DMA CH7
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b0 0000 0000 0000 0000 0000 0000
3:0 IPID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x9 CANTRGB Selects cantrgb as channel source
0xB SPI1RXTRG Selects spi1rxtrg as channel source
RW 0x0

TOP:EVTSVT:DMACH10SEL

Address Offset 0x0000 0C20
Physical Address 0x4002 5C20 Instance 0x4002 5C20
Description Output Selection for DMA CH10
Type RW
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
16 EDGDETDIS Edge detect disable.
0: Enabled.
1: Disabled		 RW 0
15:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b0 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:DMACH11SEL

Address Offset 0x0000 0C24
Physical Address 0x4002 5C24 Instance 0x4002 5C24
Description Output Selection for DMA CH11
Type RW
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
16 EDGDETDIS Edge detect disable.
0: Enabled.
1: Disabled		 RW 0
15:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b0 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:DMACH8SEL

Address Offset 0x0000 0C28
Physical Address 0x4002 5C28 Instance 0x4002 5C28
Description Output Selection for DMA CH8
Type RW
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
16 EDGDETDIS Edge detect disable.
0: Enabled.
1: Disabled		 RW 0
15:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b0 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000

TOP:EVTSVT:DMACH9SEL

Address Offset 0x0000 0C2C
Physical Address 0x4002 5C2C Instance 0x4002 5C2C
Description Output Selection for DMA CH9
Type RW
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
16 EDGDETDIS Edge detect disable.
0: Enabled.
1: Disabled		 RW 0
15:7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b0 0000 0000
6:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x10 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x11 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0x12 GPIO_EVT0 GPIO generic published event 0, controlled by GPIO:EVTCFG
0x13 FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0x14 LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0x15 LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0x16 LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0x17 SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x18 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x19 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x1A LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x1B LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x1C DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x1D DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x1E AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x1F UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x20 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x21 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x22 SYSTIM_LT SYSTIM interrupt driven by synchroinizing LFTICK signal to SVT clock
0x23 SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x24 SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x25 SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x26 SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x27 SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x28 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x29 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x2A LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x2B LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x2C LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x2D LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x2E LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x2F LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x30 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x31 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x32 LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x33 LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x34 LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x35 UART1_COMB UART1 combined interrupt, interrupt flags are found here UART0:MIS
0x36 LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x37 LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x38 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x39 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x3A LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x3B LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x3C LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x3D LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x3E LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x3F LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x40 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x41 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
0x42 I2S_IRQ I2S interrupt event, controlled by I2S:IRQMASK
0x43 CAN_IRQ MCAN interrupt event, interrupt flags can be found here MCAN:MIS0
0x44 CAN_EVT MCAN general event, interrupt flags can be found here MCAN:MIS1
0x45 SPI1_COMB SPI1 combined interrupt request, interrupt flags can be found here SPI1:MIS
0x46 VCE_IRQ VCE IRQ
0x4B GPIO_EVT1 GPIO generic published event 1, controlled by GPIO:EVTCFG
0x4C SYSTIM5 SYSTIM Channel 5 event
RW 0b000 0000


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