CKMD

Instance: CKMD
Component: CKMD
Base address: 0x40001000


Clock Controller

TOP:CKMD Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

DESC

RO

32

0x9B4B 1000

0x0000 0000

0x4000 1000

IMASK

RW

32

0x0000 0000

0x0000 0044

0x4000 1044

RIS

RO

32

0x0000 0000

0x0000 0048

0x4000 1048

MIS

RO

32

0x0000 0000

0x0000 004C

0x4000 104C

ISET

WO

32

0x0000 0000

0x0000 0050

0x4000 1050

ICLR

WO

32

0x0000 0000

0x0000 0054

0x4000 1054

IMSET

WO

32

0x0000 0000

0x0000 0058

0x4000 1058

IMCLR

WO

32

0x0000 0000

0x0000 005C

0x4000 105C

HFOSCCTL

RW

32

0x0000 0000

0x0000 0080

0x4000 1080

HFXTCTL

RW

32

0x0000 0000

0x0000 0084

0x4000 1084

LFOSCCTL

RW

32

0x0000 0000

0x0000 008C

0x4000 108C

LFXTCTL

RW

32

0x0000 0000

0x0000 0090

0x4000 1090

LFQUALCTL

RW

32

0x0000 2064

0x0000 0094

0x4000 1094

LFINCCTL

RW

32

0x9E84 8014

0x0000 0098

0x4000 1098

LFINCOVR

RW

32

0x0000 0000

0x0000 009C

0x4000 109C

AMPADCCTL

RW

32

0x0000 0000

0x0000 00A0

0x4000 10A0

HFTRACKCTL

RW

32

0x0040 0000

0x0000 00A4

0x4000 10A4

LDOCTL

RW

32

0x0000 0000

0x0000 00A8

0x4000 10A8

NABIASCTL

RW

32

0x0000 0000

0x0000 00AC

0x4000 10AC

LFMONCTL

RW

32

0x0000 0000

0x0000 00B0

0x4000 10B0

LFCLKSEL

RW

32

0x0000 0000

0x0000 00C0

0x4000 10C0

TDCCLKSEL

RW

32

0x0000 0000

0x0000 00C4

0x4000 10C4

ADCCLKSEL

RW

32

0x0000 0000

0x0000 00C8

0x4000 10C8

LFCLKSTAT

RO

32

0x01DE 8480

0x0000 00E0

0x4000 10E0

HFXTSTAT

RO

32

0x0000 0000

0x0000 00E4

0x4000 10E4

AMPADCSTAT

RO

32

0x0000 0000

0x0000 00E8

0x4000 10E8

TRACKSTAT

RW

32

0x0000 1D80

0x0000 00EC

0x4000 10EC

AMPSTAT

RO

32

0x0000 0000

0x0000 00F0

0x4000 10F0

ATBCTL0

RW

32

0x0000 0000

0x0000 0100

0x4000 1100

ATBCTL1

RW

32

0x0000 0000

0x0000 0104

0x4000 1104

DTBCTL

RW

32

0x0000 0000

0x0000 0108

0x4000 1108

TRIM0

RW

32

0x0000 0000

0x0000 0110

0x4000 1110

TRIM1

RW

32

0x006F 9439

0x0000 0114

0x4000 1114

HFXTINIT

RW

32

0x147F 8000

0x0000 0118

0x4000 1118

HFXTTARG

RW

32

0x5446 4B6D

0x0000 011C

0x4000 111C

HFXTDYN

RW

32

0x1446 4B6D

0x0000 0120

0x4000 1120

AMPCFG0

RW

32

0x003F 8882

0x0000 0124

0x4000 1124

AMPCFG1

RW

32

0x260F F0FF

0x0000 0128

0x4000 1128

LOOPCFG

RW

32

0x605E 33B2

0x0000 012C

0x4000 112C

LOOPCFG1

RW

32

0x0000 003F

0x0000 0130

0x4000 1130

AFOSCCTL

RW

32

0x0000 0000

0x0000 0140

0x4000 1140

AFTRACKCTL

RW

32

0x0999 999A

0x0000 0144

0x4000 1144

BANDGAPCTL

RW

32

0x0000 0000

0x0000 0148

0x4000 1148

AFCLKSEL

RW

32

0x0000 0000

0x0000 0150

0x4000 1150

CANCLKSEL

RW

32

0x0000 0000

0x0000 0154

0x4000 1154

TRACKSTATAF

RO

32

0x0000 1D80

0x0000 0160

0x4000 1160

TRACKSTATAF1

RO

32

0x0000 0000

0x0000 0164

0x4000 1164

TRACKSTATAF2

RW

32

0x01D8 0000

0x0000 0168

0x4000 1168

LOOPCFGAF

RW

32

0x305E 33B3

0x0000 0170

0x4000 1170

CTL

RW

32

0x0000 0000

0x0000 0200

0x4000 1200

STAT

RO

32

0x0000 0006

0x0000 0204

0x4000 1204

RESULT

RO

32

0x0000 0002

0x0000 0208

0x4000 1208

SATCFG

RW

32

0x0000 0000

0x0000 020C

0x4000 120C

TRIGSRC

RW

32

0x0000 0000

0x0000 0210

0x4000 1210

TRIGCNT

RW

32

0x0000 0000

0x0000 0214

0x4000 1214

TRIGCNTLOAD

RW

32

0x0000 0000

0x0000 0218

0x4000 1218

TRIGCNTCFG

RW

32

0x0000 0000

0x0000 021C

0x4000 121C

PRECTL

RW

32

0x0000 0000

0x0000 0220

0x4000 1220

PRECNTR

RW

32

0x0000 0000

0x0000 0224

0x4000 1224

CNT

RW

32

0x0000 0000

0x0000 0300

0x4000 1300

TEST

RW

32

0x0000 0000

0x0000 0304

0x4000 1304

LOCK

RW

32

0x0000 0001

0x0000 0308

0x4000 1308

TOP:CKMD Register Descriptions

TOP:CKMD:DESC

Address Offset 0x0000 0000
Physical Address 0x4000 1000 Instance 0x4000 1000
Description IP Description
Type RO
Bits Field Name Description Type Reset
31:16 MODID Module identifier RO 0x9B4B
15:12 STDIPOFF Standard IP MMR block offset RO 0x1
11:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
7:4 MAJREV Major revision RO 0x0
3:0 MINREV Minor revision RO 0x0

TOP:CKMD:IMASK

Address Offset 0x0000 0044
Physical Address 0x4000 1044 Instance 0x4000 1044
Description Interrupt mask register
Type RW
Bits Field Name Description Type Reset
31:21 RESERVED21 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
20 SYSUNDERCLOCKED Indicates system frequency has been lowered. It will be set only if HFTRACKCTL.UNDERCLK is appropriately configured and HFOSC tracking loop is not running. RW 0
19 AFOSCGOOD AFOSC good indication. RW 0
18 TRACKREFAFOOR Out-of-range indication from the AFOSC tracking loop.

Indicates that the reference clock frequency of AFOSC tracking loop is out-of-range.		 RW 0
17 LFTICK 32kHz TICK to RTC and WDT.

Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.		 RW 0
16 LFGEARRSTRT LFINC filter gearing restart.

Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.		 RW 0
15 AMPSETTLED HFXT Amplitude compensation - settled

Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.		 RW 0
14 AMPCTRLATTARG HFXT Amplitude compensation - controls at target

Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.		 RW 0
13 PRELFEDGE Pre-LF clock edge detect.

Indicates that a positive edge occured on the selected pre-LF clock CLKSEL.PRELFCLK'
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.		 RW 0
12 LFCLKLOSS LF clock is lost.

Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.		 RW 0
11 LFCLKOOR LF clock period out-of-range.

Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.		 RW 0
10 LFCLKGOOD LF clock good.

Indicates that the LF clock is good, according to the configuration in LFQUALCTL.		 RW 0
9 LFINCUPD LFINC updated.

Indicates that a new LFINC measurement value is available in CKM.LFCLKSTAT.		 RW 0
8 TDCDONE TDC done event.

Indicates that the TDC measurement is done.		 RW 0
7 ADCPEAKUPD HFXT-ADC PEAK measurement update event.

Indicates that the HFXT-ADC PEAK measurement is done.		 RW 0
6 ADCBIASUPD HFXT-ADC BIAS measurement update event.

Indicates that the HFXT-ADC BIAS measurement is done.		 RW 0
5 ADCCOMPUPD HFXT-ADC comparison update event.

Indicates that the HFXT-ADC comparison is done.		 RW 0
4 TRACKREFOOR Out-of-range indication from the tracking loop.

Indicates that the selected reference clock frequency of the tracking loop is out-of-range.		 RW 0
3 TRACKREFLOSS Clock loss indication from the tracking loop.

Indicates that the selected reference clock of the tracking loop is lost.		 RW 0
2 HFXTAMPGOOD HFXT amplitude good indication. RW 0
1 HFXTFAULT HFXT fault indication.

Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.		 RW 0
0 HFXTGOOD HFXT good indication.

Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.		 RW 0

TOP:CKMD:RIS

Address Offset 0x0000 0048
Physical Address 0x4000 1048 Instance 0x4000 1048
Description Raw interrupt flag register
Type RO
Bits Field Name Description Type Reset
31:21 RESERVED21 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
20 SYSUNDERCLOCKED Indicates system frequency has been lowered. It will be set only if HFTRACKCTL.UNDERCLK is appropriately configured and HFOSC tracking loop is not running. RO 0
19 AFOSCGOOD AFOSC good indication. RO 0
18 TRACKREFAFOOR Out-of-range indication from the AFOSC tracking loop.

Indicates that the reference clock frequency of AFOSC tracking loop is out-of-range.		 RO 0
17 LFTICK 32kHz TICK to RTC and WDT.

Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.		 RO 0
16 LFGEARRSTRT LFINC filter gearing restart.

Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.		 RO 0
15 AMPSETTLED HFXT Amplitude compensation - settled

Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.		 RO 0
14 AMPCTRLATTARG HFXT Amplitude compensation - controls at target

Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.		 RO 0
13 PRELFEDGE Pre-LF clock edge detect.

Indicates that a positive edge occured on the selected pre-LF clock CLKSEL.PRELFCLK'
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.		 RO 0
12 LFCLKLOSS LF clock is lost.

Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.		 RO 0
11 LFCLKOOR LF clock period out-of-range.

Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.		 RO 0
10 LFCLKGOOD LF clock good.

Indicates that the LF clock is good, according to the configuration in LFQUALCTL.		 RO 0
9 LFINCUPD LFINC updated.

Indicates that a new LFINC measurement value is available in CKM.LFCLKSTAT.		 RO 0
8 TDCDONE TDC done event.

Indicates that the TDC measurement is done.		 RO 0
7 ADCPEAKUPD HFXT-ADC PEAK measurement update event.

Indicates that the HFXT-ADC PEAK measurement is done.		 RO 0
6 ADCBIASUPD HFXT-ADC BIAS measurement update event.

Indicates that the HFXT-ADC BIAS measurement is done.		 RO 0
5 ADCCOMPUPD HFXT-ADC comparison update event.

Indicates that the HFXT-ADC comparison is done.		 RO 0
4 TRACKREFOOR Out-of-range indication from the tracking loop.

Indicates that the selected reference clock frequency of the tracking loop is out-of-range.		 RO 0
3 TRACKREFLOSS Clock loss indication from the tracking loop.

Indicates that the selected reference clock of the tracking loop is lost.		 RO 0
2 HFXTAMPGOOD HFXT amplitude good indication. RO 0
1 HFXTFAULT HFXT fault indication.

Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.		 RO 0
0 HFXTGOOD HFXT good indication.

Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.		 RO 0

TOP:CKMD:MIS

Address Offset 0x0000 004C
Physical Address 0x4000 104C Instance 0x4000 104C
Description Masked interrupt flag register
Type RO
Bits Field Name Description Type Reset
31:21 RESERVED21 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
20 SYSUNDERCLOCKED Indicates system frequency has been lowered. It will be set only if HFTRACKCTL.UNDERCLK is appropriately configured and HFOSC tracking loop is not running. RO 0
19 AFOSCGOOD AFOSC good indication. RO 0
18 TRACKREFAFOOR Out-of-range indication from the AFOSC tracking loop.

Indicates that the reference clock frequency of AFOSC tracking loop is out-of-range.		 RO 0
17 LFTICK 32kHz TICK to RTC and WDT.

Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.		 RO 0
16 LFGEARRSTRT LFINC filter gearing restart.

Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.		 RO 0
15 AMPSETTLED HFXT Amplitude compensation - settled

Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.		 RO 0
14 AMPCTRLATTARG HFXT Amplitude compensation - controls at target

Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.		 RO 0
13 PRELFEDGE Pre-LF clock edge detect.

Indicates that a positive edge occured on the selected pre-LF clock CLKSEL.PRELFCLK'
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.		 RO 0
12 LFCLKLOSS LF clock is lost.

Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.		 RO 0
11 LFCLKOOR LF clock period out-of-range.

Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.		 RO 0
10 LFCLKGOOD LF clock good.

Indicates that the LF clock is good, according to the configuration in LFQUALCTL.		 RO 0
9 LFINCUPD LFINC updated.

Indicates that a new LFINC measurement value is available in CKM.LFCLKSTAT.		 RO 0
8 TDCDONE TDC done event.

Indicates that the TDC measurement is done.		 RO 0
7 ADCPEAKUPD HFXT-ADC PEAK measurement update event.

Indicates that the HFXT-ADC PEAK measurement is done.		 RO 0
6 ADCBIASUPD HFXT-ADC BIAS measurement update event.

Indicates that the HFXT-ADC BIAS measurement is done.		 RO 0
5 ADCCOMPUPD HFXT-ADC comparison update event.

Indicates that the HFXT-ADC comparison is done.		 RO 0
4 TRACKREFOOR Out-of-range indication from the tracking loop.

Indicates that the selected reference clock frequency of the tracking loop is out-of-range.		 RO 0
3 TRACKREFLOSS Clock loss indication from the tracking loop.

Indicates that the selected reference clock of the tracking loop is lost.		 RO 0
2 HFXTAMPGOOD HFXT amplitude good indication. RO 0
1 HFXTFAULT HFXT fault indication.

Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.		 RO 0
0 HFXTGOOD HFXT good indication.

Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.		 RO 0

TOP:CKMD:ISET

Address Offset 0x0000 0050
Physical Address 0x4000 1050 Instance 0x4000 1050
Description Interrupt flag set register
Type WO
Bits Field Name Description Type Reset
31:21 RESERVED21 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
20 SYSUNDERCLOCKED Indicates system frequency has been lowered. It will be set only if HFTRACKCTL.UNDERCLK is appropriately configured and HFOSC tracking loop is not running. WO 0
19 AFOSCGOOD AFOSC good indication. WO 0
18 TRACKREFAFOOR Out-of-range indication from the AFOSC tracking loop.

Indicates that the reference clock frequency of AFOSC tracking loop is out-of-range.		 WO 0
17 LFTICK 32kHz TICK to RTC and WDT.

Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.		 WO 0
16 LFGEARRSTRT LFINC filter gearing restart.

Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.		 WO 0
15 AMPSETTLED HFXT Amplitude compensation - settled

Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.		 WO 0
14 AMPCTRLATTARG HFXT Amplitude compensation - controls at target

Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.		 WO 0
13 PRELFEDGE Pre-LF clock edge detect.

Indicates that a positive edge occured on the selected pre-LF clock CLKSEL.PRELFCLK'
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.		 WO 0
12 LFCLKLOSS LF clock is lost.

Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.		 WO 0
11 LFCLKOOR LF clock period out-of-range.

Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.		 WO 0
10 LFCLKGOOD LF clock good.

Indicates that the LF clock is good, according to the configuration in LFQUALCTL.		 WO 0
9 LFINCUPD LFINC updated.

Indicates that a new LFINC measurement value is available in CKM.LFCLKSTAT.		 WO 0
8 TDCDONE TDC done event.

Indicates that the TDC measurement is done.		 WO 0
7 ADCPEAKUPD HFXT-ADC PEAK measurement update event.

Indicates that the HFXT-ADC PEAK measurement is done.		 WO 0
6 ADCBIASUPD HFXT-ADC BIAS measurement update event.

Indicates that the HFXT-ADC BIAS measurement is done.		 WO 0
5 ADCCOMPUPD HFXT-ADC comparison update event.

Indicates that the HFXT-ADC comparison is done.		 WO 0
4 TRACKREFOOR Out-of-range indication from the tracking loop.

Indicates that the selected reference clock frequency of the tracking loop is out-of-range.		 WO 0
3 TRACKREFLOSS Clock loss indication from the tracking loop.

Indicates that the selected reference clock of the tracking loop is lost.		 WO 0
2 HFXTAMPGOOD HFXT amplitude good indication. WO 0
1 HFXTFAULT HFXT fault indication.

Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.		 WO 0
0 HFXTGOOD HFXT good indication.

Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.		 WO 0

TOP:CKMD:ICLR

Address Offset 0x0000 0054
Physical Address 0x4000 1054 Instance 0x4000 1054
Description Interrupt flag clear register
Type WO
Bits Field Name Description Type Reset
31:21 RESERVED21 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
20 SYSUNDERCLOCKED Indicates system frequency has been lowered. It will be set only if HFTRACKCTL.UNDERCLK is appropriately configured and HFOSC tracking loop is not running. WO 0
19 AFOSCGOOD AFOSC good indication. WO 0
18 TRACKREFAFOOR Out-of-range indication from the AFOSC tracking loop.

Indicates that the reference clock frequency of AFOSC tracking loop is out-of-range.		 WO 0
17 LFTICK 32kHz TICK to RTC and WDT.

Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.		 WO 0
16 LFGEARRSTRT LFINC filter gearing restart.

Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.		 WO 0
15 AMPSETTLED HFXT Amplitude compensation - settled

Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.		 WO 0
14 AMPCTRLATTARG HFXT Amplitude compensation - controls at target

Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.		 WO 0
13 PRELFEDGE Pre-LF clock edge detect.

Indicates that a positive edge occured on the selected pre-LF clock CLKSEL.PRELFCLK'
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.		 WO 0
12 LFCLKLOSS LF clock is lost.

Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.		 WO 0
11 LFCLKOOR LF clock period out-of-range.

Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.		 WO 0
10 LFCLKGOOD LF clock good.

Indicates that the LF clock is good, according to the configuration in LFQUALCTL.		 WO 0
9 LFINCUPD LFINC updated.

Indicates that a new LFINC measurement value is available in CKM.LFCLKSTAT.		 WO 0
8 TDCDONE TDC done event.

Indicates that the TDC measurement is done.		 WO 0
7 ADCPEAKUPD HFXT-ADC PEAK measurement update event.

Indicates that the HFXT-ADC PEAK measurement is done.		 WO 0
6 ADCBIASUPD HFXT-ADC BIAS measurement update event.

Indicates that the HFXT-ADC BIAS measurement is done.		 WO 0
5 ADCCOMPUPD HFXT-ADC comparison update event.

Indicates that the HFXT-ADC comparison is done.		 WO 0
4 TRACKREFOOR Out-of-range indication from the tracking loop.

Indicates that the selected reference clock frequency of the tracking loop is out-of-range.		 WO 0
3 TRACKREFLOSS Clock loss indication from the tracking loop.

Indicates that the selected reference clock of the tracking loop is lost.		 WO 0
2 HFXTAMPGOOD HFXT amplitude good indication. WO 0
1 HFXTFAULT HFXT fault indication.

Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.		 WO 0
0 HFXTGOOD HFXT good indication.

Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.		 WO 0

TOP:CKMD:IMSET

Address Offset 0x0000 0058
Physical Address 0x4000 1058 Instance 0x4000 1058
Description Interrupt mask set register
Type WO
Bits Field Name Description Type Reset
31:21 RESERVED21 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
20 SYSUNDERCLOCKED Indicates system frequency has been lowered. It will be set only if HFTRACKCTL.UNDERCLK is appropriately configured and HFOSC tracking loop is not running. WO 0
19 AFOSCGOOD AFOSC good indication. WO 0
18 TRACKREFAFOOR Out-of-range indication from the AFOSC tracking loop.

Indicates that the reference clock frequency of AFOSC tracking loop is out-of-range.		 WO 0
17 LFTICK 32kHz TICK to RTC and WDT.

Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.		 WO 0
16 LFGEARRSTRT LFINC filter gearing restart.

Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.		 WO 0
15 AMPSETTLED HFXT Amplitude compensation - settled

Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.		 WO 0
14 AMPCTRLATTARG HFXT Amplitude compensation - controls at target

Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.		 WO 0
13 PRELFEDGE Pre-LF clock edge detect.

Indicates that a positive edge occured on the selected pre-LF clock CLKSEL.PRELFCLK'
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.		 WO 0
12 LFCLKLOSS LF clock is lost.

Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.		 WO 0
11 LFCLKOOR LF clock period out-of-range.

Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.		 WO 0
10 LFCLKGOOD LF clock good.

Indicates that the LF clock is good, according to the configuration in LFQUALCTL.		 WO 0
9 LFINCUPD LFINC updated.

Indicates that a new LFINC measurement value is available in CKM.LFCLKSTAT.		 WO 0
8 TDCDONE TDC done event.

Indicates that the TDC measurement is done.		 WO 0
7 ADCPEAKUPD HFXT-ADC PEAK measurement update event.

Indicates that the HFXT-ADC PEAK measurement is done.		 WO 0
6 ADCBIASUPD HFXT-ADC BIAS measurement update event.

Indicates that the HFXT-ADC BIAS measurement is done.		 WO 0
5 ADCCOMPUPD HFXT-ADC comparison update event.

Indicates that the HFXT-ADC comparison is done.		 WO 0
4 TRACKREFOOR Out-of-range indication from the tracking loop.

Indicates that the selected reference clock frequency of the tracking loop is out-of-range.		 WO 0
3 TRACKREFLOSS Clock loss indication from the tracking loop.

Indicates that the selected reference clock of the tracking loop is lost.		 WO 0
2 HFXTAMPGOOD HFXT amplitude good indication. WO 0
1 HFXTFAULT HFXT fault indication.

Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.		 WO 0
0 HFXTGOOD HFXT good indication.

Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.		 WO 0

TOP:CKMD:IMCLR

Address Offset 0x0000 005C
Physical Address 0x4000 105C Instance 0x4000 105C
Description Interrupt mask clear register
Type WO
Bits Field Name Description Type Reset
31:21 RESERVED21 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
20 SYSUNDERCLOCKED Indicates system frequency has been lowered. It will be set only if HFTRACKCTL.UNDERCLK is appropriately configured and HFOSC tracking loop is not running. WO 0
19 AFOSCGOOD AFOSC good indication. WO 0
18 TRACKREFAFOOR Out-of-range indication from the AFOSC tracking loop.

Indicates that the reference clock frequency of AFOSC tracking loop is out-of-range.		 WO 0
17 LFTICK 32kHz TICK to RTC and WDT.

Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.		 WO 0
16 LFGEARRSTRT LFINC filter gearing restart.

Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.		 WO 0
15 AMPSETTLED HFXT Amplitude compensation - settled

Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.		 WO 0
14 AMPCTRLATTARG HFXT Amplitude compensation - controls at target

Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.		 WO 0
13 PRELFEDGE Pre-LF clock edge detect.

Indicates that a positive edge occured on the selected pre-LF clock CLKSEL.PRELFCLK'
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.		 WO 0
12 LFCLKLOSS LF clock is lost.

Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.		 WO 0
11 LFCLKOOR LF clock period out-of-range.

Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.		 WO 0
10 LFCLKGOOD LF clock good.

Indicates that the LF clock is good, according to the configuration in LFQUALCTL.		 WO 0
9 LFINCUPD LFINC updated.

Indicates that a new LFINC measurement value is available in CKM.LFCLKSTAT.		 WO 0
8 TDCDONE TDC done event.

Indicates that the TDC measurement is done.		 WO 0
7 ADCPEAKUPD HFXT-ADC PEAK measurement update event.

Indicates that the HFXT-ADC PEAK measurement is done.		 WO 0
6 ADCBIASUPD HFXT-ADC BIAS measurement update event.

Indicates that the HFXT-ADC BIAS measurement is done.		 WO 0
5 ADCCOMPUPD HFXT-ADC comparison update event.

Indicates that the HFXT-ADC comparison is done.		 WO 0
4 TRACKREFOOR Out-of-range indication from the tracking loop.

Indicates that the selected reference clock frequency of the tracking loop is out-of-range.		 WO 0
3 TRACKREFLOSS Clock loss indication from the tracking loop.

Indicates that the selected reference clock of the tracking loop is lost.		 WO 0
2 HFXTAMPGOOD HFXT amplitude good indication. WO 0
1 HFXTFAULT HFXT fault indication.

Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.		 WO 0
0 HFXTGOOD HFXT good indication.

Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.		 WO 0

TOP:CKMD:HFOSCCTL

Address Offset 0x0000 0080
Physical Address 0x4000 1080 Instance 0x4000 1080
Description High frequency oscillator control
Type RW
Bits Field Name Description Type Reset
31:24 PW Password protection for QUALBYP and FORCEOFF.

Write this field to 0xA5 to accept writes to QUALBYP and FORCEOFF.		 WO 0x00
23:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
1 FORCEOFF Force HFOSC off.

Once this MMR is set, the system will stop. The only way to start the system again is system reset.
This field is locked using the global-lock within SYS0.		 RW 0
0 QUALBYP Clock qualification bypass.

HFOSC qualification will skip a fixed number of clock cycles to prevent glitches
or frequency overshoots from reaching the system. Setting this bit will bypass the qualification.
This bit can be locked in SYS0. If unlocked, it is password protected with PW.		 RW 0

TOP:CKMD:HFXTCTL

Address Offset 0x0000 0084
Physical Address 0x4000 1084 Instance 0x4000 1084
Description High frequency crystal control
Type RW
Bits Field Name Description Type Reset
31 AMPOVR Software override for the amplitude compensation FSM

Directly use control values in CKM.HFXTDYN0 and CKM.HFXTDYN1.
Control injection and clock buffer using INJECT and LPBUFEN.		 RW 0
30:27 RESERVED27 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
26 BIASEN HFXT bias enable.

Controls the biasing if AMPOVR is set.
Otherwise, the biasing is controlled by the amplitude compensation FSM.		 RW 0
25 LPBUFEN Low power clock buffer enable.

Controls the clock buffer if AMPOVR is set.
Otherwise, the buffer is controlled by the amplitude compensation FSM.		 RW 0
24 INJECT Control HFXT injection if AMPOVR is set. RW 0
23 QUALBYP Bypass HFXT clock qualification.
Enables HFXT propagation to the system without waiting for the qualification circuit.		 RW 0
22:20 RESERVED20 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
19:8 QUALDLY Skip potentially unstable clock cycles after enabling HFXT.
Number of cycles skipped is 8*QUALDLY.		 RW 0x000
7 TCXOMODE Temperature compensated crystal oscillator mode.

Set this bit if a TXCO is connected.		 RW 0
6 TCXOTYPE Type of temperature compensated crystal used.

Only has effect if TCXOMODE is set.
Value ENUM Name Description
0x0 CLIPPEDSINE
0x1 CMOS
RW 0
5:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
2 AUTOEN Automatic enable.

If this bit is set, EN will automatically be set at wakeup or before (using pre-wake mechanism in RTC).		 RW 0
1 HPBUFEN High performance clock buffer enable.

This bit controls the clock output for the RF PLL.
It is required for radio operation.		 RW 0
0 EN HFXT enable.

Setting this bit will enable HFXT. It will automatically be cleared upon STANDBY entry.
If AUTOEN is set, this bit will be set automatically on wakeup or before (pre-wake mechanism in RTC).		 RW 0

TOP:CKMD:LFOSCCTL

Address Offset 0x0000 008C
Physical Address 0x4000 108C Instance 0x4000 108C
Description Low frequency oscillator control
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 EN LFOSC enable RW 0

TOP:CKMD:LFXTCTL

Address Offset 0x0000 0090
Physical Address 0x4000 1090 Instance 0x4000 1090
Description Low frequency crystal control
Type RW
Bits Field Name Description Type Reset
31:15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000
14:13 LEAKCOMP Leakage compensation control
Value ENUM Name Description
0x0 FULL Full leakage compensation
0x1 HALF Half leakage compensation
0x3 OFF No leakage compensation
RW 0b00
12 BUFBIAS Control the BIAS current of the input amp in LP buffer
Value ENUM Name Description
0x0 MIN Minimum bias current: 25nA
0x1 MAX Maximum bias current: 50nA
RW 0
11:8 AMPBIAS Adjust current mirror ratio into oscillator core. This value is depending on crystal and is set by FW. This field uses a 2's complement encoding. RW 0x0
7:6 BIASBOOST Boost oscillator amplitude

This value depends on the crystal and needs to be configured by Firmware.		 RW 0b00
5:4 REGBIAS Regulation loop bias resistor value

This value depends on the crystal and needs to be configured by Firmware.		 RW 0b00
3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
2 HPBUFEN Control the buffer used. In normal operation, low-power buffer is used in all device modes. The high-performance buffer is only used for test purposes. RW 0
1 AMPREGEN Amplitude regulation loop enable RW 0
0 EN LFXT enable RW 0

TOP:CKMD:LFQUALCTL

Address Offset 0x0000 0094
Physical Address 0x4000 1094 Instance 0x4000 1094
Description Low frequency clock qualification control
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13:8 MAXERR Maximum LFCLK period error.

Value given in microseconds, 3 integer bits + 3 fractional bits.		 RW 0b10 0000
7:0 CONSEC Number of consecutive times the LFCLK period error has to be
smaller than MAXERR to be considered "good".
Setting this value to 0 will bypass clock qualification,
and the "good" indicator will always be 1.		 RW 0x64

TOP:CKMD:LFINCCTL

Address Offset 0x0000 0098
Physical Address 0x4000 1098 Instance 0x4000 1098
Description Low frequency time increment control
Type RW
Bits Field Name Description Type Reset
31 PREVENTSTBY Controls if the LFINC filter prevents STANBY entry until settled.
Value ENUM Name Description
0x0 OFF Disable. Do not prevent STANDBY entry.
0x1 ON Enable. Prevent STANDBY entry.
RW 1
30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
29:8 INT Integral part of the LFINC filter.

This value is updated by Hardware to reflect the current state of the filter.
It can also be written to change the current state.		 RW 0b01 1110 1000 0100 1000 0000
7 STOPGEAR Controls the final gear of the LFINC filter.
Value ENUM Name Description
0x0 LOW Lowest final gear. Best settling, but less dynamic frequency tracking.
0x1 HIGH Highest final gear. Best dynamic frequency tracking, but higher variation in filter value.
RW 0
6:5 ERRTHR Controls the threshold for gearing restart of the LFINC filter.

Only effective if GEARRSTRT is not ONETHR or TWOTHR.
Value ENUM Name Description
0x0 LARGE Restart gearing on large error. Fewer false restarts, slower response on small frequency shifts.
0x1 MIDLARGE Middle value towards LARGE.
0x2 MIDSMALL Middle value towards SMALL.
0x3 SMALL Restart gearing on small error. Potentially more false restarts, faster response on small frequency shifts.
RW 0b00
4:3 GEARRSTRT Controls gearing restart of the LFINC filter.
Value ENUM Name Description
0x0 NEVER Never restart gearing. Very stable filter value, but very slow response on frequency changes.
0x1 ONETHR Restart gearing when the error accumulator crosses the threshold once.
0x2 TWOTHR Restart gearing when the error accumulator crosses the threshold twice in a row.
RW 0b10
2 SOFTRSTRT Use a higher gear after re-enabling / wakeup.

The filter will require 16-24 LFCLK periods to settle (depending on STOPGEAR), but may respond faster to frequency changes during STANDBY.
Value ENUM Name Description
0x0 OFF Don't use soft gearing restarts
0x1 ON Use soft gearing restarts
RW 1
1:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00

TOP:CKMD:LFINCOVR

Address Offset 0x0000 009C
Physical Address 0x4000 109C Instance 0x4000 109C
Description Low frequency time increment override control
Type RW
Bits Field Name Description Type Reset
31 OVERRIDE Override LF increment

Use the value provided in LFINC instead of the value calculated by Hardware.		 RW 0
30:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000
21:0 LFINC LF increment value

This value is used when OVERRIDE is set to 1.
Otherwise the value is calculated automatically.
The current LFINC value can be read from [CKM.LFCLKSTAT.LFINC].		 RW 0b00 0000 0000 0000 0000 0000

TOP:CKMD:AMPADCCTL

Address Offset 0x0000 00A0
Physical Address 0x4000 10A0 Instance 0x4000 10A0
Description Amplitude ADC control
Type RW
Bits Field Name Description Type Reset
31 SWOVR Software override.

Control Amplitude ADC from software		 RW 0
30:18 RESERVED18 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000
17 PEAKDETEN Enable HFXT Peak Detector.

If the peak detector is used by the AMPCOMP FSM, this bit can be used to keep the peak detector always enabled.
If SWOVR is set, this bit directly controls the peak detector.
Value ENUM Name Description
0x0 DISABLE Disable peak detector (unless requested by AMPCOMP FSM)
0x1 ENABLE Enable peak detector
RW 0
16 ADCEN Enable Amplitude ADC.

If the ADC is used by the AMPCOMP FSM, this bit can be used to keep the ADC always enabled.
If SWOVR is set, this bit directly controls the ADC.
Value ENUM Name Description
0x0 DISABLE Disable ADC (unless requested by AMPCOMP FSM)
0x1 ENABLE Enable ADC
RW 0
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:8 COMPVAL Comparator reference input in compare mode

This bitfield is only active if SWOVR is set. SRCSEL selects the source to be compared.
Result will be available in CKM.AMPADCSTAT.		 RW 0b000 0000
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4 SRCSEL Select the input to the ADC

Only active if SWOVR is set.
Value ENUM Name Description
0x0 BIAS Measure bias voltage
0x1 PEAK Measure HFXT peak voltage
RW 0
3:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
1 COMPSTRT Start a comparison

This bit is only active if SWOVR is set. SRCSEL selects the source to be measured.
COMPVAL configures the threshold value.
Result will be available in CKM.AMPADCSTAT.		 RW 0
0 SARSTRT Start a SAR conversion

This bit is only active if SWOVR is set. SRCSEL selects the source to be measured.
Result will be available in CKM.AMPADCSTAT.		 RW 0

TOP:CKMD:HFTRACKCTL

Address Offset 0x0000 00A4
Physical Address 0x4000 10A4 Instance 0x4000 10A4
Description High frequency tracking loop control
Type RW
Bits Field Name Description Type Reset
31 EN Enable tracking loop. RW 0
30 DSMBYP Bypass Delta-Sigma-Modulation of fine trim. RW 0
29:28 UNDERCLK When the HFOSC tracking loop is not running, this bitfield can be used to set the condition to automatically lower the HFOSC frequency. This will prevent frequency drift that may lead to SOC instability.
Value ENUM Name Description
0x0 DIS Disable
0x1 TIMER Timer event
0x2 BATMON Temperature event from Batmon
0x3 BOTH Temperature event from Batmon or Timer event
RW 0b00
27:26 REFCLK Select the reference clock for the tracking loop.
Change only while the tracking loop is disabled.
Value ENUM Name Description
0x0 HFXT Select HFXT as reference clock.
0x1 LRF Select LRF reference clock.
0x2 GPI Select GPI as reference clock.
RW 0b00
25:0 RATIO Ratio. Ratio format is 2b.24b RW 0b00 0100 0000 0000 0000 0000 0000

TOP:CKMD:LDOCTL

Address Offset 0x0000 00A8
Physical Address 0x4000 10A8 Instance 0x4000 10A8
Description LDO control

By default, the LDO is controlled by the HFXT Amplitude compensation.
This register is used for software overrides.
Type RW
Bits Field Name Description Type Reset
31 SWOVR Software override.

Control LDO from software		 RW 0
30:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
4 HFXTLVLEN Enable levelshifters from ULL to VCKM. Needs to be timer-based. Worst-case LDO startup time is 5us across PVT. RW 0
3 STARTCTL Enable faster startup.
This bit should be set together with EN, and cleared after 5us.		 RW 0
2 START Enable faster startup.
This bit should be set together with EN, and cleared after 5us.		 RW 0
1 BYPASS Bypass LDO RW 0
0 EN Enable LDO RW 0

TOP:CKMD:NABIASCTL

Address Offset 0x0000 00AC
Physical Address 0x4000 10AC Instance 0x4000 10AC
Description Nanoamp-bias control
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 EN Enable nanoamp-bias RW 0

TOP:CKMD:LFMONCTL

Address Offset 0x0000 00B0
Physical Address 0x4000 10B0 Instance 0x4000 10B0
Description Low-frequency clock-monitor control
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 EN Enable LFMONITOR.
Enable only after a LF clock source has been selected, enabled and is stable.
If LFMONITOR detects a clock loss, the system will be reset.		 RW 0

TOP:CKMD:LFCLKSEL

Address Offset 0x0000 00C0
Physical Address 0x4000 10C0 Instance 0x4000 10C0
Description Low frequency clock selection
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:2 PRE Select low frequency clock source for the PRELFCLK interrupt.

Can be used by Software to confirm that the clock is running and it's frequency is good, before selecting it in MAIN.
Value ENUM Name Description
0x0 NONE No clock. Output will be tied low.
0x1 LFOSC Low frequency on-chip oscillator
0x2 LFXT Low frequency crystal oscillator
0x3 EXTLF External LF clock through GPI.
RW 0b00
1:0 MAIN Select the main low frequency clock source.

If running, this clock will be used to generate LFTICK and as CLKULL during STANDBY.
If not running, LFTICK will be generated from HFOSC and STANDBY entry will be prevented.
Value ENUM Name Description
0x0 FAKE No LF clock selected. LFTICK will be generated from HFOSC, STANDBY entry will be prevented.
0x1 LFOSC Low frequency on-chip oscillator
0x2 LFXT Low frequency crystal oscillator
0x3 EXTLF External LF clock through GPI.
RW 0b00

TOP:CKMD:TDCCLKSEL

Address Offset 0x0000 00C4
Physical Address 0x4000 10C4 Instance 0x4000 10C4
Description TDC clock selection
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 REFCLK Select reference clock for the TDC.
Value ENUM Name Description
0x0 NONE No reference clock
0x1 CLKSVT 96MHz HFOSC clock div by 2
0x2 CLKULL 24MHz CLKULL
0x3 GPI General purpose input signal
0x4 AFOSC AFOSC clock div by 2
0x5 HFXT 48MHz HFXT
RW 0b000

TOP:CKMD:ADCCLKSEL

Address Offset 0x0000 00C8
Physical Address 0x4000 10C8 Instance 0x4000 10C8
Description ADC clock selection
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 SRC Select ADC clock source

Change only while ADC is disabled!
Value ENUM Name Description
0x0 CLKSVT 48MHz CLKSVT
0x1 HFXT 48MHz HFXT
RW 0b00

TOP:CKMD:LFCLKSTAT

Address Offset 0x0000 00E0
Physical Address 0x4000 10E0 Instance 0x4000 10E0
Description Low-frequency clock status
Type RO
Bits Field Name Description Type Reset
31 GOOD Low frequency clock good

Note: This is only a coarse frequency check based on LFQUALCTL. The clock may not be accurate enough for timing purposes.		 RO 0
30:26 RESERVED26 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
25 FLTSETTLED LFINC filter is running and settled. RO 0
24 LFTICKSRC Source of LFTICK.
Value ENUM Name Description
0x0 LFCLK LFTICK generated from the selected LFCLK
0x1 FAKE LFTICK generated from CLKULL (LFCLK not available)
RO 1
23:22 LFINCSRC Source of LFINC used by the RTC.

This value depends on LFINCOVR.OVERRIDE, LFINCCTL.AVG, LFINCCTL.EN and the device state (ACTIVE/STANDBY).
Value ENUM Name Description
0x0 MEAS Using measured value.
This value is updated by hardware and can be read from LFINC.
0x1 AVG Using filtered / average value.
This value is updated by hardware and can be read and updated in LFINCCTL.INT.
0x2 OVERRIDE Using override value from LFINCOVR.LFINC
0x3 FAKE Using FAKE LFTICKs with corresponding LFINC value.
RO 0b11
21:0 LFINC Measured value of LFINC.

Given in microseconds with 16 fractional bits.
This value is calculated by Hardware.
It is the LFCLK period according to CLKULL cycles.		 RO 0b01 1110 1000 0100 1000 0000

TOP:CKMD:HFXTSTAT

Address Offset 0x0000 00E4
Physical Address 0x4000 10E4 Instance 0x4000 10E4
Description HFXT status information
Type RO
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30:16 STARTUPTIME HFXT startup time

Can be used by software to plan starting HFXT ahead in time.
Measured whenever HFXT is enabled in CLKULL periods (24MHz), from [CKM.HFXTCTL.EN] until the clock is good for radio operation (amplitude compensation is settled).		 RO 0b000 0000 0000 0000
15:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000
1 FAULT HFXT clock fault

Indicates a lower than expected HFXT frequency.
HFXT will not recover from this fault, disabling and re-enabling HFXT is required.		 RO 0
0 GOOD HFXT clock available RO 0

TOP:CKMD:AMPADCSTAT

Address Offset 0x0000 00E8
Physical Address 0x4000 10E8 Instance 0x4000 10E8
Description HFXT Amplitude ADC Status
Type RO
Bits Field Name Description Type Reset
31:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
24 COMPOUT Most recent comparison output RO 0
23 RESERVED23 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
22:16 PEAKRAW Most recently measured peak voltage - raw

This value is the raw output of the HFXT ADC.
For the actual peak voltage use the value (PEAK + 0.0150)/0.74 + K, where 'K' is a function of process variation and is stored in FCFG1 register.		 RO 0b000 0000
15:8 PEAK Most recently measured peak voltage - bias corrected

This value is computed as 2*PEAKRAW-BIAS

Actual voltage = (2*PEAKRAW-BIAS - 0.015)/0.74 + K, where 'K' is a function of process variation and is stored in FCFG1 register.		 RO 0x00
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6:0 BIAS Most recently measured bias voltage RO 0b000 0000

TOP:CKMD:TRACKSTAT

Address Offset 0x0000 00EC
Physical Address 0x4000 10EC Instance 0x4000 10EC
Description HF tracking loop status information
Type RW
Bits Field Name Description Type Reset
31 LOOPERRVLD Current HFOSC tracking error valid

This bit is one if the tracking loop is running and the error value is valid.		 RO 0
30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
29:16 LOOPERR Current HFOSC tracking error

This field uses the internal fractional representation (sign, 9 integer bits, 4 fractional bits).		 RO 0b00 0000 0000 0000
15:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
12:0 FINETRIM Current HFOSC Fine-trim value

This field uses the internal fractional representation (sign, 5 integer bits, 7 fractional bits).
The actual trim value applied to the oscillator is delta-sigma modulated 6 bits non-signed
(inverted sign bit + integer bits).

INTERNAL
This field can be written by also writing a magic value (0xA5) into LOOPERR (bits 23:16)		 RO 0b1 1101 1000 0000

TOP:CKMD:AMPSTAT

Address Offset 0x0000 00F0
Physical Address 0x4000 10F0 Instance 0x4000 10F0
Description HFXT Amplitude Compensation Status
Type RO
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:25 STATE Current AMPCOMP FSM state.
Value ENUM Name Description
0x0 IDLE
0x1 LDOSTART
0x2 SHUTDN1
0x3 INJECT
0x4 RAMP1
0x5 RAMP0
0x6 UPDATEDN
0x7 INJWAIT
0xA SHUTDN0
0xC TXCOMODE
0xE UPDATEUP
0xF SETTLED
RO 0x0
24:18 IDAC Current IDAC control value. RO 0b000 0000
17:14 IREF Current IREF control value. RO 0x0
13:8 Q2CAP Current Q2CAP control value. RO 0b00 0000
7:2 Q1CAP Current Q1CAP control value. RO 0b00 0000
1 CTRLATTARGET HFXT control values match target values.

This applies to IREF, Q1CAP, Q2CAP values.		 RO 0
0 AMPGOOD HFXT amplitude good RO 0

TOP:CKMD:ATBCTL0

Address Offset 0x0000 0100
Physical Address 0x4000 1100 Instance 0x4000 1100
Description Analog test bus controls

All fields within this register are locked using the global-lock within SYS0.
Type RW
Bits Field Name Description Type Reset
31:24 RESERVED24 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00
23:0 SEL Testmux selection
ALWAYS write this signal to 0 (OFF), before selecting another configuration!
Not following this might result in device damage.
Value ENUM Name Description
0x0 OFF No signal connected to ATB. All outputs high impedant
0x1 HFXTANA vr_atb_hfxt_ana connected to vr_atb_ckmanatop_ana
0x2 VDDCKM vr_atb_ckmldo_vddckm connected to vr_atb_ckmanatop_ana
0x8 LFXTANA vr_atb_lfxt_ana connected to vr_atb_ckmanatop_ana
0x10 ADCCOMPOUT vr_atb_hfxtadc_compout connected to vr_atb_ckmanatop_ana
0x20 ADCCOMPIN vr_atb_hfxtadc_compin connected to vr_atb_ckmanatop_ana
0x40 ADCDACOUT vr_atb_hfxtadc_dacout connected to vr_atb_ckmanatop_ana
0x80 NABIASITEST vr_atb_nabias_itest_250n_dn connected to vr_atb_ckmanatop_ana
0x100 HFOSCOUT vr_atb_hfosc_out connected to vr_atb_ckmanatop_ana
0x1000 LFMONVTEST vr_atb_lfmonitor_vtest connected to vr_atb_ckmanatop_ana
0x4000 AFOSCOUT vr_atb_afosc connected to vr_atb_ckmanatop_ana
0x10000 HFOSCTESTCLK ull_ckm_hfosc_testclk connected to vr_atb_ckmanatop_clk
0x30000 HFXTTESTCLK ull_ckm_hfxt_testclk connected to vr_atb_ckmanatop_clk
0x50000 LFOSCTESTCLK ull_ckm_lfosc_testclk connected to vr_atb_ckmanatop_clk
0x70000 LFXTTESTCLK ull_ckm_lfxt_testclk connected to vr_atb_ckmanatop_clk
0x90000 AFOSCTESTCLK ull_ckm_afosc_testclk connected to vr_atb_ckmanatop_clk
RW 0x00 0000

TOP:CKMD:ATBCTL1

Address Offset 0x0000 0104
Physical Address 0x4000 1104 Instance 0x4000 1104
Description Analog test bus controls

All fields within this register are locked using the global-lock within SYS0.
Type RW
Bits Field Name Description Type Reset
31:19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000
18 BGAP Control bandgap test output signals RW 0
17:15 AFOSC Control AFOSC test output signals RW 0b000
14:13 LFOSC Control LFOSC test output signals
Value ENUM Name Description
0x0 OFF No output signal selected
0x1 TESTCLK LFOSC test clock
0x2 VDDLOCAL LFOSC VDD LOCAL
0x3 BOTH Both LFOSC test signals (TESTCLK, VDD LOCAL)
RW 0b00
12 NABIAS Enable NABIAS test mode. RW 0
11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
10 LFXT Control LFXT test output signals
Value ENUM Name Description
0x0 OFF No output signal selected
0x1 TESTCLK LFXT test clock
RW 0
9:8 LFMON Control LFMON test output signals
Value ENUM Name Description
0x0 OFF No output signal selected
0x1 TEST1 Test signal 1 / in phase with LF clock
0x2 TEST2 Test signal 2 / in phase with inverted clock signal
RW 0b00
7 HFXT Enable HFXT test mode. RW 0
6:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
2:0 HFOSC Control HFOSC test output signals RW 0b000

TOP:CKMD:DTBCTL

Address Offset 0x0000 0108
Physical Address 0x4000 1108 Instance 0x4000 1108
Description Digital test bus mux control
Type RW
Bits Field Name Description Type Reset
31:23 RESERVED23 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000
22:18 DSEL2 Select data to output on DTB[15:11] RW 0b0 0000
17:13 DSEL1 Select data to output on DTB[10:6] RW 0b0 0000
12:8 DSEL0 Select data to output on DTB[5:1] RW 0b0 0000
7:3 CLKSEL Select clock to output on DTB[0] RW 0b0 0000
2:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
0 EN Enable DTB output RW 0

TOP:CKMD:TRIM0

Address Offset 0x0000 0110
Physical Address 0x4000 1110 Instance 0x4000 1110
Description Production Trim Register 0

Note: This register contains the HFOSC and AFOSC coarse trims.
Changing it might result in frequency overshoots.
To prevent these from reaching the system, the clock is gated off for some periods after writing this register.
Type RW
Bits Field Name Description Type Reset
31:26 RESERVED26 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
25 AFOSC_MODE AFOSC mode trim RW 0
24:21 AFOSC_MID AFOSC mid trim RW 0x0
20:16 AFOSC_COARSE AFOSC coarse trim RW 0b0 0000
15:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
9 HFOSC_MODE HFOSC mode trim
This field is locked using the global-lock within SYS0.		 RW 0
8:5 HFOSC_MID HFOSC mid trim
This field is locked using the global-lock within SYS0.		 RW 0x0
4:0 HFOSC_COARSE HFOSC coarse trim
This field is locked using the global-lock within SYS0.		 RW 0b0 0000

TOP:CKMD:TRIM1

Address Offset 0x0000 0114
Physical Address 0x4000 1114 Instance 0x4000 1114
Description Production Trim Register 1
Type RW
Bits Field Name Description Type Reset
31:30 HFXTSLICER Bias current trim for HFXT slicer. RW 0b00
29:28 PEAKIBIAS IBIAS value for the HFXT peak detector RW 0b00
27 NABIAS_UDIGLDO Decrease uDIGLDO reference current by 25nA RW 0
26:24 LDOBW HFXT LDO bandwidth trim RW 0b000
23:20 LDOFB HFXT LDO feedback trim RW 0x6
19:16 LFDLY LF delay cell trim RW 0xF
15 NABIAS_LFOSC Increase LFOSC reference current by 25nA RW 1
14:8 NABIAS_RES NABIAS resistor trim RW 0b001 0100
7:0 LFOSC_CAP LFOSC cap trim.

Note:-
It's changing resistor inside LFOC, and not capacitor.		 RW 0x39

TOP:CKMD:HFXTINIT

Address Offset 0x0000 0118
Physical Address 0x4000 1118 Instance 0x4000 1118
Description Initial values for HFXT ramping
Type RW
Bits Field Name Description Type Reset
31:30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
29:23 AMPTHR Amplitude threshold during HFXT ramping RW 0b010 1000
22:16 IDAC Initial HFXT IDAC current RW 0b111 1111
15:12 IREF Initial HFXT IREF current RW 0x8
11:6 Q2CAP Initial HFXT Q2 cap trim
Value ENUM Name Description
0x0 CAP0 Nominal 25C = 2.57E-12 F
Stong 25C = 1.50E-12 F
Weak 25C = 2.69E-12 F
0x1 CAP1 Nominal 25C = 2.66E-12 F
Stong 25C = 1.60E-12 F
Weak 25C = 2.79E-12 F
0x2 CAP2 Nominal 25C = 2.76E-12 F
Stong 25C = 1.69E-12 F
Weak 25C = 2.89E-12 F
0x3 CAP3 Nominal 25C = 2.85E-12 F
Stong 25C = 1.79E-12 F
Weak 25C = 2.99E-12 F
0x4 CAP4 Nominal 25C = 2.95E-12 F
Stong 25C = 1.89E-12 F
Weak 25C = 3.09E-12 F
0x5 CAP5 Nominal 25C = 3.04E-12 F
Stong 25C = 1.99E-12 F
Weak 25C = 3.19E-12 F
0x6 CAP6 Nominal 25C = 3.14E-12 F
Stong 25C = 2.09E-12 F
Weak 25C = 3.30E-12 F
0x7 CAP7 Nominal 25C = 3.23E-12 F
Stong 25C = 2.19E-12 F
Weak 25C = 3.40E-12 F
0x8 CAP8 Nominal 25C = 3.33E-12 F
Stong 25C = 2.29E-12 F
Weak 25C = 3.50E-12 F
0x9 CAP9 Nominal 25C = 3.42E-12 F
Stong 25C = 2.39E-12 F
Weak 25C = 3.60E-12 F
0xA CAP10 Nominal 25C = 3.51E-12 F
Stong 25C = 2.49E-12 F
Weak 25C = 3.70E-12 F
0xB CAP11 Nominal 25C = 3.61E-12 F
Stong 25C = 2.59E-12 F
Weak 25C = 3.80E-12 F
0xC CAP12 Nominal 25C = 3.70E-12 F
Stong 25C = 2.69E-12 F
Weak 25C = 3.90E-12 F
0xD CAP13 Nominal 25C = 3.79E-12 F
Stong 25C = 2.79E-12 F
Weak 25C = 4.00E-12 F
0xE CAP14 Nominal 25C = 3.88E-12 F
Stong 25C = 2.89E-12 F
Weak 25C = 4.10E-12 F
0xF CAP15 Nominal 25C = 3.97E-12 F
Stong 25C = 2.98E-12 F
Weak 25C = 4.20E-12 F
0x10 CAP16 Nominal 25C = 3.97E-12 F
Stong 25C = 2.98E-12 F
Weak 25C = 4.20E-12 F
0x11 CAP17 Nominal 25C = 4.09E-12 F
Stong 25C = 3.11E-12 F
Weak 25C = 4.33E-12 F
0x12 CAP18 Nominal 25C = 4.21E-12 F
Stong 25C = 3.23E-12 F
Weak 25C = 4.46E-12 F
0x13 CAP19 Nominal 25C = 4.33E-12 F
Stong 25C = 3.36E-12 F
Weak 25C = 4.59E-12 F
0x14 CAP20 Nominal 25C = 4.45E-12 F
Stong 25C = 3.48E-12 F
Weak 25C = 4.72E-12 F
0x15 CAP21 Nominal 25C = 4.57E-12 F
Stong 25C = 3.60E-12 F
Weak 25C = 4.85E-12 F
0x16 CAP22 Nominal 25C = 4.68E-12 F
Stong 25C = 3.73E-12 F
Weak 25C = 4.98E-12 F
0x17 CAP23 Nominal 25C = 4.80E-12 F
Stong 25C = 3.85E-12 F
Weak 25C = 5.10E-12 F
0x18 CAP24 Nominal 25C = 4.91E-12 F
Stong 25C = 3.97E-12 F
Weak 25C = 5.23E-12 F
0x19 CAP25 Nominal 25C = 5.03E-12 F
Stong 25C = 4.09E-12 F
Weak 25C = 5.36E-12 F
0x1A CAP26 Nominal 25C = 5.15E-12 F
Stong 25C = 4.21E-12 F
Weak 25C = 5.49E-12 F
0x1B CAP27 Nominal 25C = 5.26E-12 F
Stong 25C = 4.32E-12 F
Weak 25C = 5.61E-12 F
0x1C CAP28 Nominal 25C = 5.37E-12 F
Stong 25C = 4.44E-12 F
Weak 25C = 5.74E-12 F
0x1D CAP29 Nominal 25C = 5.49E-12 F
Stong 25C = 4.56E-12 F
Weak 25C = 5.87E-12 F
0x1E CAP30 Nominal 25C = 5.60E-12 F
Stong 25C = 4.67E-12 F
Weak 25C = 5.99E-12 F
0x1F CAP31 Nominal 25C = 5.72E-12 F
Stong 25C = 4.79E-12 F
Weak 25C = 6.12E-12 F
0x20 CAP32 Nominal 25C = 5.97E-12 F
Stong 25C = 5.05E-12 F
Weak 25C = 6.40E-12 F
0x21 CAP33 Nominal 25C = 6.12E-12 F
Stong 25C = 5.20E-12 F
Weak 25C = 6.56E-12 F
0x22 CAP34 Nominal 25C = 6.26E-12 F
Stong 25C = 5.35E-12 F
Weak 25C = 6.72E-12 F
0x23 CAP35 Nominal 25C = 6.41E-12 F
Stong 25C = 5.49E-12 F
Weak 25C = 6.88E-12 F
0x24 CAP36 Nominal 25C = 6.55E-12 F
Stong 25C = 5.63E-12 F
Weak 25C = 7.04E-12 F
0x25 CAP37 Nominal 25C = 6.69E-12 F
Stong 25C = 5.78E-12 F
Weak 25C = 7.20E-12 F
0x26 CAP38 Nominal 25C = 6.84E-12 F
Stong 25C = 5.92E-12 F
Weak 25C = 7.35E-12 F
0x27 CAP39 Nominal 25C = 6.98E-12 F
Stong 25C = 6.06E-12 F
Weak 25C = 7.51E-12 F
0x28 CAP40 Nominal 25C = 7.12E-12 F
Stong 25C = 6.21E-12 F
Weak 25C = 7.67E-12 F
0x29 CAP41 Nominal 25C = 7.26E-12 F
Stong 25C = 6.35E-12 F
Weak 25C = 7.82E-12 F
0x2A CAP42 Nominal 25C = 7.40E-12 F
Stong 25C = 6.49E-12 F
Weak 25C = 7.98E-12 F
0x2B CAP43 Nominal 25C = 7.55E-12 F
Stong 25C = 6.63E-12 F
Weak 25C = 8.13E-12 F
0x2C CAP44 Nominal 25C = 7.69E-12 F
Stong 25C = 6.77E-12 F
Weak 25C = 8.29E-12 F
0x2D CAP45 Nominal 25C = 7.83E-12 F
Stong 25C = 6.91E-12 F
Weak 25C = 8.44E-12 F
0x2E CAP46 Nominal 25C = 7.97E-12 F
Stong 25C = 7.05E-12 F
Weak 25C = 8.60E-12 F
0x2F CAP47 Nominal 25C = 8.10E-12 F
Stong 25C = 7.18E-12 F
Weak 25C = 8.75E-12 F
0x30 CAP48 Nominal 25C = 8.10E-12 F
Stong 25C = 7.18E-12 F
Weak 25C = 8.75E-12 F
0x31 CAP49 Nominal 25C = 8.30E-12 F
Stong 25C = 7.38E-12 F
Weak 25C = 8.96E-12 F
0x32 CAP50 Nominal 25C = 8.49E-12 F
Stong 25C = 7.57E-12 F
Weak 25C = 9.18E-12 F
0x33 CAP51 Nominal 25C = 8.69E-12 F
Stong 25C = 7.76E-12 F
Weak 25C = 9.39E-12 F
0x34 CAP52 Nominal 25C = 8.88E-12 F
Stong 25C = 7.94E-12 F
Weak 25C = 9.60E-12 F
0x35 CAP53 Nominal 25C = 9.07E-12 F
Stong 25C = 8.13E-12 F
Weak 25C = 9.81E-12 F
0x36 CAP54 Nominal 25C = 9.26E-12 F
Stong 25C = 8.32E-12 F
Weak 25C = 1.00E-11 F
0x37 CAP55 Nominal 25C = 9.46E-12 F
Stong 25C = 8.51E-12 F
Weak 25C = 1.02E-11 F
0x38 CAP56 Nominal 25C = 9.65E-12 F
Stong 25C = 8.70E-12 F
Weak 25C = 1.04E-11 F
0x39 CAP57 Nominal 25C = 9.84E-12 F
Stong 25C = 8.89E-12 F
Weak 25C = 1.07E-11 F
0x3A CAP58 Nominal 25C = 1.00E-11 F
Stong 25C = 9.07E-12 F
Weak 25C = 1.09E-11 F
0x3B CAP59 Nominal 25C = 1.02E-11 F
Stong 25C = 9.26E-12 F
Weak 25C = 1.11E-11 F
0x3C CAP60 Nominal 25C = 1.04E-11 F
Stong 25C = 9.45E-12 F
Weak 25C = 1.13E-11 F
0x3D CAP61 Nominal 25C = 1.06E-11 F
Stong 25C = 9.64E-12 F
Weak 25C = 1.15E-11 F
0x3E CAP62 Nominal 25C = 1.08E-11 F
Stong 25C = 9.82E-12 F
Weak 25C = 1.17E-11 F
0x3F CAP63 Nominal 25C = 1.10E-11 F
Stong 25C = 1.00E-11 F
Weak 25C = 1.19E-11 F
RW 0b00 0000
5:0 Q1CAP Initial HFXT Q1 cap trim
Value ENUM Name Description
0x0 CAP0 Nominal 25C = 2.57E-12 F
Stong 25C = 1.50E-12 F
Weak 25C = 2.69E-12 F
0x1 CAP1 Nominal 25C = 2.66E-12 F
Stong 25C = 1.60E-12 F
Weak 25C = 2.79E-12 F
0x2 CAP2 Nominal 25C = 2.76E-12 F
Stong 25C = 1.69E-12 F
Weak 25C = 2.89E-12 F
0x3 CAP3 Nominal 25C = 2.85E-12 F
Stong 25C = 1.79E-12 F
Weak 25C = 2.99E-12 F
0x4 CAP4 Nominal 25C = 2.95E-12 F
Stong 25C = 1.89E-12 F
Weak 25C = 3.09E-12 F
0x5 CAP5 Nominal 25C = 3.04E-12 F
Stong 25C = 1.99E-12 F
Weak 25C = 3.19E-12 F
0x6 CAP6 Nominal 25C = 3.14E-12 F
Stong 25C = 2.09E-12 F
Weak 25C = 3.30E-12 F
0x7 CAP7 Nominal 25C = 3.23E-12 F
Stong 25C = 2.19E-12 F
Weak 25C = 3.40E-12 F
0x8 CAP8 Nominal 25C = 3.33E-12 F
Stong 25C = 2.29E-12 F
Weak 25C = 3.50E-12 F
0x9 CAP9 Nominal 25C = 3.42E-12 F
Stong 25C = 2.39E-12 F
Weak 25C = 3.60E-12 F
0xA CAP10 Nominal 25C = 3.51E-12 F
Stong 25C = 2.49E-12 F
Weak 25C = 3.70E-12 F
0xB CAP11 Nominal 25C = 3.61E-12 F
Stong 25C = 2.59E-12 F
Weak 25C = 3.80E-12 F
0xC CAP12 Nominal 25C = 3.70E-12 F
Stong 25C = 2.69E-12 F
Weak 25C = 3.90E-12 F
0xD CAP13 Nominal 25C = 3.79E-12 F
Stong 25C = 2.79E-12 F
Weak 25C = 4.00E-12 F
0xE CAP14 Nominal 25C = 3.88E-12 F
Stong 25C = 2.89E-12 F
Weak 25C = 4.10E-12 F
0xF CAP15 Nominal 25C = 3.97E-12 F
Stong 25C = 2.98E-12 F
Weak 25C = 4.20E-12 F
0x10 CAP16 Nominal 25C = 3.97E-12 F
Stong 25C = 2.98E-12 F
Weak 25C = 4.20E-12 F
0x11 CAP17 Nominal 25C = 4.09E-12 F
Stong 25C = 3.11E-12 F
Weak 25C = 4.33E-12 F
0x12 CAP18 Nominal 25C = 4.21E-12 F
Stong 25C = 3.23E-12 F
Weak 25C = 4.46E-12 F
0x13 CAP19 Nominal 25C = 4.33E-12 F
Stong 25C = 3.36E-12 F
Weak 25C = 4.59E-12 F
0x14 CAP20 Nominal 25C = 4.45E-12 F
Stong 25C = 3.48E-12 F
Weak 25C = 4.72E-12 F
0x15 CAP21 Nominal 25C = 4.57E-12 F
Stong 25C = 3.60E-12 F
Weak 25C = 4.85E-12 F
0x16 CAP22 Nominal 25C = 4.68E-12 F
Stong 25C = 3.73E-12 F
Weak 25C = 4.98E-12 F
0x17 CAP23 Nominal 25C = 4.80E-12 F
Stong 25C = 3.85E-12 F
Weak 25C = 5.10E-12 F
0x18 CAP24 Nominal 25C = 4.91E-12 F
Stong 25C = 3.97E-12 F
Weak 25C = 5.23E-12 F
0x19 CAP25 Nominal 25C = 5.03E-12 F
Stong 25C = 4.09E-12 F
Weak 25C = 5.36E-12 F
0x1A CAP26 Nominal 25C = 5.15E-12 F
Stong 25C = 4.21E-12 F
Weak 25C = 5.49E-12 F
0x1B CAP27 Nominal 25C = 5.26E-12 F
Stong 25C = 4.32E-12 F
Weak 25C = 5.61E-12 F
0x1C CAP28 Nominal 25C = 5.37E-12 F
Stong 25C = 4.44E-12 F
Weak 25C = 5.74E-12 F
0x1D CAP29 Nominal 25C = 5.49E-12 F
Stong 25C = 4.56E-12 F
Weak 25C = 5.87E-12 F
0x1E CAP30 Nominal 25C = 5.60E-12 F
Stong 25C = 4.67E-12 F
Weak 25C = 5.99E-12 F
0x1F CAP31 Nominal 25C = 5.72E-12 F
Stong 25C = 4.79E-12 F
Weak 25C = 6.12E-12 F
0x20 CAP32 Nominal 25C = 5.97E-12 F
Stong 25C = 5.05E-12 F
Weak 25C = 6.40E-12 F
0x21 CAP33 Nominal 25C = 6.12E-12 F
Stong 25C = 5.20E-12 F
Weak 25C = 6.56E-12 F
0x22 CAP34 Nominal 25C = 6.26E-12 F
Stong 25C = 5.35E-12 F
Weak 25C = 6.72E-12 F
0x23 CAP35 Nominal 25C = 6.41E-12 F
Stong 25C = 5.49E-12 F
Weak 25C = 6.88E-12 F
0x24 CAP36 Nominal 25C = 6.55E-12 F
Stong 25C = 5.63E-12 F
Weak 25C = 7.04E-12 F
0x25 CAP37 Nominal 25C = 6.69E-12 F
Stong 25C = 5.78E-12 F
Weak 25C = 7.20E-12 F
0x26 CAP38 Nominal 25C = 6.84E-12 F
Stong 25C = 5.92E-12 F
Weak 25C = 7.35E-12 F
0x27 CAP39 Nominal 25C = 6.98E-12 F
Stong 25C = 6.06E-12 F
Weak 25C = 7.51E-12 F
0x28 CAP40 Nominal 25C = 7.12E-12 F
Stong 25C = 6.21E-12 F
Weak 25C = 7.67E-12 F
0x29 CAP41 Nominal 25C = 7.26E-12 F
Stong 25C = 6.35E-12 F
Weak 25C = 7.82E-12 F
0x2A CAP42 Nominal 25C = 7.40E-12 F
Stong 25C = 6.49E-12 F
Weak 25C = 7.98E-12 F
0x2B CAP43 Nominal 25C = 7.55E-12 F
Stong 25C = 6.63E-12 F
Weak 25C = 8.13E-12 F
0x2C CAP44 Nominal 25C = 7.69E-12 F
Stong 25C = 6.77E-12 F
Weak 25C = 8.29E-12 F
0x2D CAP45 Nominal 25C = 7.83E-12 F
Stong 25C = 6.91E-12 F
Weak 25C = 8.44E-12 F
0x2E CAP46 Nominal 25C = 7.97E-12 F
Stong 25C = 7.05E-12 F
Weak 25C = 8.60E-12 F
0x2F CAP47 Nominal 25C = 8.10E-12 F
Stong 25C = 7.18E-12 F
Weak 25C = 8.75E-12 F
0x30 CAP48 Nominal 25C = 8.10E-12 F
Stong 25C = 7.18E-12 F
Weak 25C = 8.75E-12 F
0x31 CAP49 Nominal 25C = 8.30E-12 F
Stong 25C = 7.38E-12 F
Weak 25C = 8.96E-12 F
0x32 CAP50 Nominal 25C = 8.49E-12 F
Stong 25C = 7.57E-12 F
Weak 25C = 9.18E-12 F
0x33 CAP51 Nominal 25C = 8.69E-12 F
Stong 25C = 7.76E-12 F
Weak 25C = 9.39E-12 F
0x34 CAP52 Nominal 25C = 8.88E-12 F
Stong 25C = 7.94E-12 F
Weak 25C = 9.60E-12 F
0x35 CAP53 Nominal 25C = 9.07E-12 F
Stong 25C = 8.13E-12 F
Weak 25C = 9.81E-12 F
0x36 CAP54 Nominal 25C = 9.26E-12 F
Stong 25C = 8.32E-12 F
Weak 25C = 1.00E-11 F
0x37 CAP55 Nominal 25C = 9.46E-12 F
Stong 25C = 8.51E-12 F
Weak 25C = 1.02E-11 F
0x38 CAP56 Nominal 25C = 9.65E-12 F
Stong 25C = 8.70E-12 F
Weak 25C = 1.04E-11 F
0x39 CAP57 Nominal 25C = 9.84E-12 F
Stong 25C = 8.89E-12 F
Weak 25C = 1.07E-11 F
0x3A CAP58 Nominal 25C = 1.00E-11 F
Stong 25C = 9.07E-12 F
Weak 25C = 1.09E-11 F
0x3B CAP59 Nominal 25C = 1.02E-11 F
Stong 25C = 9.26E-12 F
Weak 25C = 1.11E-11 F
0x3C CAP60 Nominal 25C = 1.04E-11 F
Stong 25C = 9.45E-12 F
Weak 25C = 1.13E-11 F
0x3D CAP61 Nominal 25C = 1.06E-11 F
Stong 25C = 9.64E-12 F
Weak 25C = 1.15E-11 F
0x3E CAP62 Nominal 25C = 1.08E-11 F
Stong 25C = 9.82E-12 F
Weak 25C = 1.17E-11 F
0x3F CAP63 Nominal 25C = 1.10E-11 F
Stong 25C = 1.00E-11 F
Weak 25C = 1.19E-11 F
RW 0b00 0000

TOP:CKMD:HFXTTARG

Address Offset 0x0000 011C
Physical Address 0x4000 111C Instance 0x4000 111C
Description Target values for HFXT ramping
Type RW
Bits Field Name Description Type Reset
31:30 AMPHYST ADC hysteresis used during IDAC updates.

Every AMPCFG0.INTERVAL, IDAC will be regulated
- up as long as ADC < AMPTHR
- down as long as ADC > AMPTHR+AMPHYST		 RW 0b01
29:23 AMPTHR Minimum HFXT amplitude RW 0b010 1000
22:16 IDAC Minimum IDAC current RW 0b100 0110
15:12 IREF Target HFXT IREF current RW 0x4
11:6 Q2CAP Target HFXT Q2 cap trim
Value ENUM Name Description
0x0 CAP0 Nominal 25C = 2.57E-12 F
Stong 25C = 1.50E-12 F
Weak 25C = 2.69E-12 F
0x1 CAP1 Nominal 25C = 2.66E-12 F
Stong 25C = 1.60E-12 F
Weak 25C = 2.79E-12 F
0x2 CAP2 Nominal 25C = 2.76E-12 F
Stong 25C = 1.69E-12 F
Weak 25C = 2.89E-12 F
0x3 CAP3 Nominal 25C = 2.85E-12 F
Stong 25C = 1.79E-12 F
Weak 25C = 2.99E-12 F
0x4 CAP4 Nominal 25C = 2.95E-12 F
Stong 25C = 1.89E-12 F
Weak 25C = 3.09E-12 F
0x5 CAP5 Nominal 25C = 3.04E-12 F
Stong 25C = 1.99E-12 F
Weak 25C = 3.19E-12 F
0x6 CAP6 Nominal 25C = 3.14E-12 F
Stong 25C = 2.09E-12 F
Weak 25C = 3.30E-12 F
0x7 CAP7 Nominal 25C = 3.23E-12 F
Stong 25C = 2.19E-12 F
Weak 25C = 3.40E-12 F
0x8 CAP8 Nominal 25C = 3.33E-12 F
Stong 25C = 2.29E-12 F
Weak 25C = 3.50E-12 F
0x9 CAP9 Nominal 25C = 3.42E-12 F
Stong 25C = 2.39E-12 F
Weak 25C = 3.60E-12 F
0xA CAP10 Nominal 25C = 3.51E-12 F
Stong 25C = 2.49E-12 F
Weak 25C = 3.70E-12 F
0xB CAP11 Nominal 25C = 3.61E-12 F
Stong 25C = 2.59E-12 F
Weak 25C = 3.80E-12 F
0xC CAP12 Nominal 25C = 3.70E-12 F
Stong 25C = 2.69E-12 F
Weak 25C = 3.90E-12 F
0xD CAP13 Nominal 25C = 3.79E-12 F
Stong 25C = 2.79E-12 F
Weak 25C = 4.00E-12 F
0xE CAP14 Nominal 25C = 3.88E-12 F
Stong 25C = 2.89E-12 F
Weak 25C = 4.10E-12 F
0xF CAP15 Nominal 25C = 3.97E-12 F
Stong 25C = 2.98E-12 F
Weak 25C = 4.20E-12 F
0x10 CAP16 Nominal 25C = 3.97E-12 F
Stong 25C = 2.98E-12 F
Weak 25C = 4.20E-12 F
0x11 CAP17 Nominal 25C = 4.09E-12 F
Stong 25C = 3.11E-12 F
Weak 25C = 4.33E-12 F
0x12 CAP18 Nominal 25C = 4.21E-12 F
Stong 25C = 3.23E-12 F
Weak 25C = 4.46E-12 F
0x13 CAP19 Nominal 25C = 4.33E-12 F
Stong 25C = 3.36E-12 F
Weak 25C = 4.59E-12 F
0x14 CAP20 Nominal 25C = 4.45E-12 F
Stong 25C = 3.48E-12 F
Weak 25C = 4.72E-12 F
0x15 CAP21 Nominal 25C = 4.57E-12 F
Stong 25C = 3.60E-12 F
Weak 25C = 4.85E-12 F
0x16 CAP22 Nominal 25C = 4.68E-12 F
Stong 25C = 3.73E-12 F
Weak 25C = 4.98E-12 F
0x17 CAP23 Nominal 25C = 4.80E-12 F
Stong 25C = 3.85E-12 F
Weak 25C = 5.10E-12 F
0x18 CAP24 Nominal 25C = 4.91E-12 F
Stong 25C = 3.97E-12 F
Weak 25C = 5.23E-12 F
0x19 CAP25 Nominal 25C = 5.03E-12 F
Stong 25C = 4.09E-12 F
Weak 25C = 5.36E-12 F
0x1A CAP26 Nominal 25C = 5.15E-12 F
Stong 25C = 4.21E-12 F
Weak 25C = 5.49E-12 F
0x1B CAP27 Nominal 25C = 5.26E-12 F
Stong 25C = 4.32E-12 F
Weak 25C = 5.61E-12 F
0x1C CAP28 Nominal 25C = 5.37E-12 F
Stong 25C = 4.44E-12 F
Weak 25C = 5.74E-12 F
0x1D CAP29 Nominal 25C = 5.49E-12 F
Stong 25C = 4.56E-12 F
Weak 25C = 5.87E-12 F
0x1E CAP30 Nominal 25C = 5.60E-12 F
Stong 25C = 4.67E-12 F
Weak 25C = 5.99E-12 F
0x1F CAP31 Nominal 25C = 5.72E-12 F
Stong 25C = 4.79E-12 F
Weak 25C = 6.12E-12 F
0x20 CAP32 Nominal 25C = 5.97E-12 F
Stong 25C = 5.05E-12 F
Weak 25C = 6.40E-12 F
0x21 CAP33 Nominal 25C = 6.12E-12 F
Stong 25C = 5.20E-12 F
Weak 25C = 6.56E-12 F
0x22 CAP34 Nominal 25C = 6.26E-12 F
Stong 25C = 5.35E-12 F
Weak 25C = 6.72E-12 F
0x23 CAP35 Nominal 25C = 6.41E-12 F
Stong 25C = 5.49E-12 F
Weak 25C = 6.88E-12 F
0x24 CAP36 Nominal 25C = 6.55E-12 F
Stong 25C = 5.63E-12 F
Weak 25C = 7.04E-12 F
0x25 CAP37 Nominal 25C = 6.69E-12 F
Stong 25C = 5.78E-12 F
Weak 25C = 7.20E-12 F
0x26 CAP38 Nominal 25C = 6.84E-12 F
Stong 25C = 5.92E-12 F
Weak 25C = 7.35E-12 F
0x27 CAP39 Nominal 25C = 6.98E-12 F
Stong 25C = 6.06E-12 F
Weak 25C = 7.51E-12 F
0x28 CAP40 Nominal 25C = 7.12E-12 F
Stong 25C = 6.21E-12 F
Weak 25C = 7.67E-12 F
0x29 CAP41 Nominal 25C = 7.26E-12 F
Stong 25C = 6.35E-12 F
Weak 25C = 7.82E-12 F
0x2A CAP42 Nominal 25C = 7.40E-12 F
Stong 25C = 6.49E-12 F
Weak 25C = 7.98E-12 F
0x2B CAP43 Nominal 25C = 7.55E-12 F
Stong 25C = 6.63E-12 F
Weak 25C = 8.13E-12 F
0x2C CAP44 Nominal 25C = 7.69E-12 F
Stong 25C = 6.77E-12 F
Weak 25C = 8.29E-12 F
0x2D CAP45 Nominal 25C = 7.83E-12 F
Stong 25C = 6.91E-12 F
Weak 25C = 8.44E-12 F
0x2E CAP46 Nominal 25C = 7.97E-12 F
Stong 25C = 7.05E-12 F
Weak 25C = 8.60E-12 F
0x2F CAP47 Nominal 25C = 8.10E-12 F
Stong 25C = 7.18E-12 F
Weak 25C = 8.75E-12 F
0x30 CAP48 Nominal 25C = 8.10E-12 F
Stong 25C = 7.18E-12 F
Weak 25C = 8.75E-12 F
0x31 CAP49 Nominal 25C = 8.30E-12 F
Stong 25C = 7.38E-12 F
Weak 25C = 8.96E-12 F
0x32 CAP50 Nominal 25C = 8.49E-12 F
Stong 25C = 7.57E-12 F
Weak 25C = 9.18E-12 F
0x33 CAP51 Nominal 25C = 8.69E-12 F
Stong 25C = 7.76E-12 F
Weak 25C = 9.39E-12 F
0x34 CAP52 Nominal 25C = 8.88E-12 F
Stong 25C = 7.94E-12 F
Weak 25C = 9.60E-12 F
0x35 CAP53 Nominal 25C = 9.07E-12 F
Stong 25C = 8.13E-12 F
Weak 25C = 9.81E-12 F
0x36 CAP54 Nominal 25C = 9.26E-12 F
Stong 25C = 8.32E-12 F
Weak 25C = 1.00E-11 F
0x37 CAP55 Nominal 25C = 9.46E-12 F
Stong 25C = 8.51E-12 F
Weak 25C = 1.02E-11 F
0x38 CAP56 Nominal 25C = 9.65E-12 F
Stong 25C = 8.70E-12 F
Weak 25C = 1.04E-11 F
0x39 CAP57 Nominal 25C = 9.84E-12 F
Stong 25C = 8.89E-12 F
Weak 25C = 1.07E-11 F
0x3A CAP58 Nominal 25C = 1.00E-11 F
Stong 25C = 9.07E-12 F
Weak 25C = 1.09E-11 F
0x3B CAP59 Nominal 25C = 1.02E-11 F
Stong 25C = 9.26E-12 F
Weak 25C = 1.11E-11 F
0x3C CAP60 Nominal 25C = 1.04E-11 F
Stong 25C = 9.45E-12 F
Weak 25C = 1.13E-11 F
0x3D CAP61 Nominal 25C = 1.06E-11 F
Stong 25C = 9.64E-12 F
Weak 25C = 1.15E-11 F
0x3E CAP62 Nominal 25C = 1.08E-11 F
Stong 25C = 9.82E-12 F
Weak 25C = 1.17E-11 F
0x3F CAP63 Nominal 25C = 1.10E-11 F
Stong 25C = 1.00E-11 F
Weak 25C = 1.19E-11 F
RW 0b10 1101
5:0 Q1CAP Target HFXT Q1 cap trim
Value ENUM Name Description
0x0 CAP0 Nominal 25C = 2.57E-12 F
Stong 25C = 1.50E-12 F
Weak 25C = 2.69E-12 F
0x1 CAP1 Nominal 25C = 2.66E-12 F
Stong 25C = 1.60E-12 F
Weak 25C = 2.79E-12 F
0x2 CAP2 Nominal 25C = 2.76E-12 F
Stong 25C = 1.69E-12 F
Weak 25C = 2.89E-12 F
0x3 CAP3 Nominal 25C = 2.85E-12 F
Stong 25C = 1.79E-12 F
Weak 25C = 2.99E-12 F
0x4 CAP4 Nominal 25C = 2.95E-12 F
Stong 25C = 1.89E-12 F
Weak 25C = 3.09E-12 F
0x5 CAP5 Nominal 25C = 3.04E-12 F
Stong 25C = 1.99E-12 F
Weak 25C = 3.19E-12 F
0x6 CAP6 Nominal 25C = 3.14E-12 F
Stong 25C = 2.09E-12 F
Weak 25C = 3.30E-12 F
0x7 CAP7 Nominal 25C = 3.23E-12 F
Stong 25C = 2.19E-12 F
Weak 25C = 3.40E-12 F
0x8 CAP8 Nominal 25C = 3.33E-12 F
Stong 25C = 2.29E-12 F
Weak 25C = 3.50E-12 F
0x9 CAP9 Nominal 25C = 3.42E-12 F
Stong 25C = 2.39E-12 F
Weak 25C = 3.60E-12 F
0xA CAP10 Nominal 25C = 3.51E-12 F
Stong 25C = 2.49E-12 F
Weak 25C = 3.70E-12 F
0xB CAP11 Nominal 25C = 3.61E-12 F
Stong 25C = 2.59E-12 F
Weak 25C = 3.80E-12 F
0xC CAP12 Nominal 25C = 3.70E-12 F
Stong 25C = 2.69E-12 F
Weak 25C = 3.90E-12 F
0xD CAP13 Nominal 25C = 3.79E-12 F
Stong 25C = 2.79E-12 F
Weak 25C = 4.00E-12 F
0xE CAP14 Nominal 25C = 3.88E-12 F
Stong 25C = 2.89E-12 F
Weak 25C = 4.10E-12 F
0xF CAP15 Nominal 25C = 3.97E-12 F
Stong 25C = 2.98E-12 F
Weak 25C = 4.20E-12 F
0x10 CAP16 Nominal 25C = 3.97E-12 F
Stong 25C = 2.98E-12 F
Weak 25C = 4.20E-12 F
0x11 CAP17 Nominal 25C = 4.09E-12 F
Stong 25C = 3.11E-12 F
Weak 25C = 4.33E-12 F
0x12 CAP18 Nominal 25C = 4.21E-12 F
Stong 25C = 3.23E-12 F
Weak 25C = 4.46E-12 F
0x13 CAP19 Nominal 25C = 4.33E-12 F
Stong 25C = 3.36E-12 F
Weak 25C = 4.59E-12 F
0x14 CAP20 Nominal 25C = 4.45E-12 F
Stong 25C = 3.48E-12 F
Weak 25C = 4.72E-12 F
0x15 CAP21 Nominal 25C = 4.57E-12 F
Stong 25C = 3.60E-12 F
Weak 25C = 4.85E-12 F
0x16 CAP22 Nominal 25C = 4.68E-12 F
Stong 25C = 3.73E-12 F
Weak 25C = 4.98E-12 F
0x17 CAP23 Nominal 25C = 4.80E-12 F
Stong 25C = 3.85E-12 F
Weak 25C = 5.10E-12 F
0x18 CAP24 Nominal 25C = 4.91E-12 F
Stong 25C = 3.97E-12 F
Weak 25C = 5.23E-12 F
0x19 CAP25 Nominal 25C = 5.03E-12 F
Stong 25C = 4.09E-12 F
Weak 25C = 5.36E-12 F
0x1A CAP26 Nominal 25C = 5.15E-12 F
Stong 25C = 4.21E-12 F
Weak 25C = 5.49E-12 F
0x1B CAP27 Nominal 25C = 5.26E-12 F
Stong 25C = 4.32E-12 F
Weak 25C = 5.61E-12 F
0x1C CAP28 Nominal 25C = 5.37E-12 F
Stong 25C = 4.44E-12 F
Weak 25C = 5.74E-12 F
0x1D CAP29 Nominal 25C = 5.49E-12 F
Stong 25C = 4.56E-12 F
Weak 25C = 5.87E-12 F
0x1E CAP30 Nominal 25C = 5.60E-12 F
Stong 25C = 4.67E-12 F
Weak 25C = 5.99E-12 F
0x1F CAP31 Nominal 25C = 5.72E-12 F
Stong 25C = 4.79E-12 F
Weak 25C = 6.12E-12 F
0x20 CAP32 Nominal 25C = 5.97E-12 F
Stong 25C = 5.05E-12 F
Weak 25C = 6.40E-12 F
0x21 CAP33 Nominal 25C = 6.12E-12 F
Stong 25C = 5.20E-12 F
Weak 25C = 6.56E-12 F
0x22 CAP34 Nominal 25C = 6.26E-12 F
Stong 25C = 5.35E-12 F
Weak 25C = 6.72E-12 F
0x23 CAP35 Nominal 25C = 6.41E-12 F
Stong 25C = 5.49E-12 F
Weak 25C = 6.88E-12 F
0x24 CAP36 Nominal 25C = 6.55E-12 F
Stong 25C = 5.63E-12 F
Weak 25C = 7.04E-12 F
0x25 CAP37 Nominal 25C = 6.69E-12 F
Stong 25C = 5.78E-12 F
Weak 25C = 7.20E-12 F
0x26 CAP38 Nominal 25C = 6.84E-12 F
Stong 25C = 5.92E-12 F
Weak 25C = 7.35E-12 F
0x27 CAP39 Nominal 25C = 6.98E-12 F
Stong 25C = 6.06E-12 F
Weak 25C = 7.51E-12 F
0x28 CAP40 Nominal 25C = 7.12E-12 F
Stong 25C = 6.21E-12 F
Weak 25C = 7.67E-12 F
0x29 CAP41 Nominal 25C = 7.26E-12 F
Stong 25C = 6.35E-12 F
Weak 25C = 7.82E-12 F
0x2A CAP42 Nominal 25C = 7.40E-12 F
Stong 25C = 6.49E-12 F
Weak 25C = 7.98E-12 F
0x2B CAP43 Nominal 25C = 7.55E-12 F
Stong 25C = 6.63E-12 F
Weak 25C = 8.13E-12 F
0x2C CAP44 Nominal 25C = 7.69E-12 F
Stong 25C = 6.77E-12 F
Weak 25C = 8.29E-12 F
0x2D CAP45 Nominal 25C = 7.83E-12 F
Stong 25C = 6.91E-12 F
Weak 25C = 8.44E-12 F
0x2E CAP46 Nominal 25C = 7.97E-12 F
Stong 25C = 7.05E-12 F
Weak 25C = 8.60E-12 F
0x2F CAP47 Nominal 25C = 8.10E-12 F
Stong 25C = 7.18E-12 F
Weak 25C = 8.75E-12 F
0x30 CAP48 Nominal 25C = 8.10E-12 F
Stong 25C = 7.18E-12 F
Weak 25C = 8.75E-12 F
0x31 CAP49 Nominal 25C = 8.30E-12 F
Stong 25C = 7.38E-12 F
Weak 25C = 8.96E-12 F
0x32 CAP50 Nominal 25C = 8.49E-12 F
Stong 25C = 7.57E-12 F
Weak 25C = 9.18E-12 F
0x33 CAP51 Nominal 25C = 8.69E-12 F
Stong 25C = 7.76E-12 F
Weak 25C = 9.39E-12 F
0x34 CAP52 Nominal 25C = 8.88E-12 F
Stong 25C = 7.94E-12 F
Weak 25C = 9.60E-12 F
0x35 CAP53 Nominal 25C = 9.07E-12 F
Stong 25C = 8.13E-12 F
Weak 25C = 9.81E-12 F
0x36 CAP54 Nominal 25C = 9.26E-12 F
Stong 25C = 8.32E-12 F
Weak 25C = 1.00E-11 F
0x37 CAP55 Nominal 25C = 9.46E-12 F
Stong 25C = 8.51E-12 F
Weak 25C = 1.02E-11 F
0x38 CAP56 Nominal 25C = 9.65E-12 F
Stong 25C = 8.70E-12 F
Weak 25C = 1.04E-11 F
0x39 CAP57 Nominal 25C = 9.84E-12 F
Stong 25C = 8.89E-12 F
Weak 25C = 1.07E-11 F
0x3A CAP58 Nominal 25C = 1.00E-11 F
Stong 25C = 9.07E-12 F
Weak 25C = 1.09E-11 F
0x3B CAP59 Nominal 25C = 1.02E-11 F
Stong 25C = 9.26E-12 F
Weak 25C = 1.11E-11 F
0x3C CAP60 Nominal 25C = 1.04E-11 F
Stong 25C = 9.45E-12 F
Weak 25C = 1.13E-11 F
0x3D CAP61 Nominal 25C = 1.06E-11 F
Stong 25C = 9.64E-12 F
Weak 25C = 1.15E-11 F
0x3E CAP62 Nominal 25C = 1.08E-11 F
Stong 25C = 9.82E-12 F
Weak 25C = 1.17E-11 F
0x3F CAP63 Nominal 25C = 1.10E-11 F
Stong 25C = 1.00E-11 F
Weak 25C = 1.19E-11 F
RW 0b10 1101

TOP:CKMD:HFXTDYN

Address Offset 0x0000 0120
Physical Address 0x4000 1120 Instance 0x4000 1120
Description Alternative target values for HFXT configuration

Software can change these values to dynamically transition the HFXT configuration while HFXT is running.
Set SEL to select the alternative set of target values.
Type RW
Bits Field Name Description Type Reset
31 SEL Select the dynamic configuration.

Amplitude ramping will always happen using the values in HFXTINIT0, HFXTINIT1, HFXTTARG0 and HFXTTARG1.
Afterwards, this bit can be used to select between HFXTTARG0/HFXTTARG1 and HFXTDYN0/HFXTDYN1.
Hardware will ensure a smooth transition of analog control signals.
Value ENUM Name Description
0x0 TARGET Select configuration in CKM.HFXTTARG0 and CKM.HFXTTARG1.
0x1 DYNAMIC Select configuration in CKM.HFXTDYN0 and CKM.HFXTDYN1.
RW 0
30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
29:23 AMPTHR Minimum HFXT amplitude RW 0b010 1000
22:16 IDAC Minimum IDAC current RW 0b100 0110
15:12 IREF Target HFXT IREF current RW 0x4
11:6 Q2CAP Target HFXT Q2 cap trim
Value ENUM Name Description
0x0 CAP0 Nominal 25C = 2.57E-12 F
Stong 25C = 1.50E-12 F
Weak 25C = 2.69E-12 F
0x1 CAP1 Nominal 25C = 2.66E-12 F
Stong 25C = 1.60E-12 F
Weak 25C = 2.79E-12 F
0x2 CAP2 Nominal 25C = 2.76E-12 F
Stong 25C = 1.69E-12 F
Weak 25C = 2.89E-12 F
0x3 CAP3 Nominal 25C = 2.85E-12 F
Stong 25C = 1.79E-12 F
Weak 25C = 2.99E-12 F
0x4 CAP4 Nominal 25C = 2.95E-12 F
Stong 25C = 1.89E-12 F
Weak 25C = 3.09E-12 F
0x5 CAP5 Nominal 25C = 3.04E-12 F
Stong 25C = 1.99E-12 F
Weak 25C = 3.19E-12 F
0x6 CAP6 Nominal 25C = 3.14E-12 F
Stong 25C = 2.09E-12 F
Weak 25C = 3.30E-12 F
0x7 CAP7 Nominal 25C = 3.23E-12 F
Stong 25C = 2.19E-12 F
Weak 25C = 3.40E-12 F
0x8 CAP8 Nominal 25C = 3.33E-12 F
Stong 25C = 2.29E-12 F
Weak 25C = 3.50E-12 F
0x9 CAP9 Nominal 25C = 3.42E-12 F
Stong 25C = 2.39E-12 F
Weak 25C = 3.60E-12 F
0xA CAP10 Nominal 25C = 3.51E-12 F
Stong 25C = 2.49E-12 F
Weak 25C = 3.70E-12 F
0xB CAP11 Nominal 25C = 3.61E-12 F
Stong 25C = 2.59E-12 F
Weak 25C = 3.80E-12 F
0xC CAP12 Nominal 25C = 3.70E-12 F
Stong 25C = 2.69E-12 F
Weak 25C = 3.90E-12 F
0xD CAP13 Nominal 25C = 3.79E-12 F
Stong 25C = 2.79E-12 F
Weak 25C = 4.00E-12 F
0xE CAP14 Nominal 25C = 3.88E-12 F
Stong 25C = 2.89E-12 F
Weak 25C = 4.10E-12 F
0xF CAP15 Nominal 25C = 3.97E-12 F
Stong 25C = 2.98E-12 F
Weak 25C = 4.20E-12 F
0x10 CAP16 Nominal 25C = 3.97E-12 F
Stong 25C = 2.98E-12 F
Weak 25C = 4.20E-12 F
0x11 CAP17 Nominal 25C = 4.09E-12 F
Stong 25C = 3.11E-12 F
Weak 25C = 4.33E-12 F
0x12 CAP18 Nominal 25C = 4.21E-12 F
Stong 25C = 3.23E-12 F
Weak 25C = 4.46E-12 F
0x13 CAP19 Nominal 25C = 4.33E-12 F
Stong 25C = 3.36E-12 F
Weak 25C = 4.59E-12 F
0x14 CAP20 Nominal 25C = 4.45E-12 F
Stong 25C = 3.48E-12 F
Weak 25C = 4.72E-12 F
0x15 CAP21 Nominal 25C = 4.57E-12 F
Stong 25C = 3.60E-12 F
Weak 25C = 4.85E-12 F
0x16 CAP22 Nominal 25C = 4.68E-12 F
Stong 25C = 3.73E-12 F
Weak 25C = 4.98E-12 F
0x17 CAP23 Nominal 25C = 4.80E-12 F
Stong 25C = 3.85E-12 F
Weak 25C = 5.10E-12 F
0x18 CAP24 Nominal 25C = 4.91E-12 F
Stong 25C = 3.97E-12 F
Weak 25C = 5.23E-12 F
0x19 CAP25 Nominal 25C = 5.03E-12 F
Stong 25C = 4.09E-12 F
Weak 25C = 5.36E-12 F
0x1A CAP26 Nominal 25C = 5.15E-12 F
Stong 25C = 4.21E-12 F
Weak 25C = 5.49E-12 F
0x1B CAP27 Nominal 25C = 5.26E-12 F
Stong 25C = 4.32E-12 F
Weak 25C = 5.61E-12 F
0x1C CAP28 Nominal 25C = 5.37E-12 F
Stong 25C = 4.44E-12 F
Weak 25C = 5.74E-12 F
0x1D CAP29 Nominal 25C = 5.49E-12 F
Stong 25C = 4.56E-12 F
Weak 25C = 5.87E-12 F
0x1E CAP30 Nominal 25C = 5.60E-12 F
Stong 25C = 4.67E-12 F
Weak 25C = 5.99E-12 F
0x1F CAP31 Nominal 25C = 5.72E-12 F
Stong 25C = 4.79E-12 F
Weak 25C = 6.12E-12 F
0x20 CAP32 Nominal 25C = 5.97E-12 F
Stong 25C = 5.05E-12 F
Weak 25C = 6.40E-12 F
0x21 CAP33 Nominal 25C = 6.12E-12 F
Stong 25C = 5.20E-12 F
Weak 25C = 6.56E-12 F
0x22 CAP34 Nominal 25C = 6.26E-12 F
Stong 25C = 5.35E-12 F
Weak 25C = 6.72E-12 F
0x23 CAP35 Nominal 25C = 6.41E-12 F
Stong 25C = 5.49E-12 F
Weak 25C = 6.88E-12 F
0x24 CAP36 Nominal 25C = 6.55E-12 F
Stong 25C = 5.63E-12 F
Weak 25C = 7.04E-12 F
0x25 CAP37 Nominal 25C = 6.69E-12 F
Stong 25C = 5.78E-12 F
Weak 25C = 7.20E-12 F
0x26 CAP38 Nominal 25C = 6.84E-12 F
Stong 25C = 5.92E-12 F
Weak 25C = 7.35E-12 F
0x27 CAP39 Nominal 25C = 6.98E-12 F
Stong 25C = 6.06E-12 F
Weak 25C = 7.51E-12 F
0x28 CAP40 Nominal 25C = 7.12E-12 F
Stong 25C = 6.21E-12 F
Weak 25C = 7.67E-12 F
0x29 CAP41 Nominal 25C = 7.26E-12 F
Stong 25C = 6.35E-12 F
Weak 25C = 7.82E-12 F
0x2A CAP42 Nominal 25C = 7.40E-12 F
Stong 25C = 6.49E-12 F
Weak 25C = 7.98E-12 F
0x2B CAP43 Nominal 25C = 7.55E-12 F
Stong 25C = 6.63E-12 F
Weak 25C = 8.13E-12 F
0x2C CAP44 Nominal 25C = 7.69E-12 F
Stong 25C = 6.77E-12 F
Weak 25C = 8.29E-12 F
0x2D CAP45 Nominal 25C = 7.83E-12 F
Stong 25C = 6.91E-12 F
Weak 25C = 8.44E-12 F
0x2E CAP46 Nominal 25C = 7.97E-12 F
Stong 25C = 7.05E-12 F
Weak 25C = 8.60E-12 F
0x2F CAP47 Nominal 25C = 8.10E-12 F
Stong 25C = 7.18E-12 F
Weak 25C = 8.75E-12 F
0x30 CAP48 Nominal 25C = 8.10E-12 F
Stong 25C = 7.18E-12 F
Weak 25C = 8.75E-12 F
0x31 CAP49 Nominal 25C = 8.30E-12 F
Stong 25C = 7.38E-12 F
Weak 25C = 8.96E-12 F
0x32 CAP50 Nominal 25C = 8.49E-12 F
Stong 25C = 7.57E-12 F
Weak 25C = 9.18E-12 F
0x33 CAP51 Nominal 25C = 8.69E-12 F
Stong 25C = 7.76E-12 F
Weak 25C = 9.39E-12 F
0x34 CAP52 Nominal 25C = 8.88E-12 F
Stong 25C = 7.94E-12 F
Weak 25C = 9.60E-12 F
0x35 CAP53 Nominal 25C = 9.07E-12 F
Stong 25C = 8.13E-12 F
Weak 25C = 9.81E-12 F
0x36 CAP54 Nominal 25C = 9.26E-12 F
Stong 25C = 8.32E-12 F
Weak 25C = 1.00E-11 F
0x37 CAP55 Nominal 25C = 9.46E-12 F
Stong 25C = 8.51E-12 F
Weak 25C = 1.02E-11 F
0x38 CAP56 Nominal 25C = 9.65E-12 F
Stong 25C = 8.70E-12 F
Weak 25C = 1.04E-11 F
0x39 CAP57 Nominal 25C = 9.84E-12 F
Stong 25C = 8.89E-12 F
Weak 25C = 1.07E-11 F
0x3A CAP58 Nominal 25C = 1.00E-11 F
Stong 25C = 9.07E-12 F
Weak 25C = 1.09E-11 F
0x3B CAP59 Nominal 25C = 1.02E-11 F
Stong 25C = 9.26E-12 F
Weak 25C = 1.11E-11 F
0x3C CAP60 Nominal 25C = 1.04E-11 F
Stong 25C = 9.45E-12 F
Weak 25C = 1.13E-11 F
0x3D CAP61 Nominal 25C = 1.06E-11 F
Stong 25C = 9.64E-12 F
Weak 25C = 1.15E-11 F
0x3E CAP62 Nominal 25C = 1.08E-11 F
Stong 25C = 9.82E-12 F
Weak 25C = 1.17E-11 F
0x3F CAP63 Nominal 25C = 1.10E-11 F
Stong 25C = 1.00E-11 F
Weak 25C = 1.19E-11 F
RW 0b10 1101
5:0 Q1CAP Target HFXT Q1 cap trim
Value ENUM Name Description
0x0 CAP0 Nominal 25C = 2.57E-12 F
Stong 25C = 1.50E-12 F
Weak 25C = 2.69E-12 F
0x1 CAP1 Nominal 25C = 2.66E-12 F
Stong 25C = 1.60E-12 F
Weak 25C = 2.79E-12 F
0x2 CAP2 Nominal 25C = 2.76E-12 F
Stong 25C = 1.69E-12 F
Weak 25C = 2.89E-12 F
0x3 CAP3 Nominal 25C = 2.85E-12 F
Stong 25C = 1.79E-12 F
Weak 25C = 2.99E-12 F
0x4 CAP4 Nominal 25C = 2.95E-12 F
Stong 25C = 1.89E-12 F
Weak 25C = 3.09E-12 F
0x5 CAP5 Nominal 25C = 3.04E-12 F
Stong 25C = 1.99E-12 F
Weak 25C = 3.19E-12 F
0x6 CAP6 Nominal 25C = 3.14E-12 F
Stong 25C = 2.09E-12 F
Weak 25C = 3.30E-12 F
0x7 CAP7 Nominal 25C = 3.23E-12 F
Stong 25C = 2.19E-12 F
Weak 25C = 3.40E-12 F
0x8 CAP8 Nominal 25C = 3.33E-12 F
Stong 25C = 2.29E-12 F
Weak 25C = 3.50E-12 F
0x9 CAP9 Nominal 25C = 3.42E-12 F
Stong 25C = 2.39E-12 F
Weak 25C = 3.60E-12 F
0xA CAP10 Nominal 25C = 3.51E-12 F
Stong 25C = 2.49E-12 F
Weak 25C = 3.70E-12 F
0xB CAP11 Nominal 25C = 3.61E-12 F
Stong 25C = 2.59E-12 F
Weak 25C = 3.80E-12 F
0xC CAP12 Nominal 25C = 3.70E-12 F
Stong 25C = 2.69E-12 F
Weak 25C = 3.90E-12 F
0xD CAP13 Nominal 25C = 3.79E-12 F
Stong 25C = 2.79E-12 F
Weak 25C = 4.00E-12 F
0xE CAP14 Nominal 25C = 3.88E-12 F
Stong 25C = 2.89E-12 F
Weak 25C = 4.10E-12 F
0xF CAP15 Nominal 25C = 3.97E-12 F
Stong 25C = 2.98E-12 F
Weak 25C = 4.20E-12 F
0x10 CAP16 Nominal 25C = 3.97E-12 F
Stong 25C = 2.98E-12 F
Weak 25C = 4.20E-12 F
0x11 CAP17 Nominal 25C = 4.09E-12 F
Stong 25C = 3.11E-12 F
Weak 25C = 4.33E-12 F
0x12 CAP18 Nominal 25C = 4.21E-12 F
Stong 25C = 3.23E-12 F
Weak 25C = 4.46E-12 F
0x13 CAP19 Nominal 25C = 4.33E-12 F
Stong 25C = 3.36E-12 F
Weak 25C = 4.59E-12 F
0x14 CAP20 Nominal 25C = 4.45E-12 F
Stong 25C = 3.48E-12 F
Weak 25C = 4.72E-12 F
0x15 CAP21 Nominal 25C = 4.57E-12 F
Stong 25C = 3.60E-12 F
Weak 25C = 4.85E-12 F
0x16 CAP22 Nominal 25C = 4.68E-12 F
Stong 25C = 3.73E-12 F
Weak 25C = 4.98E-12 F
0x17 CAP23 Nominal 25C = 4.80E-12 F
Stong 25C = 3.85E-12 F
Weak 25C = 5.10E-12 F
0x18 CAP24 Nominal 25C = 4.91E-12 F
Stong 25C = 3.97E-12 F
Weak 25C = 5.23E-12 F
0x19 CAP25 Nominal 25C = 5.03E-12 F
Stong 25C = 4.09E-12 F
Weak 25C = 5.36E-12 F
0x1A CAP26 Nominal 25C = 5.15E-12 F
Stong 25C = 4.21E-12 F
Weak 25C = 5.49E-12 F
0x1B CAP27 Nominal 25C = 5.26E-12 F
Stong 25C = 4.32E-12 F
Weak 25C = 5.61E-12 F
0x1C CAP28 Nominal 25C = 5.37E-12 F
Stong 25C = 4.44E-12 F
Weak 25C = 5.74E-12 F
0x1D CAP29 Nominal 25C = 5.49E-12 F
Stong 25C = 4.56E-12 F
Weak 25C = 5.87E-12 F
0x1E CAP30 Nominal 25C = 5.60E-12 F
Stong 25C = 4.67E-12 F
Weak 25C = 5.99E-12 F
0x1F CAP31 Nominal 25C = 5.72E-12 F
Stong 25C = 4.79E-12 F
Weak 25C = 6.12E-12 F
0x20 CAP32 Nominal 25C = 5.97E-12 F
Stong 25C = 5.05E-12 F
Weak 25C = 6.40E-12 F
0x21 CAP33 Nominal 25C = 6.12E-12 F
Stong 25C = 5.20E-12 F
Weak 25C = 6.56E-12 F
0x22 CAP34 Nominal 25C = 6.26E-12 F
Stong 25C = 5.35E-12 F
Weak 25C = 6.72E-12 F
0x23 CAP35 Nominal 25C = 6.41E-12 F
Stong 25C = 5.49E-12 F
Weak 25C = 6.88E-12 F
0x24 CAP36 Nominal 25C = 6.55E-12 F
Stong 25C = 5.63E-12 F
Weak 25C = 7.04E-12 F
0x25 CAP37 Nominal 25C = 6.69E-12 F
Stong 25C = 5.78E-12 F
Weak 25C = 7.20E-12 F
0x26 CAP38 Nominal 25C = 6.84E-12 F
Stong 25C = 5.92E-12 F
Weak 25C = 7.35E-12 F
0x27 CAP39 Nominal 25C = 6.98E-12 F
Stong 25C = 6.06E-12 F
Weak 25C = 7.51E-12 F
0x28 CAP40 Nominal 25C = 7.12E-12 F
Stong 25C = 6.21E-12 F
Weak 25C = 7.67E-12 F
0x29 CAP41 Nominal 25C = 7.26E-12 F
Stong 25C = 6.35E-12 F
Weak 25C = 7.82E-12 F
0x2A CAP42 Nominal 25C = 7.40E-12 F
Stong 25C = 6.49E-12 F
Weak 25C = 7.98E-12 F
0x2B CAP43 Nominal 25C = 7.55E-12 F
Stong 25C = 6.63E-12 F
Weak 25C = 8.13E-12 F
0x2C CAP44 Nominal 25C = 7.69E-12 F
Stong 25C = 6.77E-12 F
Weak 25C = 8.29E-12 F
0x2D CAP45 Nominal 25C = 7.83E-12 F
Stong 25C = 6.91E-12 F
Weak 25C = 8.44E-12 F
0x2E CAP46 Nominal 25C = 7.97E-12 F
Stong 25C = 7.05E-12 F
Weak 25C = 8.60E-12 F
0x2F CAP47 Nominal 25C = 8.10E-12 F
Stong 25C = 7.18E-12 F
Weak 25C = 8.75E-12 F
0x30 CAP48 Nominal 25C = 8.10E-12 F
Stong 25C = 7.18E-12 F
Weak 25C = 8.75E-12 F
0x31 CAP49 Nominal 25C = 8.30E-12 F
Stong 25C = 7.38E-12 F
Weak 25C = 8.96E-12 F
0x32 CAP50 Nominal 25C = 8.49E-12 F
Stong 25C = 7.57E-12 F
Weak 25C = 9.18E-12 F
0x33 CAP51 Nominal 25C = 8.69E-12 F
Stong 25C = 7.76E-12 F
Weak 25C = 9.39E-12 F
0x34 CAP52 Nominal 25C = 8.88E-12 F
Stong 25C = 7.94E-12 F
Weak 25C = 9.60E-12 F
0x35 CAP53 Nominal 25C = 9.07E-12 F
Stong 25C = 8.13E-12 F
Weak 25C = 9.81E-12 F
0x36 CAP54 Nominal 25C = 9.26E-12 F
Stong 25C = 8.32E-12 F
Weak 25C = 1.00E-11 F
0x37 CAP55 Nominal 25C = 9.46E-12 F
Stong 25C = 8.51E-12 F
Weak 25C = 1.02E-11 F
0x38 CAP56 Nominal 25C = 9.65E-12 F
Stong 25C = 8.70E-12 F
Weak 25C = 1.04E-11 F
0x39 CAP57 Nominal 25C = 9.84E-12 F
Stong 25C = 8.89E-12 F
Weak 25C = 1.07E-11 F
0x3A CAP58 Nominal 25C = 1.00E-11 F
Stong 25C = 9.07E-12 F
Weak 25C = 1.09E-11 F
0x3B CAP59 Nominal 25C = 1.02E-11 F
Stong 25C = 9.26E-12 F
Weak 25C = 1.11E-11 F
0x3C CAP60 Nominal 25C = 1.04E-11 F
Stong 25C = 9.45E-12 F
Weak 25C = 1.13E-11 F
0x3D CAP61 Nominal 25C = 1.06E-11 F
Stong 25C = 9.64E-12 F
Weak 25C = 1.15E-11 F
0x3E CAP62 Nominal 25C = 1.08E-11 F
Stong 25C = 9.82E-12 F
Weak 25C = 1.17E-11 F
0x3F CAP63 Nominal 25C = 1.10E-11 F
Stong 25C = 1.00E-11 F
Weak 25C = 1.19E-11 F
RW 0b10 1101

TOP:CKMD:AMPCFG0

Address Offset 0x0000 0124
Physical Address 0x4000 1124 Instance 0x4000 1124
Description Amplitude Compensation Configuration 0
Type RW
Bits Field Name Description Type Reset
31:28 Q2DLY Q2CAP change delay.

Number of clock cycles to wait before changing Q2CAP by one step.
Clock frequency defined in FSMRATE.		 RW 0x0
27:24 Q1DLY Q1CAP change delay.

Number of clock cycles to wait before changing Q1CAP by one step.
Clock frequency defined in FSMRATE.		 RW 0x0
23:20 ADCDLY ADC and PEAKDET startup time.

Number of clock cycles to wait after enabling the PEAKDET and ADC before the first measurement.
Clock frequency defined in FSMRATE.		 RW 0x3
19:15 LDOSTART LDO startup time.

Number of clock cycles to bypass the LDO resistors for faster startup.
Clock frequency defined in FSMRATE.		 RW 0b1 1111
14:10 INJWAIT Inject HFOSC for faster HFXT startup.

This value specifies the number of clock cycles to wait after injection is done.
The clock speed is defined in FSMRATE.		 RW 0b0 0010
9:5 INJTIME Inject HFOSC for faster HFXT startup.

This value specifies the number of clock cycles the injection is enabled.
The clock speed is defined in FSMRATE.
Set to 0 to disable injection.		 RW 0b0 0100
4:0 FSMRATE Update rate for the AMPCOMP update rate.
Also affects the clock rate for the Amplitude ADC.

The update rate is 6MHz / (FSMRATE+1).
Value ENUM Name Description
0x0 _6M 6 MHz
0x1 _3M 3 MHz
0x2 _2M 2 MHz
0x5 _1M 1 MHz
0xB _500K 500 kHz
0x17 _250K 250 kHz
RW 0b0 0010

TOP:CKMD:AMPCFG1

Address Offset 0x0000 0128
Physical Address 0x4000 1128 Instance 0x4000 1128
Description Amplitude Compensation Configuration 1
Type RW
Bits Field Name Description Type Reset
31:28 IDACDLY IDAC change delay.

Time to wait before changing IDAC by one step.
This time needs to be long enough for the crystal to settle.
The number of clock cycles to wait is IDACDLY<<4 + 15.
Clock frequency defined in AMPCFG0.FSMRATE.		 RW 0x2
27:24 IREFDLY IREF change delay.

Number of clock cycles to wait before changing IREF by one step.
Clock frequency defined in AMPCFG0.FSMRATE.		 RW 0x6
23:12 BIASLT Lifetime of the amplitude ADC bias value.
This value specifies the number of adjustment intervals,
until the ADC bias value has to be measured again.
Set to 0 to disable automatic bias measurements.		 RW 0x0FF
11:0 INTERVAL Interval for amplitude adjustments.
Set to 0 to disable periodic adjustments.

This value specifies the number of clock cycles between adjustments.
The clock speed is defined in [CKM.AMPCFG0.FSMRATE].		 RW 0x0FF

TOP:CKMD:LOOPCFG

Address Offset 0x0000 012C
Physical Address 0x4000 112C Instance 0x4000 112C
Description Configuration Register for the Tracking Loop. Writing to this MMR will override the filter output to FINETRIM_INIT.
Type RW
Bits Field Name Description Type Reset
31:26 FINETRIM_INIT Initial value for the resistor fine trim RW 0b01 1000
25:21 BOOST_TARGET Error-updates for 4xBOOST_TARGET times using KI_BOOST/KP_BOOST, before using KI/KP.
Note: If boost is used for long duration using large values of KI_BOOST & KP_BOOST, the oscillator frequency can reach well above the max frequence limit of the design, causing unexpected behaviour.		 RW 0b0 0010
20:18 KP_BOOST Proportional loop coefficient during BOOST RW 0b111
17:15 KI_BOOST Integral loop coefficient during BOOST RW 0b100
14:10 SETTLED_TARGET Number of updates before HFOSC is considered "settled" RW 0b0 1100
9:6 OOR_LIMIT Out-of-range threshold. OOR_LIMIT is compared with absolute value of 5 MSB bits of loop filter error. RW 0xE
5:3 KP Proportional loop coefficient RW 0b110
2:0 KI Integral loop coefficient RW 0b010

TOP:CKMD:LOOPCFG1

Address Offset 0x0000 0130
Physical Address 0x4000 1130 Instance 0x4000 1130
Description Configuration Register for underclocking HFOSC
Type RW
Bits Field Name Description Type Reset
31:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
24:6 UNDERCLKCNT Timer to trigger HFOSC underclocking. The timer will run at approximately 32.768 KHz. RW 0b000 0000 0000 0000 0000
5:0 KIOFF Based on HFTRACKCTRL.UNDERCLK configuration, after an event is triggerred, KI of the HFOSC tracking loop will be reduced by this amount. RW 0b11 1111

TOP:CKMD:AFOSCCTL

Address Offset 0x0000 0140
Physical Address 0x4000 1140 Instance 0x4000 1140
Description Audio frequency oscillator control
Type RW
Bits Field Name Description Type Reset
31:24 PW Password protection for QUALBYP.

Write this field to 0xA5 to accept writes to QUALBYP.		 WO 0x00
23:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
2 AUTODIS If set, AFOSC can be disabled by PMCTL upon standby entry. EN bit will be overriden with a value 0 and user has to manually re-enable AFOSC. RW 0
1 QUALBYP Clock qualification bypass.

AFOSC qualification will skip a fixed number of clock cycles to prevent glitches
or frequency overshoots from reaching the system. Setting this bit will bypass the qualification.
This bit can be locked in SYS0. If unlocked, it is password protected with PW.		 RW 0
0 EN Enable AFOSC. RW 0

TOP:CKMD:AFTRACKCTL

Address Offset 0x0000 0144
Physical Address 0x4000 1144 Instance 0x4000 1144
Description Audio frequency tracking loop control
Type RW
Bits Field Name Description Type Reset
31 EN Enable tracking loop. RW 0
30 DSMBYP Bypass Delta-Sigma-Modulation of fine trim. RW 0
29:0 RATIO Ratio. Ratio format is 0b.30b
Value ENUM Name Description
0x7D6343F _98MHZ
0x88190AC _90P288MHZ
0x8EE23B9 _86MHZ
0x999999A _80MHZ
0x9B8B578 _79MHZ
RW 0b00 1001 1001 1001 1001 1001 1001 1010

TOP:CKMD:BANDGAPCTL

Address Offset 0x0000 0148
Physical Address 0x4000 1148 Instance 0x4000 1148
Description Configuration Register for the Tracking Loop
Type RW
Bits Field Name Description Type Reset
31 BGOVR Software override for bandgap control signals.
This field is locked using the global-lock within SYS0.		 RW 0
30:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
3 VBGAPBYP Bandgap reference enable. RW 0
2 VBGAPREFEN Bandgap bypass counter. The counter runs at 24 MHz. RW 0
1 VDDRREFEN This MMR is used only when BANDCFG.BGOVR is set. RW 0
0 REFEN Enable reference voltage to AFOSC and HFOSC. This MMR is used only when BANDCFG.BGOVR is set. RW 0

TOP:CKMD:AFCLKSEL

Address Offset 0x0000 0150
Physical Address 0x4000 1150 Instance 0x4000 1150
Description Audio clock selection
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 SRC Select audio frequency clock source

Software should make sure that proper clock is selected before enabling the audio IP.
Value ENUM Name Description
0x0 DIS Clock disabled
0x1 CLKAF AFOSC clock
0x2 CLKHF 96MHz CLKHF
0x3 CLKREF 48MHz reference clock (HFXT)
0x4 CLKEXT External clock
RW 0b000

TOP:CKMD:CANCLKSEL

Address Offset 0x0000 0154
Physical Address 0x4000 1154 Instance 0x4000 1154
Description CAN clock selection
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 SRC Select audio frequency clock source

Software should make sure that proper clock is selected before enabling the audio IP.
Value ENUM Name Description
0x0 DIS Clock disabled
0x1 CLKAF AFOSC clock
0x2 CLKHF 96MHz CLKHF
RW 0b00

TOP:CKMD:TRACKSTATAF

Address Offset 0x0000 0160
Physical Address 0x4000 1160 Instance 0x4000 1160
Description AF tracking loop status information
Type RO
Bits Field Name Description Type Reset
31 LOOPERRVLD Current AFOSC tracking error valid

This bit is one if the tracking loop is running and the error value is valid.		 RO 0
30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
29:16 LOOPERR Current AFOSC tracking error

This field uses the internal fractional representation (sign, 9 integer bits, 4 fractional bits).
The actual fine trim value of format (sign, 9 integer bits, 30 fractional bits) is saturated to (sign, 9 integer bits, 4 fractional bits).		 RO 0b00 0000 0000 0000
15:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
12:0 FINETRIM Current AFOSC Fine-trim value

This field uses the internal fractional representation (sign, 5 integer bits, 7 fractional bits).
The actual fine trim value of format (sign, 5 integer bits, 19 fractional bits) is saturated to (sign, 5 integer bits, 7 fractional bits).
The actual trim value applied to the oscillator is delta-sigma modulated 6 bits non-signed
(inverted sign bit + integer bits).		 RO 0b1 1101 1000 0000

TOP:CKMD:TRACKSTATAF1

Address Offset 0x0000 0164
Physical Address 0x4000 1164 Instance 0x4000 1164
Description AF tracking loop status information
Type RO
Bits Field Name Description Type Reset
31:30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
29:0 LOOPERR Current AFOSC tracking error

This field uses the fractional representation of the actual error(30 fractional bits). The actual error is of format (sign, 9 integer bits, 30 fractional bits).		 RO 0b00 0000 0000 0000 0000 0000 0000 0000

TOP:CKMD:TRACKSTATAF2

Address Offset 0x0000 0168
Physical Address 0x4000 1168 Instance 0x4000 1168
Description AF tracking loop status information
Type RW
Bits Field Name Description Type Reset
31:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
24:0 FINETRIM Current AFOSC Fine-trim value

This field uses the internal fractional representation (sign, 4 integer bits, 8 fractional bits).
The actual trim value applied to the oscillator is delta-sigma modulated 5 bits non-signed
(inverted sign bit + integer bits).		 RO 0b1 1101 1000 0000 0000 0000 0000

TOP:CKMD:LOOPCFGAF

Address Offset 0x0000 0170
Physical Address 0x4000 1170 Instance 0x4000 1170
Description Configuration Register for the Audio frequency Tracking Loop
Type RW
Bits Field Name Description Type Reset
31:26 FINETRIM_INIT Initial value for the resistor fine trim RW 0b00 1100
25:21 BOOST_TARGET Number of error-updates using BOOST values, before using KI/KP RW 0b0 0010
20:18 KP_BOOST Proportional loop coefficient during BOOST RW 0b111
17:15 KI_BOOST Integral loop coefficient during BOOST RW 0b100
14:10 SETTLED_TARGET Number of updates before AFOSC is considered "settled" RW 0b0 1100
9:6 OOR_LIMIT Out-of-range threshold. Out-of-range threshold. OOR_LIMIT is compared with absolute value of 5 MSB bits of loop filter error. RW 0xE
5:3 KP Proportional loop coefficient RW 0b110
2:0 KI Integral loop coefficient RW 0b011

TOP:CKMD:CTL

Address Offset 0x0000 0200
Physical Address 0x4000 1200 Instance 0x4000 1200
Description Control
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 CMD TDC commands.
Value ENUM Name Description
0x0 CLR_RESULT Clear [TDC.STAT.SAT], [TDC.STAT.DONE], and [TDC.RESULT.VALUE].

This is not needed as prerequisite for a measurement. Reliable clear is only guaranteed from IDLE state.
0x1 RUN_SYNC_START Synchronous counter start.

The counter looks for the opposite edge of the selected start event before it starts to count when the selected edge occurs. This guarantees an edge-triggered start and is recommended for frequency measurements.
0x2 RUN Asynchronous counter start.

The counter starts to count when the start event is high. To achieve precise edge-to-edge measurements you must ensure that the start event is low for at least 420 ns after you write this command.
0x3 ABORT Force TDC state machine back to IDLE state.

Never write this command while [TDC.STAT.STATE] equals CLR_CNT or WAIT_CLR_CNT_DONE.
WO 0b00

TOP:CKMD:STAT

Address Offset 0x0000 0204
Physical Address 0x4000 1204 Instance 0x4000 1204
Description Status
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 SAT TDC measurement saturation flag.

0: Conversion has not saturated.
1: Conversion stopped due to saturation.

This field is cleared when a new measurement is started or when CLR_RESULT is written to [TDC.CTL.CMD].		 RO 0
6 DONE TDC measurement complete flag.

0: TDC measurement has not yet completed.
1: TDC measurement has completed.

This field clears when a new TDC measurement starts or when you write CLR_RESULT to [TDC.CTL.CMD].		 RO 0
5:0 STATE TDC state machine status.
Value ENUM Name Description
0x0 WAIT_START Current state is TDC_STATE_WAIT_START.
The fast-counter circuit looks for the start condition. The state machine waits for the fast-counter to increment.
0x4 WAIT_START_STOP_CNT_EN Current state is TDC_STATE_WAIT_STARTSTOPCNTEN.
The fast-counter circuit looks for the start condition. The state machine waits for the fast-counter to increment.
0x6 IDLE Current state is TDC_STATE_IDLE.
This is the default state after reset and abortion. State will change when you write [TDC.CTL.CMD] to either RUN_SYNC_START or RUN.
0x7 CLR_CNT Current state is TDC_STATE_CLRCNT. The fast-counter circuit is reset.
0x8 WAIT_STOP Current state is TDC_STATE_WAIT_STOP.
The state machine waits for the fast-counter circuit to stop.
0xC WAIT_STOP_CNTDWN Current state is TDC_STATE_WAIT_STOPCNTDOWN.
The fast-counter circuit looks for the stop condition. It will ignore a number of stop events configured in [TDC.TRIGCNTLOAD.CNT].
0xE GET_RESULT Current state is TDC_STATE_GETRESULTS.
The state machine copies the counter value from the fast-counter circuit.
0xF POR Current state is TDC_STATE_POR.
This is the reset state.
0x16 WAIT_CLR_CNT_DONE Current state is TDC_STATE_WAIT_CLRCNT_DONE.
The state machine waits for fast-counter circuit to finish reset.
0x1E START_FALL Current state is TDC_WAIT_STARTFALL.
The fast-counter circuit waits for a falling edge on the start event.
0x2E FORCE_STOP Current state is TDC_FORCESTOP.
You wrote ABORT to [TDC.CTL.CMD] to abort the TDC measurement.
RO 0b00 0110

TOP:CKMD:RESULT

Address Offset 0x0000 0208
Physical Address 0x4000 1208 Instance 0x4000 1208
Description Result

Result of last TDC conversion.
Type RO
Bits Field Name Description Type Reset
31:0 VALUE TDC conversion result.

The result of the TDC conversion is given in number of clock edges of the clock source selected in [IPSPECIFIC.CKM.TDCCLKSEL.REFCLK]. Both rising and falling edges are counted.

Note that [TDC.SATCFG.LIMIT] is given in periods, while VALUE is given in edges (periods*2).
If TDC counter saturates, VALUE is slightly higher than [TDC.SATCFG.LIMIT]*2, as it takes a non-zero time to stop the measurement. Hence, the maximum value of this field becomes slightly higher than 2^31 (2^30 periods*2) if you configure [TDC.SATCFG.LIMIT] to R30.		 RO 0x0000 0002

TOP:CKMD:SATCFG

Address Offset 0x0000 020C
Physical Address 0x4000 120C Instance 0x4000 120C
Description Saturation Configuration
Type RW
Bits Field Name Description Type Reset
31:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
4:0 LIMIT Saturation limit.

The flag [TDC.STAT.SAT] is set when the TDC counter saturates.
Note that this value is given in periods, while [TDC.RESULT.VALUE] is given in edges (periods*2).

Values not enumerated are not supported
Value ENUM Name Description
0x0 NONE No saturation. An additional timer should be used to know if [TDC.RESULT.VALUE] rolled over.
0x3 R12 TDC conversion saturates and stops after 2^12 periods.
0x4 R13 TDC conversion saturates and stops after 2^13 periods.
0x5 R14 TDC conversion saturates and stops after 2^14 periods.
0x6 R15 TDC conversion saturates and stops after 2^15 periods.
0x7 R16 TDC conversion saturates and stops after 2^16 periods.
0x8 R17 TDC conversion saturates and stops after 2^17 periods.
0x9 R18 TDC conversion saturates and stops after 2^18 periods.
0xA R19 TDC conversion saturates and stops after 2^19 periods.
0xB R20 TDC conversion saturates and stops after 2^20 periods.
0xC R21 TDC conversion saturates and stops after 2^21 periods.
0xD R22 TDC conversion saturates and stops after 2^22 periods.
0xE R23 TDC conversion saturates and stops after 2^23 periods.
0xF R24 TDC conversion saturates and stops after 2^24 periods.
0x10 R25 TDC conversion saturates and stops after 2^25 periods.
0x11 R26 TDC conversion saturates and stops after 2^26 periods.
0x12 R27 TDC conversion saturates and stops after 2^27 periods.
0x13 R28 TDC conversion saturates and stops after 2^28 periods.
0x14 R29 TDC conversion saturates and stops after 2^29 periods.
0x15 R30 TDC conversion saturates and stops after 2^30 periods.
RW 0b0 0000

TOP:CKMD:TRIGSRC

Address Offset 0x0000 0210
Physical Address 0x4000 1210 Instance 0x4000 1210
Description Trigger Source

Select source and polarity for TDC start and stop events. See the Technical Reference Manual for event timing requirements.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 STOP_POL Polarity of stop source.

Change only while [TDC.STAT.STATE] is IDLE.
Value ENUM Name Description
0x0 HIGH TDC conversion stops when high level is detected.
0x1 LOW TDC conversion stops when low level is detected.
RW 0
14:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
12:8 STOP_SRC Select stop source from the asynchronous AUX event bus.

Change only while [TDC.STAT.STATE] is IDLE.
Value ENUM Name Description
0x0 LFTICK LFTICK signal going to the RTC
0x1 LFOSC Low frequency on-chip oscillator
0x2 LFXT Low frequency crystal oscillator
0x3 LFCLK_DLY Delayed version of selected LFCLK
0x4 GPI General purpose input signal
0x5 DTB0 Digital testbus bit 0
0x6 DTB1 Digital testbus bit 1
0x7 DTB2 Digital testbus bit 2
0x8 DTB3 Digital testbus bit 3
0x9 DTB4 Digital testbus bit 4
0xA DTB5 Digital testbus bit 5
0xB DTB6 Digital testbus bit 6
0xC DTB7 Digital testbus bit 7
0xD DTB8 Digital testbus bit 8
0xE DTB9 Digital testbus bit 9
0xF DTB10 Digital testbus bit 10
0x10 DTB11 Digital testbus bit 11
0x11 DTB12 Digital testbus bit 12
0x12 DTB13 Digital testbus bit 13
0x13 DTB14 Digital testbus bit 14
0x14 DTB15 Digital testbus bit 15
0x1F TDC_PRE Select TDC Prescaler event which is generated by configuration of TDC.PRECTL.
RW 0b0 0000
7 START_POL Polarity of start source.

Change only while [TDC.STAT.STATE] is IDLE.
Value ENUM Name Description
0x0 HIGH TDC conversion starts when high level is detected.
0x1 LOW TDC conversion starts when low level is detected.
RW 0
6:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
4:0 START_SRC Select start source from the asynchronous AUX event bus.

Change only while [TDC.STAT.STATE] is IDLE.
Value ENUM Name Description
0x0 LFTICK LFTICK signal going to the RTC
0x1 LFOSC Low frequency on-chip oscillator
0x2 LFXT Low frequency crystal oscillator
0x3 LFCLK_DLY Delayed version of selected LFCLK
0x4 GPI General purpose input signal
0x5 DTB0 Digital testbus bit 0
0x6 DTB1 Digital testbus bit 1
0x7 DTB2 Digital testbus bit 2
0x8 DTB3 Digital testbus bit 3
0x9 DTB4 Digital testbus bit 4
0xA DTB5 Digital testbus bit 5
0xB DTB6 Digital testbus bit 6
0xC DTB7 Digital testbus bit 7
0xD DTB8 Digital testbus bit 8
0xE DTB9 Digital testbus bit 9
0xF DTB10 Digital testbus bit 10
0x10 DTB11 Digital testbus bit 11
0x11 DTB12 Digital testbus bit 12
0x12 DTB13 Digital testbus bit 13
0x13 DTB14 Digital testbus bit 14
0x14 DTB15 Digital testbus bit 15
0x1F TDC_PRE Select TDC Prescaler event which is generated by configuration of TDC.PRECTL.
RW 0b0 0000

TOP:CKMD:TRIGCNT

Address Offset 0x0000 0214
Physical Address 0x4000 1214 Instance 0x4000 1214
Description Trigger Counter

Stop-counter control and status.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 CNT Number of stop events to ignore when [TDC.TRIGCNTCFG.EN] is 1.

Read CNT to get the remaining number of stop events to ignore during a TDC measurement.

Write CNT to update the remaining number of stop events to ignore during a TDC measurement. The TDC measurement ignores updates of CNT if there are no more stop events left to ignore.

When [TDC.TRIGCNTCFG.EN] is 1, [TDC.TRIGCNTLOAD.CNT] is loaded into CNT at the start of the measurement.		 RW 0x0000

TOP:CKMD:TRIGCNTLOAD

Address Offset 0x0000 0218
Physical Address 0x4000 1218 Instance 0x4000 1218
Description Trigger Counter Load

Stop-counter load.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 CNT Number of stop events to ignore when [TDC.TRIGCNTCFG.EN] is 1.

To measure frequency of an event source:
- Set start event equal to stop event.
- Set CNT to number of periods to measure. Both 0 and 1 values measures a single event source period.

To measure pulse width of an event source:
- Set start event source equal to stop event source.
- Select different polarity for start and stop event.
- Set CNT to 0.

To measure time from the start event to the Nth stop event when N > 1:
- Select different start and stop event source.
- Set CNT to (N-1).

See the Technical Reference Manual for event timing requirements.

When [TDC.TRIGCNTCFG.EN] is 1, CNT is loaded into [TDC.TRIGCNT.CNT] at the start of the measurement.		 RW 0x0000

TOP:CKMD:TRIGCNTCFG

Address Offset 0x0000 021C
Physical Address 0x4000 121C Instance 0x4000 121C
Description Trigger Counter Configuration

Stop-counter configuration.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 EN Enable stop-counter.

0: Disable stop-counter.
1: Enable stop-counter.

Change only while [TDC.STAT.STATE] is IDLE.		 RW 0

TOP:CKMD:PRECTL

Address Offset 0x0000 0220
Physical Address 0x4000 1220 Instance 0x4000 1220
Description Prescaler Control

The prescaler can be used to count events that are faster than the bus rate.
It can be used to:
- count pulses on a specified event from the asynchronous event bus.
- prescale a specified event from the asynchronous event bus.

To use the prescaler output as an event source in TDC measurements you must set both TRIGSRC.START_SRC and TRIGSRC.STOP_SRC to TDC_PRE.

It is recommended to use the prescaler when the signal frequency to measure exceeds 1/10th of the bus rate.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 RESET_N Prescaler reset.

0: Reset prescaler.
1: Release reset of prescaler.

AUX_TDC_PRE event becomes 0 when you reset the prescaler.		 RW 0
6 RATIO Prescaler ratio.

This controls how often the TDC_PRE event is generated by the prescaler.
Value ENUM Name Description
0x0 DIV16 Prescaler divides input by 16.

AUX_TDC_PRE event has a rising edge for every 16 rising edges of the input. AUX_TDC_PRE event toggles on every 8th rising edge of the input.
0x1 DIV64 Prescaler divides input by 64.

AUX_TDC_PRE event has a rising edge for every 64 rising edges of the input. AUX_TDC_PRE event toggles on every 32nd rising edge of the input.
RW 0
5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
4:0 SRC Prescaler event source.

Select an event from the asynchronous AUX event bus to connect to the prescaler input.

Configure only while RESET_N is 0.
Value ENUM Name Description
0x0 LFTICK LFTICK signal going to the RTC
0x1 LFOSC Low frequency on-chip oscillator
0x2 LFXT Low frequency crystal oscillator
0x3 LFCLK_DLY Delayed version of selected LFCLK
0x4 GPI General purpose input signal
0x5 DTB0 Digital testbus bit 0
0x6 DTB1 Digital testbus bit 1
0x7 DTB2 Digital testbus bit 2
0x8 DTB3 Digital testbus bit 3
0x9 DTB4 Digital testbus bit 4
0xA DTB5 Digital testbus bit 5
0xB DTB6 Digital testbus bit 6
0xC DTB7 Digital testbus bit 7
0xD DTB8 Digital testbus bit 8
0xE DTB9 Digital testbus bit 9
0xF DTB10 Digital testbus bit 10
0x10 DTB11 Digital testbus bit 11
0x11 DTB12 Digital testbus bit 12
0x12 DTB13 Digital testbus bit 13
0x13 DTB14 Digital testbus bit 14
0x14 DTB15 Digital testbus bit 15
0x15 HFOSC High frequency on-chip oscillator
0x16 HFXT High frequency crystal oscillator
0x17 AFOSC Audio frequency on-chip oscillator
RW 0b0 0000

TOP:CKMD:PRECNTR

Address Offset 0x0000 0224
Physical Address 0x4000 1224 Instance 0x4000 1224
Description Prescaler Counter
Type RW
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000
16 CAPT Prescaler counter capture strobe.

Write a 1 to CAPT to capture the value of the 16-bit prescaler counter into CNT. Read CNT to get the captured value.		 WO 0
15:0 CNT Prescaler counter value.

Write a 1 to CAPT to capture the value of the 16-bit prescaler counter into CNT. Read CNT to get the captured value.

The read value gets 1 LSB uncertainty if the event source level rises when you release the reset.
The read value gets 1 LSB uncertainty if the event source level rises when you capture the prescaler counter.

Please note the following:
- The prescaler counter is reset to 3 by [TDC.PRECTL.RESET_N].
- The captured value is 3 when the number of rising edges on prescaler input is less than 3. Otherwise, captured value equals number of event pulses.		 RO 0x0000

TOP:CKMD:CNT

Address Offset 0x0000 0300
Physical Address 0x4000 1300 Instance 0x4000 1300
Description WDT counter value register
Type RW
Bits Field Name Description Type Reset
31:0 VAL Counter value.

A write to this field immediately starts (or restarts) the counter. It will count down from the written value.
If the counter reaches 0, a reset will be generated.
A write value of 0 immediately generates a reset.

This field is only writable if not locked. See LOCK register.
Writing this field will automatically activate the lock.

A read returns the current value of the counter.		 RW 0x0000 0000

TOP:CKMD:TEST

Address Offset 0x0000 0304
Physical Address 0x4000 1304 Instance 0x4000 1304
Description WDT test mode register
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 STALLEN WDT stall enable

This field is only writable if not locked. See LOCK register.
Value ENUM Name Description
0x0 DIS DISABLE

WDT continues counting while the CPU is stopped by a debugger.
0x1 EN ENABLE

WDT stops counting while the CPU is stopped by a debugger.
RW 0

TOP:CKMD:LOCK

Address Offset 0x0000 0308
Physical Address 0x4000 1308 Instance 0x4000 1308
Description WDT lock register
Type RW
Bits Field Name Description Type Reset
31:0 STAT A write with value 0x1ACCE551 unlocks the watchdog registers for write access.
A write with any other value locks the watchdog registers for write access.
Writing the CNT register will also lock the watchdog registers.

A read of this field returns the state of the lock (0=unlocked, 1=locked).		 RW 0x0000 0001


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