ADC

Instance: ADC
Component: ADC
Base address: 0x40050000


TOP:ADC Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

IMASK

RW

32

0x0000 0000

0x0000 1028

0x4005 1028

RIS

RO

32

0x0000 0000

0x0000 1030

0x4005 1030

MIS

RO

32

0x0000 0000

0x0000 1038

0x4005 1038

ISET

WO

32

0x0000 0000

0x0000 1040

0x4005 1040

ICLR

WO

32

0x0000 0000

0x0000 1048

0x4005 1048

IMASK

RW

32

0x0000 0000

0x0000 1058

0x4005 1058

RIS

RO

32

0x0000 0000

0x0000 1060

0x4005 1060

MIS

RO

32

0x0000 0000

0x0000 1068

0x4005 1068

ISET

WO

32

0x0000 0000

0x0000 1070

0x4005 1070

ICLR

WO

32

0x0000 0000

0x0000 1078

0x4005 1078

IMASK

RW

32

0x0000 0000

0x0000 1088

0x4005 1088

RIS

RO

32

0x0000 0000

0x0000 1090

0x4005 1090

MIS

RO

32

0x0000 0000

0x0000 1098

0x4005 1098

ISET

WO

32

0x0000 0000

0x0000 10A0

0x4005 10A0

ICLR

WO

32

0x0000 0000

0x0000 10A8

0x4005 10A8

CTL0

RW

32

0x0000 0000

0x0000 1100

0x4005 1100

CTL1

RW

32

0x0000 0000

0x0000 1104

0x4005 1104

CTL2

RW

32

0x0000 0000

0x0000 1108

0x4005 1108

CTL3

RW

32

0x0000 0000

0x0000 110C

0x4005 110C

SCOMP0

RW

32

0x0000 0000

0x0000 1114

0x4005 1114

SCOMP1

RW

32

0x0000 0000

0x0000 1118

0x4005 1118

REFCFG

RW

32

0x0000 0000

0x0000 111C

0x4005 111C

WCLOW

RW

32

0x0000 0000

0x0000 1148

0x4005 1148

WCHIGH

RW

32

0x0000 0000

0x0000 1150

0x4005 1150

FIFODATA

RO

32

0x0000 0000

0x0000 1160

0x4005 1160

ASCRES

RO

32

0x0000 0000

0x0000 1170

0x4005 1170

MEMCTL__0-MEMCTL__3

RW

32

0x0000 0000

0x0000 1180 - 0x0000 118C

0x4005 1180 - 0x4005 118C

MEMRES__0-MEMRES__3

RO

32

0x0000 0000

0x0000 1280 - 0x0000 128C

0x4005 1280 - 0x4005 128C

STATUS

RO

32

0x0000 0000

0x0000 1340

0x4005 1340

TEST0

RW

32

0x0000 0000

0x0000 1E00

0x4005 1E00

TEST1

RW

32

0x0000 0000

0x0000 1E04

0x4005 1E04

TEST2

RW

32

0x0000 0000

0x0000 1E08

0x4005 1E08

TEST3

RW

32

0x0000 0000

0x0000 1E0C

0x4005 1E0C

TEST4

RW

32

0x0000 0000

0x0000 1E10

0x4005 1E10

TEST5

RW

32

0x0000 0000

0x0000 1E14

0x4005 1E14

TEST6

RW

32

0x0000 0000

0x0000 1E18

0x4005 1E18

DEBUG1

RW

32

0x0080 1000

0x0000 1E20

0x4005 1E20

DEBUG2

RW

32

0x0000 0000

0x0000 1E24

0x4005 1E24

DEBUG3

RW

32

0x0000 0000

0x0000 1E28

0x4005 1E28

DEBUG4

RW

32

0x0000 0000

0x0000 1E2C

0x4005 1E2C

TOP:ADC Register Descriptions

TOP:ADC:IMASK

Address Offset 0x0000 1028
Physical Address 0x4005 1028 Instance 0x4005 1028
Description Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Raw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 Raw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 Raw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7 ASCDONE Mask for ASC done raw interrupt flag
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
6 UVIFG Raw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
5 DMADONE Raw interrupt flag for DMADONE.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
4 INIFG Mask INIFG in MIS_EX register.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Raw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1 TOVIFG Raw interrupt flag for sequence conversion timeout overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
0 OVIFG Raw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0

TOP:ADC:RIS

Address Offset 0x0000 1030
Physical Address 0x4005 1030 Instance 0x4005 1030
Description Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
Type RO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Raw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 Raw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 Raw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7 ASCDONE Raw interrupt flag for ASC done
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
6 UVIFG Raw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
5 DMADONE Raw interrupt flag for DMADONE.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
4 INIFG Mask INIFG in MIS_EX register.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Raw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1 TOVIFG Raw interrupt flag for sequence conversion trigger overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
0 OVIFG Raw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0

TOP:ADC:MIS

Address Offset 0x0000 1038
Physical Address 0x4005 1038 Instance 0x4005 1038
Description Masked interrupt status. This is an AND of the IMASK and RIS registers.
Type RO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Raw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 Raw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 Raw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7 ASCDONE Masked interrupt status for ASC done
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
6 UVIFG Raw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
5 DMADONE Raw interrupt flag for DMADONE.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
4 INIFG Mask INIFG in MIS_EX register.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Raw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1 TOVIFG Raw interrupt flag for sequence conversion timeout overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
0 OVIFG Raw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0

TOP:ADC:ISET

Address Offset 0x0000 1040
Physical Address 0x4005 1040 Instance 0x4005 1040
Description Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
Type WO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Raw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 Raw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 Raw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7 ASCDONE Set ASC done flag in RIS
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
6 UVIFG Raw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
5 DMADONE Raw interrupt flag for DMADONE.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
4 INIFG Mask INIFG in MIS_EX register.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Raw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1 TOVIFG Raw interrupt flag for sequence conversion timeout overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
0 OVIFG Raw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0

TOP:ADC:ICLR

Address Offset 0x0000 1048
Physical Address 0x4005 1048 Instance 0x4005 1048
Description Interrupt clear. Write a 1 to clear corresponding Interrupt.
Type WO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Raw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
10 MEMRESIFG2 Raw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
9 MEMRESIFG1 Raw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
7 ASCDONE Clear ASC done flag in RIS
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
6 UVIFG Raw interrupt flag for MEMRESx underflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
5 DMADONE Raw interrupt flag for DMADONE.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
4 INIFG Mask INIFG in MIS_EX register.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
3 LOWIFG Raw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
2 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
1 TOVIFG Raw interrupt flag for sequence conversion timeout overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
0 OVIFG Raw interrupt flag for MEMRESx overflow.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0

TOP:ADC:IMASK

Address Offset 0x0000 1058
Physical Address 0x4005 1058 Instance 0x4005 1058
Description Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4 INIFG Mask INIFG in MIS_EX register.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Raw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00

TOP:ADC:RIS

Address Offset 0x0000 1060
Physical Address 0x4005 1060 Instance 0x4005 1060
Description Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
Type RO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4 INIFG Mask INIFG in MIS_EX register.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Raw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00

TOP:ADC:MIS

Address Offset 0x0000 1068
Physical Address 0x4005 1068 Instance 0x4005 1068
Description Masked interrupt status. This is an AND of the IMASK and RIS registers.
Type RO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4 INIFG Mask INIFG in MIS_EX register.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Raw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00

TOP:ADC:ISET

Address Offset 0x0000 1070
Physical Address 0x4005 1070 Instance 0x4005 1070
Description Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
Type WO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4 INIFG Mask INIFG in MIS_EX register.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Raw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00

TOP:ADC:ICLR

Address Offset 0x0000 1078
Physical Address 0x4005 1078 Instance 0x4005 1078
Description Interrupt clear. Write a 1 to clear corresponding Interrupt.
Type WO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4 INIFG Mask INIFG in MIS_EX register.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
3 LOWIFG Raw interrupt flag for the MEMRESx result register being below
than the WCLOWx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
2 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher
than the WCHIGHx threshold of the window comparator.
This bit is reset to 0 by IIDX read or when corresponding bit in
ICLR_EX is set to 1.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
1:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00

TOP:ADC:IMASK

Address Offset 0x0000 1088
Physical Address 0x4005 1088 Instance 0x4005 1088
Description Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Raw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 Raw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 Raw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00

TOP:ADC:RIS

Address Offset 0x0000 1090
Physical Address 0x4005 1090 Instance 0x4005 1090
Description Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
Type RO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Raw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 Raw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 Raw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00

TOP:ADC:MIS

Address Offset 0x0000 1098
Physical Address 0x4005 1098 Instance 0x4005 1098
Description Extension of Masked interrupt status. This is an AND of the IMASK and RIS registers.
Type RO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Raw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 Raw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 Raw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00

TOP:ADC:ISET

Address Offset 0x0000 10A0
Physical Address 0x4005 10A0 Instance 0x4005 10A0
Description Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
Type WO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Raw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 Raw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 Raw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00

TOP:ADC:ICLR

Address Offset 0x0000 10A8
Physical Address 0x4005 10A8 Instance 0x4005 10A8
Description Interrupt clear. Write a 1 to clear corresponding Interrupt.
Type WO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Raw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
10 MEMRESIFG2 Raw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
9 MEMRESIFG1 Raw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR is set to 1
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
7:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00

TOP:ADC:CTL0

Address Offset 0x0000 1100
Physical Address 0x4005 1100 Instance 0x4005 1100
Description Control Register 0
Type RW
Bits Field Name Description Type Reset
31:27 RESERVED27 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
26:24 SCLKDIV Sample clock divider
Value ENUM Name Description
0x0 DIV_BY_1 Do not divide clock source
0x1 DIV_BY_2 Divide clock source by 2
0x2 DIV_BY_4 Divide clock source by 4
0x3 DIV_BY_8 Divide clock source by 8
0x4 DIV_BY_16 Divide clock source by 16
0x5 DIV_BY_24 Divide clock source by 24
0x6 DIV_BY_32 Divide clock source by 32
0x7 DIV_BY_48 Divide clock source by 48
RW 0b000
23:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
16 PWRDN Power down policy
Value ENUM Name Description
0x0 AUTO ADC is powered down on completion of a conversion if there is no pending trigger
0x1 MANUAL ADC remains powered on as long as it is enabled through software.
RW 0
15:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000
0 ENC Enable conversion
Value ENUM Name Description
0x0 OFF Conversion disabled. ENC change from ON to OFF will abort single or repeat sequence on a MEMCTLx boundary. The current conversion will finish and result stored in corresponding MEMRESx.
0x1 ON Conversion enabled. ADC sequencer waits for valid trigger (software or hardware).
RW 0

TOP:ADC:CTL1

Address Offset 0x0000 1104
Physical Address 0x4005 1104 Instance 0x4005 1104
Description Control Register 1
Type RW
Bits Field Name Description Type Reset
31:21 RESERVED21 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
20 SAMPMODE Sample mode. This bit selects the source of the sampling signal.
MANUAL option is not valid when TRIGSRC is selected as hardware event trigger.
Value ENUM Name Description
0x0 AUTO Sample timer high phase is used as sample signal
0x1 MANUAL Software trigger is used as sample signal
RW 0
19:18 RESERVED18 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
17:16 CONSEQ Conversion sequence mode
Value ENUM Name Description
0x0 SINGLE ADC channel in MEMCTLx pointed by STARTADD will be converted once
0x1 SEQUENCE ADC channel sequence pointed by STARTADD and ENDADD will be converted once
0x2 REPEATSINGLE ADC channel in MEMCTLx pointed by STARTADD will be converted repeatedly
0x3 REPEATSEQUENCE ADC channel sequence pointed by STARTADD and ENDADD will be converted repeatedly
RW 0b00
15:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
8 SC Start of conversion
Value ENUM Name Description
0x0 STOP When SAMPMODE is set to MANUAL, clearing this bit will end the sample phase and the conversion phase will start.
When SAMPMODE is set to AUTO, writing 0 has no effect.
0x1 START When SAMPMODE is set to MANUAL, setting this bit will start the sample phase. Sample phase will last as long as this bit is set.
When SAMPMODE is set to AUTO, setting this bit will trigger the timer based sample time.
RW 0
7:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
0 TRIGSRC Sample trigger source
Value ENUM Name Description
0x0 SOFTWARE Software trigger
0x1 EVENT Hardware event trigger
RW 0

TOP:ADC:CTL2

Address Offset 0x0000 1108
Physical Address 0x4005 1108 Instance 0x4005 1108
Description Control Register 2
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:24 ENDADD Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode.
The value of ENDADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
Value ENUM Name Description
0x0 ADDR_00 MEMCTL0 is selected as end address of sequence.
0x1 ADDR_01 MEMCTL1 is selected as end address of sequence.
0x2 ADDR_02 MEMCTL2 is selected as end address of sequence.
0x3 ADDR_03 MEMCTL3 is selected as end address of sequence.
0x4 ADDR_04 MEMCTL4 is selected as end address of sequence.
0x5 ADDR_05 MEMCTL5 is selected as end address of sequence.
0x6 ADDR_06 MEMCTL6 is selected as end address of sequence.
0x7 ADDR_07 MEMCTL7 is selected as end address of sequence.
0x8 ADDR_08 MEMCTL8 is selected as end address of sequence.
0x9 ADDR_09 MEMCTL9 is selected as end address of sequence.
0xA ADDR_10 MEMCTL10 is selected as end address of sequence.
0xB ADDR_11 MEMCTL11 is selected as end address of sequence.
0xC ADDR_12 MEMCTL12 is selected as end address of sequence.
0xD ADDR_13 MEMCTL13 is selected as end address of sequence.
0xE ADDR_14 MEMCTL14 is selected as end address of sequence.
0xF ADDR_15 MEMCTL15 is selected as end address of sequence.
0x10 ADDR_16 MEMCTL16 is selected as end address of sequence.
0x11 ADDR_17 MEMCTL17 is selected as end address of sequence.
0x12 ADDR_18 MEMCTL18 is selected as end address of sequence.
0x13 ADDR_19 MEMCTL19 is selected as end address of sequence.
0x14 ADDR_20 MEMCTL20 is selected as end address of sequence.
0x15 ADDR_21 MEMCTL21 is selected as end address of sequence.
0x16 ADDR_22 MEMCTL22 is selected as end address of sequence.
0x17 ADDR_23 MEMCTL23 is selected as end address of sequence.
RW 0b0 0000
23:21 RESERVED21 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
20:16 STARTADD Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode.
The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
Value ENUM Name Description
0x0 ADDR_00 MEMCTL0 is selected as start address of a sequence or for a single conversion.
0x1 ADDR_01 MEMCTL1 is selected as start address of a sequence or for a single conversion.
0x2 ADDR_02 MEMCTL2 is selected as start address of a sequence or for a single conversion.
0x3 ADDR_03 MEMCTL3 is selected as start address of a sequence or for a single conversion.
0x4 ADDR_04 MEMCTL4 is selected as start address of a sequence or for a single conversion.
0x5 ADDR_05 MEMCTL5 is selected as start address of a sequence or for a single conversion.
0x6 ADDR_06 MEMCTL6 is selected as start address of a sequence or for a single conversion.
0x7 ADDR_07 MEMCTL7 is selected as start address of a sequence or for a single conversion.
0x8 ADDR_08 MEMCTL8 is selected as start address of a sequence or for a single conversion.
0x9 ADDR_09 MEMCTL9 is selected as start address of a sequence or for a single conversion.
0xA ADDR_10 MEMCTL10 is selected as start address of a sequence or for a single conversion.
0xB ADDR_11 MEMCTL11 is selected as start address of a sequence or for a single conversion.
0xC ADDR_12 MEMCTL12 is selected as start address of a sequence or for a single conversion.
0xD ADDR_13 MEMCTL13 is selected as start address of a sequence or for a single conversion.
0xE ADDR_14 MEMCTL14 is selected as start address of a sequence or for a single conversion.
0xF ADDR_15 MEMCTL15 is selected as start address of a sequence or for a single conversion.
0x10 ADDR_16 MEMCTL16 is selected as start address of a sequence or for a single conversion.
0x11 ADDR_17 MEMCTL17 is selected as start address of a sequence or for a single conversion.
0x12 ADDR_18 MEMCTL18 is selected as start address of a sequence or for a single conversion.
0x13 ADDR_19 MEMCTL19 is selected as start address of a sequence or for a single conversion.
0x14 ADDR_20 MEMCTL20 is selected as start address of a sequence or for a single conversion.
0x15 ADDR_21 MEMCTL21 is selected as start address of a sequence or for a single conversion.
0x16 ADDR_22 MEMCTL22 is selected as start address of a sequence or for a single conversion.
0x17 ADDR_23 MEMCTL23 is selected as start address of a sequence or for a single conversion.
RW 0b0 0000
15:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
10 FIFOEN Enable FIFO based operation
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0
9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
8 DMAEN Enable DMA trigger for data transfer.
Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers.
Value ENUM Name Description
0x0 DISABLE DMA trigger not enabled
0x1 ENABLE DMA trigger enabled
RW 0
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2:1 RES Resolution. These bits define the resolution of ADC conversion result.
Note : A value of 3 defaults to 12-bits resolution.
Value ENUM Name Description
0x0 BIT_12 12-bits resolution
0x1 BIT_10 10-bits resolution
0x2 BIT_8 8-bits resolution
RW 0b00
0 DF Data read-back format. Data is always stored in binary unsigned format.
Value ENUM Name Description
0x0 UNSIGNED Digital result reads as Binary Unsigned.
0x1 SIGNED Digital result reads Signed Binary. (2s complement), left aligned.
RW 0

TOP:ADC:CTL3

Address Offset 0x0000 110C
Physical Address 0x4005 110C Instance 0x4005 110C
Description Control Register 3. This register is used to configure ADC for ad-hoc single conversion.
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13:12 ASCVRSEL Selects voltage reference for ASC operation. VEREFM must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
Value ENUM Name Description
0x0 VDDA VDDA reference.
0x1 EXTREF EXTREF pin reference.
0x2 INTREF Internal reference.
RW 0b00
11:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
8 ASCSTIME ASC sample time compare value select. This is used to select between SCOMP0 and SCOMP1 registers for ASC operation.
Value ENUM Name Description
0x0 SEL_SCOMP0 Select SCOMP0
0x1 SEL_SCOMP1 Select SCOMP1
RW 0
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4:0 ASCCHSEL ASC channel select
Value ENUM Name Description
0x0 CHAN_0 Selects channel 0
0x1 CHAN_1 Selects channel 1
0x2 CHAN_2 Selects channel 2
0x3 CHAN_3 Selects channel 3
0x4 CHAN_4 Selects channel 4
0x5 CHAN_5 Selects channel 5
0x6 CHAN_6 Selects channel 6
0x7 CHAN_7 Selects channel 7
0x8 CHAN_8 Selects channel 8
0x9 CHAN_9 Selects channel 9
0xA CHAN_10 Selects channel 10
0xB CHAN_11 Selects channel 11
0xC CHAN_12 Selects channel 12
0xD CHAN_13 Selects channel 13
0xE CHAN_14 Selects channel 14
0xF CHAN_15 Selects channel 15
0x10 CHAN_16 Selects channel 16
0x11 CHAN_17 Selects channel 17
0x12 CHAN_18 Selects channel 18
0x13 CHAN_19 Selects channel 19
0x14 CHAN_20 Selects channel 20
0x15 CHAN_21 Selects channel 21
0x16 CHAN_22 Selects channel 22
0x17 CHAN_23 Selects channel 23
0x18 CHAN_24 Selects channel 24
0x19 CHAN_25 Selects channel 25
0x1A CHAN_26 Selects channel 26
0x1B CHAN_27 Selects channel 27
0x1C CHAN_28 Selects channel 28
0x1D CHAN_29 Selects channel 29
0x1E CHAN_30 Selects channel 30
0x1F CHAN_31 Selects channel 31
RW 0b0 0000

TOP:ADC:SCOMP0

Address Offset 0x0000 1114
Physical Address 0x4005 1114 Instance 0x4005 1114
Description Sample time compare 0 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be 0 to write to this register.
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 VAL Specifies the number of sample clocks.
When VAL = 0 or 1, number of sample clocks = Sample clock divide value.
When VAL > 1, number of sample clocks = VAL x Sample clock divide value.
Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4).
Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.		 RW 0b00 0000 0000

TOP:ADC:SCOMP1

Address Offset 0x0000 1118
Physical Address 0x4005 1118 Instance 0x4005 1118
Description Sample time compare 1 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be 0 to write to this register.
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 VAL Specifies the number of sample clocks.
When VAL = 0 or 1, number of sample clocks = Sample clock divide value.
When VAL > 1, number of sample clocks = VAL x Sample clock divide value.
Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4).
Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.		 RW 0b00 0000 0000

TOP:ADC:REFCFG

Address Offset 0x0000 111C
Physical Address 0x4005 111C Instance 0x4005 111C
Description Reference buffer configuration register
Type RW
Bits Field Name Description Type Reset
31:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
4:3 IBPROG Configures reference buffer bias current output value
Value ENUM Name Description
0x0 VAL0 1uA
0x1 VAL1 0.5uA
0x2 VAL2 2uA
0x3 VAL3 0.67uA
RW 0b00
2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
1 REFVSEL Configures reference buffer output voltage
Value ENUM Name Description
0x0 V2P5 Reference buffer generates 2.5 V output
0x1 V1P4 Reference buffer generates 1.4 V output
RW 0
0 REFEN Reference buffer enable
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0

TOP:ADC:WCLOW

Address Offset 0x0000 1148
Physical Address 0x4005 1148 Instance 0x4005 1148
Description Window Comparator Low Threshold Register.
The data format that is used to write and read WCLOW depends on the value of DF bit in CTL2 register.
CTL0.ENC must be 0 to write to this register.
Note: Change in ADC data format or resolution does not reset WCLOW.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA If DF = 0, unsigned binary format has to be used.
The value based on the resolution has to be right aligned with the MSB on the left.
For 10-bits and 8-bits resolution, unused bits have to be 0s.

If DF = 1, 2s-complement format has to be used.
The value based on the resolution has to be left aligned with the LSB on the right.
For 10-bits and 8-bits resolution, unused bits have to be 0s.		 RW 0x0000

TOP:ADC:WCHIGH

Address Offset 0x0000 1150
Physical Address 0x4005 1150 Instance 0x4005 1150
Description Window Comparator High Threshold Register.
The data format that is used to write and read WCHIGH depends on the value of DF bit in CTL2 register.
CTL0.ENC must be 0 to write to this register.
Note: Change in ADC data format or resolution does not reset WCHIGH.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA If DF = 0, unsigned binary format has to be used.
The threshold value has to be right aligned, with the MSB on the left.
For 10-bits and 8-bits resolution, unused bit have to be 0s.

If DF = 1, 2s-complement format has to be used.
The value based on the resolution has to be left aligned with the LSB on the right.
For 10-bits and 8-bits resolution, unused bit have to be 0s.		 RW 0x0000

TOP:ADC:FIFODATA

Address Offset 0x0000 1160
Physical Address 0x4005 1160 Instance 0x4005 1160
Description FIFO data register. This is a virtual register used to do read from FIFO.
Type RO
Bits Field Name Description Type Reset
31:0 DATA Read from this data field returns the ADC sample from FIFO. RW 0x0000 0000

TOP:ADC:ASCRES

Address Offset 0x0000 1170
Physical Address 0x4005 1170 Instance 0x4005 1170
Description ASC result register
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA Result of ADC ad-hoc single conversion.
If DF = 0, unsigned binary:
The conversion result is right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion result is left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.		 RO 0x0000

TOP:ADC:MEMCTL__0-MEMCTL__3

Address Offset 0x0000 1180 - 0x0000 118C
Physical Address 0x4005 1180 - 0x4005 118C Instance 0x4005 1180 - 0x4005 118C
Description Conversion Memory Control Register.
CTL0.ENC must be 0 to write to this register.
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28 WINCOMP Enable window comparator.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0
27:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
24 TRIG Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
Value ENUM Name Description
0x0 AUTO_NEXT Next conversion is automatic
0x1 TRIGGER_NEXT Next conversion requires a trigger
RW 0
23:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
12 STIME Selects the source of sample timer period between SCOMP0 and SCOMP1.
Value ENUM Name Description
0x0 SEL_SCOMP0 Select SCOMP0
0x1 SEL_SCOMP1 Select SCOMP1
RW 0
11:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
9:8 VRSEL Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
Value ENUM Name Description
0x0 VDDA VDDA reference
0x1 EXTREF External reference from pin
0x2 INTREF Internal reference
RW 0b00
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4:0 CHANSEL Input channel select.
Value ENUM Name Description
0x0 CHAN_0 Selects channel 0
0x1 CHAN_1 Selects channel 1
0x2 CHAN_2 Selects channel 2
0x3 CHAN_3 Selects channel 3
0x4 CHAN_4 Selects channel 4
0x5 CHAN_5 Selects channel 5
0x6 CHAN_6 Selects channel 6
0x7 CHAN_7 Selects channel 7
0x8 CHAN_8 Selects channel 8
0x9 CHAN_9 Selects channel 9
0xA CHAN_10 Selects channel 10
0xB CHAN_11 Selects channel 11
0xC CHAN_12 Selects channel 12
0xD CHAN_13 Selects channel 13
0xE CHAN_14 Selects channel 14
0xF CHAN_15 Selects channel 15
0x10 CHAN_16 Selects channel 16
0x11 CHAN_17 Selects channel 17
0x12 CHAN_18 Selects channel 18
0x13 CHAN_19 Selects channel 19
0x14 CHAN_20 Selects channel 20
0x15 CHAN_21 Selects channel 21
0x16 CHAN_22 Selects channel 22
0x17 CHAN_23 Selects channel 23
0x18 CHAN_24 Selects channel 24
0x19 CHAN_25 Selects channel 25
0x1A CHAN_26 Selects channel 26
0x1B CHAN_27 Selects channel 27
0x1C CHAN_28 Selects channel 28
0x1D CHAN_29 Selects channel 29
0x1E CHAN_30 Selects channel 30
0x1F CHAN_31 Selects channel 31
RW 0b0 0000

TOP:ADC:MEMRES__0-MEMRES__3

Address Offset 0x0000 1280 - 0x0000 128C
Physical Address 0x4005 1280 - 0x4005 128C Instance 0x4005 1280 - 0x4005 128C
Description Memory Result Register
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA MEMRES result register.
If DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.		 RW 0x0000

TOP:ADC:STATUS

Address Offset 0x0000 1340
Physical Address 0x4005 1340 Instance 0x4005 1340
Description Status Register
Type RO
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 ASCACT ASC active
Value ENUM Name Description
0x0 IDLE Idle or done
0x1 ACTIVE ASC active
RO 0
1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
0 BUSY Busy. This bit indicates that an active ADC sample or conversion operation is in progress.
Value ENUM Name Description
0x0 IDLE No ADC sampling or conversion in progress.
0x1 ACTIVE ADC sampling or conversion is in progress.
RO 0

TOP:ADC:TEST0

Address Offset 0x0000 1E00
Physical Address 0x4005 1E00 Instance 0x4005 1E00
Description Test 0 register. This is used to select ADC internal analog signals on ATBBUF and ATBUNBUF.
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
30 ATB_BUFEN ATBBUF enable.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0
29 ATB_UNBUFEN ATBUNBUF enable.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0
28:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
12:8 ATB_MUX_UNBUFSEL This is used to select analog signal on ATBUNBUF. The undefined values are reserved and should not be used.
Value ENUM Name Description
0x1 VAL1 Ground
0x2 VAL2 Ground
0x4 VAL4 Ground
0x8 VAL8 Negative voltage reference to CDAC
0x10 VAL16 Ground
RW 0b0 0000
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4:0 ATB_MUX_BUFSEL This is used to select analog signal on ATBBUF. The undefined values are reserved and should not be used.
Value ENUM Name Description
0x1 VAL1 Ground
0x2 VAL2 Ground
0x4 VAL4 Ground
0x8 VAL8 Positive voltage reference to CDAC
0x10 VAL16 Ground
RW 0b0 0000

TOP:ADC:TEST1

Address Offset 0x0000 1E04
Physical Address 0x4005 1E04 Instance 0x4005 1E04
Description DTB MUX Selection
Type RW
Bits Field Name Description Type Reset
31:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
4:0 DTB_MUX_SEL DTB Mux Sel
ull_dft_dtb_usc_ulpadchp_muxsel<0x0> : ADC 16 bit data
ull_dft_dtb_usc_ulpadchp_muxsel<0x1> :
DTB0: ADC CLK DIV2
DTB1 - 9 : See implementation document for detail signal name.		 RW 0b0 0000

TOP:ADC:TEST2

Address Offset 0x0000 1E08
Physical Address 0x4005 1E08 Instance 0x4005 1E08
Description ATB Ch sel as ADC input
MUX Test mode sel, ATB REF and CAP OSVT enable
Type RW
Bits Field Name Description Type Reset
31 CDAC_OVST_EN ADC P_CDAC CAP OVST Enable Control Signal
ull_usc_ulpadchp_dft_i<31>:1 -> ADC CDAC CAP OVST Enable Control Signal		 RW 0
30:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
24 LATCH_TRIM_EN Latch trim enable. RW 0
23:21 RESERVED21 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
20 COMP_GAIN_TRIM Resistor Trim Enable Control Signal
ull_usc_ulpadchp_dft_i<30>:1 -> Resistor Trim Enable Control Signal		 RW 0
19:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
8 MUX_TEST_SEL ADC Input MUX test mode selection:
ull_usc_ulpachp_mux_testmode_i<1:0>: 0x01 : Selected Even ch short with ATBBUF CH sel
ull_usc_ulpachp_mux_testmode_i<1:0>: 0x10 : Selected Odd ch short with ATBUnBUFCh sel		 RW 0
7:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00

TOP:ADC:TEST3

Address Offset 0x0000 1E0C
Physical Address 0x4005 1E0C Instance 0x4005 1E0C
Description ADC CAL Accumulation Register
Type RW
Bits Field Name Description Type Reset
31:0 CAL_ACUML Accumulation of # samples during Calibration step RW 0x0000 0000

TOP:ADC:TEST4

Address Offset 0x0000 1E10
Physical Address 0x4005 1E10 Instance 0x4005 1E10
Description CAL Control register: Average Sample count, Step number, Recal En and Debug option to override ull_usc_ulpadchp_dft_i<26:0>.
Type RW
Bits Field Name Description Type Reset
31 HW_STEP_SEL_DIS By Enabling this bit, DLC written value overwritten of ull_usc_ulpadchp_dft_i<26:0> from TEST7 regsiter.
This is for debug.		 RW 0
30:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
24 CAL_MODE_EN ADC CDAC Calibration mode enable RW 0
23:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
21:16 CAL_STEP_SEL ADC CAL STEP SELECTION RW 0b00 0000
15:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000

TOP:ADC:TEST5

Address Offset 0x0000 1E14
Physical Address 0x4005 1E14 Instance 0x4005 1E14
Description This regsiter updated ull_usc_ulpadchp_dft_i[26:0] value if Test 5: HW_STEP_SEL_DIS bit enable
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 CAL_CAP_CTL This regsiter updated ull_usc_ulpadchp_dft_i[26:0] value if Test 5: HW_STEP_SEL_DIS bit enabled
ull_usc_ulpadchp_dft_i[26:0]		 RW 0b00 0000 0000

TOP:ADC:TEST6

Address Offset 0x0000 1E18
Physical Address 0x4005 1E18 Instance 0x4005 1E18
Description REFBUF ATB selection. This register is used to select the REFBUF signals on ATB.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 ATBSEL ATB selection. The undefined values are reserved and should not be used.
Value ENUM Name Description
0x0 VAL0 Both ATEST0 and ATEST1 switches are open
0x1 VAL1 REFBUF output (ATEST0/BUF path)
0x2 VAL2 1st stage output (ATEST0/BUF path)
0x4 VAL4 Resistor ladder feedback (ATEST0/BUF path)
0x8 VAL8 1st stage source (ATEST1/UNBUF path)
RW 0x0

TOP:ADC:DEBUG1

Address Offset 0x0000 1E20
Physical Address 0x4005 1E20 Instance 0x4005 1E20
Description COMP CTL Debug register
Type RW
Bits Field Name Description Type Reset
31:0 CTRL COMP Debug signals control
ull_usc_ulpadchp_ctrl_comp_i[31]: Enable the use of external value for comaparor gain and IB settings		 RW 0x0080 1000

TOP:ADC:DEBUG2

Address Offset 0x0000 1E24
Physical Address 0x4005 1E24 Instance 0x4005 1E24
Description OSC, LATCH_OS, VTOI Debug CTL resgister
Type RW
Bits Field Name Description Type Reset
31:30 RESERVED30 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
29:28 VTOI_CTRL VTOI Debug Signals control
ull_usc_ulpadchp_ctrl_vtoi_i[3:0]		 RW 0b00
27:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
24 VTOI_TESTMODE_EN VTOI TETSMODE Enable RW 0
23:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000

TOP:ADC:DEBUG3

Address Offset 0x0000 1E28
Physical Address 0x4005 1E28 Instance 0x4005 1E28
Description Boost, DCLK Sel, Int coex dirty and Dec disbale debug control regsiter
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5 DEC1_DIS DEC1 Disbale control signal RW 0
4 DEC0_DIS DEC0 Disbale control signal RW 0
3:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
0 BOOST_ENZ BOOST ENZ RW 0

TOP:ADC:DEBUG4

Address Offset 0x0000 1E2C
Physical Address 0x4005 1E2C Instance 0x4005 1E2C
Description ADC MSIP Control signal for Debug: adc_ctrl<31:0>
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 ADC_CTRL0 ADC MSIP Control signal for Debug: adc_ctrl<15:0> RW 0x0000


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