Instance: SYSTIM
Component: SYSTIM
Base address: 0x40022000
SVT System Timer Module
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x9443 1010 |
0x0000 0000 |
0x4002 2000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x4002 2044 |
|
RO |
32 |
0x0000 0000 |
0x0000 0048 |
0x4002 2048 |
|
RO |
32 |
0x0000 0000 |
0x0000 004C |
0x4002 204C |
|
WO |
32 |
0x0000 0000 |
0x0000 0050 |
0x4002 2050 |
|
WO |
32 |
0x0000 0000 |
0x0000 0054 |
0x4002 2054 |
|
WO |
32 |
0x0000 0000 |
0x0000 0058 |
0x4002 2058 |
|
WO |
32 |
0x0000 0000 |
0x0000 005C |
0x4002 205C |
|
RW |
32 |
0x0000 0000 |
0x0000 0060 |
0x4002 2060 |
|
RO |
32 |
0x0000 0000 |
0x0000 0100 |
0x4002 2100 |
|
RO |
32 |
0x0000 0000 |
0x0000 0104 |
0x4002 2104 |
|
RO |
32 |
0x0000 0000 |
0x0000 0108 |
0x4002 2108 |
|
RW |
32 |
0x0000 0000 |
0x0000 010C |
0x4002 210C |
|
RW |
32 |
0x0000 0000 |
0x0000 0110 |
0x4002 2110 |
|
RW |
32 |
0x0000 0000 |
0x0000 0114 |
0x4002 2114 |
|
RW |
32 |
0x0000 0000 |
0x0000 0118 |
0x4002 2118 |
|
RW |
32 |
0x0000 0000 |
0x0000 011C |
0x4002 211C |
|
RW |
32 |
0x0000 0000 |
0x0000 0120 |
0x4002 2120 |
|
RW |
32 |
0x0000 0000 |
0x0000 0124 |
0x4002 2124 |
|
RW |
32 |
0x0000 0000 |
0x0000 0128 |
0x4002 2128 |
|
RW |
32 |
0x0000 0000 |
0x0000 012C |
0x4002 212C |
|
RW |
32 |
0x0000 0000 |
0x0000 0130 |
0x4002 2130 |
|
RW |
32 |
0x0000 0000 |
0x0000 0134 |
0x4002 2134 |
|
RW |
32 |
0x0000 0010 |
0x0000 0140 |
0x4002 2140 |
|
RW |
32 |
0x0000 0000 |
0x0000 0144 |
0x4002 2144 |
|
RW |
32 |
0x0000 0000 |
0x0000 0148 |
0x4002 2148 |
|
RW |
32 |
0x0000 0000 |
0x0000 014C |
0x4002 214C |
|
RW |
32 |
0x0000 0000 |
0x0000 0150 |
0x4002 2150 |
|
RW |
32 |
0x0000 0000 |
0x0000 0154 |
0x4002 2154 |
|
RW |
32 |
0x0000 0000 |
0x0000 0158 |
0x4002 2158 |
|
RW |
32 |
0x0000 0000 |
0x0000 015C |
0x4002 215C |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4002 2000 | Instance | 0x4002 2000 |
Description | Description. This register identifies the peripheral and its exact version. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | MODID | Module identifier used to uniquely identify this IP. | RO | 0x9443 | ||
15:12 | STDIPOFF | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) |
RO | 0x1 | ||
11:8 | INSTIDX | IP Instance ID number. If multiple instances of IP exists in SOC, this field can identify the instance number 0-15 | RO | 0x0 | ||
7:4 | MAJREV | Major revision of IP 0-15 | RO | 0x1 | ||
3:0 | MINREV | Minor revision of IP 0-15. | RO | 0x0 |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x4002 2044 | Instance | 0x4002 2044 |
Description | Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
5 | OVFL | Systimer counter overflow event interrupt mask.
|
RW | 0 | |||||||||||
4 | EV4 | Systimer channel 4 event interrupt mask.
|
RW | 0 | |||||||||||
3 | EV3 | Systimer channel 3 event interrupt mask.
|
RW | 0 | |||||||||||
2 | EV2 | Systimer channel 2 event interrupt mask.
|
RW | 0 | |||||||||||
1 | EV1 | Systimer channel 1 event interrupt mask.
|
RW | 0 | |||||||||||
0 | EV0 | Systimer channel 0 event interrupt mask.
|
RW | 0 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4002 2048 | Instance | 0x4002 2048 |
Description | Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
5 | OVFL | Raw interrupt status for Systimer counter overflow event. This bit is set to 1 when an event is received on SysTimer Overflow occurs.
|
RO | 0 | |||||||||||
4 | EV4 | Raw interrupt status for channel 4 event. This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 4.
|
RO | 0 | |||||||||||
3 | EV3 | Raw interrupt status for channel 3 event. This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 3.
|
RO | 0 | |||||||||||
2 | EV2 | Raw interrupt status for channel 2 Event. This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 2.
|
RO | 0 | |||||||||||
1 | EV1 | Raw interrupt status for channel 1 event. This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 1.
|
RO | 0 | |||||||||||
0 | EV0 | Raw interrupt status for channel 0 event. This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 0.
|
RO | 0 |
Address Offset | 0x0000 004C | ||
Physical Address | 0x4002 204C | Instance | 0x4002 204C |
Description | Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
5 | OVFL | Mask Interrupt status for Systimer counter overflow Event in MIS register.
|
RO | 0 | |||||||||||
4 | EV4 | Mask interrupt status for channel 4 event.
|
RO | 0 | |||||||||||
3 | EV3 | Mask interrupt status for channel 3 event.
|
RO | 0 | |||||||||||
2 | EV2 | Mask interrupt status for channel 2 event.
|
RO | 0 | |||||||||||
1 | EV1 | Mask interrupt status for channel 1 event.
|
RO | 0 | |||||||||||
0 | EV0 | Mask interrupt status for channel 0 event.
|
RO | 0 |
Address Offset | 0x0000 0050 | ||
Physical Address | 0x4002 2050 | Instance | 0x4002 2050 |
Description | Interrupt set. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
5 | OVFL | Sets Systimer counter overflow interrupt.
|
WO | 0 | |||||||||||
4 | EV4 | Sets channel 4 interrupt.
|
WO | 0 | |||||||||||
3 | EV3 | Sets channel 3 interrupt.
|
WO | 0 | |||||||||||
2 | EV2 | Sets channel 2 interrupt.
|
WO | 0 | |||||||||||
1 | EV1 | Sets channel 1 interrupt.
|
WO | 0 | |||||||||||
0 | EV0 | Sets channel 0 interrupt.
|
WO | 0 |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x4002 2054 | Instance | 0x4002 2054 |
Description | Interrupt clear. 'This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
5 | OVFL | Clears Systimer counter overflow interrupt.
|
WO | 0 | |||||||||||
4 | EV4 | Clears channel 4 interrupt.
|
WO | 0 | |||||||||||
3 | EV3 | Clears channel 3 interrupt.
|
WO | 0 | |||||||||||
2 | EV2 | Clears channel 2 interrupt.
|
WO | 0 | |||||||||||
1 | EV1 | Clears channel 1 interrupt.
|
WO | 0 | |||||||||||
0 | EV0 | Clears channel 0 interrupt.
|
WO | 0 |
Address Offset | 0x0000 0058 | ||
Physical Address | 0x4002 2058 | Instance | 0x4002 2058 |
Description | Interrupt mask set. Writing a 1 to a bit in this register will set the corresponding IMASK bit. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
5 | OVFL | Sets Timer Overflow Event Interrupt Mask.
|
WO | 0 | |||||||||||
4 | EV4 | Sets channel4 Event Interrupt mask
|
WO | 0 | |||||||||||
3 | EV3 | Sets channel3 Event Interrupt mask
|
WO | 0 | |||||||||||
2 | EV2 | Sets channel2 Event Interrupt mask
|
WO | 0 | |||||||||||
1 | EV1 | Sets channel1 Event Interrupt mask
|
WO | 0 | |||||||||||
0 | EV0 | Sets channel0 Event Interrupt mask
|
WO | 0 |
Address Offset | 0x0000 005C | ||
Physical Address | 0x4002 205C | Instance | 0x4002 205C |
Description | Interrupt mask clear. Writing a 1 to a bit in this register will clear the corresponding IMASK bit. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
5 | OVFL | Clears Timer Overflow Event Interrupt Mask.
|
WO | 0 | |||||||||||
4 | EV4 | Clears channel4 Event Interrupt Mask.
|
WO | 0 | |||||||||||
3 | EV3 | Clears channel3 Event Interrupt Mask.
|
WO | 0 | |||||||||||
2 | EV2 | Clears channel2 Event Interrupt Mask.
|
WO | 0 | |||||||||||
1 | EV1 | Clears channel1 Event Interrupt Mask.
|
WO | 0 | |||||||||||
0 | EV0 | Clears channel0 Event Interrupt Mask.
|
WO | 0 |
Address Offset | 0x0000 0060 | ||
Physical Address | 0x4002 2060 | Instance | 0x4002 2060 |
Description | Emulation control. This register controls the behavior of the IP related to core halted input. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | HALT | Halt control.
|
RW | 0 |
Address Offset | 0x0000 0100 | ||
Physical Address | 0x4002 2100 | Instance | 0x4002 2100 |
Description | Systimer Counter Value - 250ns resolution. This 32-bit value reads out bits [31:0] of the systimer counter. The counter is 34-bit and runs on CLKSVT/12. It maintains a resolution of 250ns with a range of about 17.9m. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | 32-bit counter value [31:0]. This will provide a 250ns resolution and a range of 17.9m. | RO | 0x0000 0000 |
Address Offset | 0x0000 0104 | ||
Physical Address | 0x4002 2104 | Instance | 0x4002 2104 |
Description | Systimer Counter Value - 1μs resolution This 32-bit value reads out bits[33:2] of the systimer counter. The counter is 34-bit and runs on CLKSVT/12. It maintains a resolution of 1us with a range of about 1 h 11m. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | 32-bit counter value [33:2]. This will provide a resolution of 1us and a range of 1hr and 11m. | RO | 0x0000 0000 |
Address Offset | 0x0000 0108 | ||
Physical Address | 0x4002 2108 | Instance | 0x4002 2108 |
Description | Systimer's channel Output Event Values | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | |||||||||||
4 | OUT4 | Output Value of channel 4.
|
RW | 0 | |||||||||||
3 | OUT3 | Output Value of channel 3.
|
RW | 0 | |||||||||||
2 | OUT2 | Output Value of channel 2.
|
RW | 0 | |||||||||||
1 | OUT1 | Output Value of channel 1.
|
RW | 0 | |||||||||||
0 | OUT0 | Output Value of channel 0.
|
RW | 0 |
Address Offset | 0x0000 010C | ||
Physical Address | 0x4002 210C | Instance | 0x4002 210C |
Description | Systimer channel 0 configuration. This channel has configurability for 250ns and 1us based capture and compare operations. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||||||||||||||
4 | RES | This bit decides the RESOLUTION of the channel that will be used.
|
RW | 0 | ||||||||||||||
3 | REARM | When Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
|
RW | 0 | ||||||||||||||
2:1 | INP | Decides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function.
|
RW | 0b00 | ||||||||||||||
0 | MODE | Decides the channel mode.
|
RW | 0 |
Address Offset | 0x0000 0110 | ||
Physical Address | 0x4002 2110 | Instance | 0x4002 2110 |
Description | Systimer channel 1 configuration. This channel works in 1us based capture and compare operations. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||||||||||||||
3 | REARM | When Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
|
RW | 0 | ||||||||||||||
2:1 | INP | Decides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function
|
RW | 0b00 | ||||||||||||||
0 | MODE | Decides the channel mode.
|
RW | 0 |
Address Offset | 0x0000 0114 | ||
Physical Address | 0x4002 2114 | Instance | 0x4002 2114 |
Description | Systimer channel 2 configuration. This channel works in 250ns based capture and compare operations. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||||||||||||||
3 | REARM | When Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
|
RW | 0 | ||||||||||||||
2:1 | INP | Decides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function
|
RW | 0b00 | ||||||||||||||
0 | MODE | Decides the channel mode.
|
RW | 0 |
Address Offset | 0x0000 0118 | ||
Physical Address | 0x4002 2118 | Instance | 0x4002 2118 |
Description | Systimer channel 3 configuration. This channel works in 250ns based capture and compare operations. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||||||||||||||
3 | REARM | When Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
|
RW | 0 | ||||||||||||||
2:1 | INP | Decides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function
|
RW | 0b00 | ||||||||||||||
0 | MODE | Decides the channel mode.
|
RW | 0 |
Address Offset | 0x0000 011C | ||
Physical Address | 0x4002 211C | Instance | 0x4002 211C |
Description | Systimer channel 4 configuration. This channel works in 250ns based capture and compare operations. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||||||||||||||
3 | REARM | When Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
|
RW | 0 | ||||||||||||||
2:1 | INP | Decides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function
|
RW | 0b00 | ||||||||||||||
0 | MODE | Decides the channel mode.
|
RW | 0 |
Address Offset | 0x0000 0120 | ||
Physical Address | 0x4002 2120 | Instance | 0x4002 2120 |
Description | System Timer channel 0 Capture/Compare register. This register when written with any compare value will arm the channel to work in compare mode. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | Capture/compare value | RW | 0x0000 0000 |
Address Offset | 0x0000 0124 | ||
Physical Address | 0x4002 2124 | Instance | 0x4002 2124 |
Description | System Timer channel 1 Capture/Compare register. This register when written with any compare value will arm the channel to work in compare mode. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | Capture/compare value | RW | 0x0000 0000 |
Address Offset | 0x0000 0128 | ||
Physical Address | 0x4002 2128 | Instance | 0x4002 2128 |
Description | System Timer channel 2 Capture/Compare register. This register when written with any compare value will arm the channel to work in compare mode. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | Capture/compare value | RW | 0x0000 0000 |
Address Offset | 0x0000 012C | ||
Physical Address | 0x4002 212C | Instance | 0x4002 212C |
Description | System Timer channel 3 Capture/Compare register. This register when written with any compare value will arm the channel to work in compare mode. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | Capture/compare value | RW | 0x0000 0000 |
Address Offset | 0x0000 0130 | ||
Physical Address | 0x4002 2130 | Instance | 0x4002 2130 |
Description | System Timer channel 4 Capture/Compare register. This register when written with any compare value will arm the channel to work in compare mode. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | Capture/compare value | RW | 0x0000 0000 |
Address Offset | 0x0000 0134 | ||
Physical Address | 0x4002 2134 | Instance | 0x4002 2134 |
Description | Systimer's Time bit. This Register will be used to specify which TIME bit is required by LGPT to be forwarded from SYSTIMER. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | VAL | The corresponding bit will have value '1' rest should be '0'. If more than one bit is asserted, output is "or" of all the bits.
|
RW | 0x0000 |
Address Offset | 0x0000 0140 | ||
Physical Address | 0x4002 2140 | Instance | 0x4002 2140 |
Description | Systimer status. This register can be used to read the running status of the timer and to resync the Systimer with RTC. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | |||||||||||
4 | SYNCUP | This bit indicates sync status of Systimer with RTC. The bitfield has a reset value of '1', which gets cleared to '0' after the Systimer synchronizes with RTC on the first LFTICK edge. A write to this bit resynchronizes the Systimer with RTC on the next LFTICK edge. A read value of '1' indicates the synchronization is ongoing and a read of '0' indicates the synchronization is done. | RW | 1 | |||||||||||
3:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
0 | VAL | This bit indicates if the system time is initialized and running.
|
RO | 0 |
Address Offset | 0x0000 0144 | ||
Physical Address | 0x4002 2144 | Instance | 0x4002 2144 |
Description | ARMSET Reading this register gives out the status of the 5 channels. Channel state UNARMED returns 0. Channel state CAPTURE or COMPARE returns 1. A write to ARMSET has for each channel the following effect - If ARMSTA[x]==0 -> no effect If ARMSTA[x]==1 and channel x is in CAPTURE state then no effect on the channel Else, set channel in COMPARE mode using existing CHxVAL value |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | |||||||||||
4 | CH4 | Arming channel 4 for either compare or capture operation.
|
RW | 0 | |||||||||||
3 | CH3 | Arming channel 3 for either compare or capture operation.
|
RW | 0 | |||||||||||
2 | CH2 | Arming channel 2 for either compare or capture operation.
|
RW | 0 | |||||||||||
1 | CH1 | Arming channel 1 for either compare or capture operation.
|
RW | 0 | |||||||||||
0 | CH0 | Arming channel 0 for either compare or capture operation.
|
RW | 0 |
Address Offset | 0x0000 0148 | ||
Physical Address | 0x4002 2148 | Instance | 0x4002 2148 |
Description | ARMCLR Read of this register gives out the status of the 5 channels . Channel state UNARMED returns 0. Channel state CAPTURE or COMPARE returns 1. A write to ARMCLR has for each channel the following effect - If ARMCLR[x]==0 -> no effect. Else, set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | |||||||||||
4 | CH4 | Disarming channel 4
|
RW | 0 | |||||||||||
3 | CH3 | Disarming channel 3
|
RW | 0 | |||||||||||
2 | CH2 | Disarming channel 2
|
RW | 0 | |||||||||||
1 | CH1 | Disarming channel 1
|
RW | 0 | |||||||||||
0 | CH0 | Disarming channel 0
|
RW | 0 |
Address Offset | 0x0000 014C | ||
Physical Address | 0x4002 214C | Instance | 0x4002 214C |
Description | Save/restore alias register for channel 0. A read to this register behaves exactly as a read to CH0CC. Write to CH0CCSR sets CH0CC.VAL value of register without affecting channel state or configuration |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | Capture/compare value | RW | 0x0000 0000 |
Address Offset | 0x0000 0150 | ||
Physical Address | 0x4002 2150 | Instance | 0x4002 2150 |
Description | Save/restore alias registers channel 1. A read to CH1CCSR behaves exactly as a read to CH1VAL. Write to this register sets CH1CC.VAL without affecting channel state or configuration. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | Capture/compare value | RW | 0x0000 0000 |
Address Offset | 0x0000 0154 | ||
Physical Address | 0x4002 2154 | Instance | 0x4002 2154 |
Description | Save/restore alias registers channel 2. A read to CH2CCSR behaves exactly as a read to CH2CC Write to CH2CCSR sets CH2CC.VAL value of register without affecting channel state or configuration |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | Capture/compare value | RW | 0x0000 0000 |
Address Offset | 0x0000 0158 | ||
Physical Address | 0x4002 2158 | Instance | 0x4002 2158 |
Description | Save/restore alias registers channel 3. A read to CH3CCSR behaves exactly as a read to CH3CC Write to CH3CCSR sets CH3CC.VAL value of register without affecting channel state or configuration. |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | Capture/compare value | RW | 0x0000 0000 |
Address Offset | 0x0000 015C | ||
Physical Address | 0x4002 215C | Instance | 0x4002 215C |
Description | Save/restore alias registers channel 4. A read to CH4CCSR behaves exactly as a read to CH4CC Write to CH4CCSR sets CH4CC.VAL value of register without affecting channel state or configuration. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | Capture/compare value | RW | 0x0000 0000 |
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