SYS0

Instance: SYS0
Component: SYS0
Base address: 0x40004000


This is top module of SYS0 for LOKI

TOP:SYS0 Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

DESC

RO

32

0x6B4E 0010

0x0000 0000

0x4000 4000

DESCEX

RO

32

0x0000 0129

0x0000 0004

0x4000 4004

GLOCK

WO

32

0x0000 0000

0x0000 0008

0x4000 4008

MUNLOCK

WO

32

0x0000 0000

0x0000 000C

0x4000 400C

STATUS

RO

32

0xC000 0000

0x0000 0010

0x4000 4010

ATESTCFG

RW

32

0x0000 000F

0x0000 0100

0x4000 4100

I2VCFG

RW

32

0x0000 0000

0x0000 0104

0x4000 4104

TSENSCFG

RW

32

0x0000 0000

0x0000 0108

0x4000 4108

LPCMPCFG

RW

32

0x0000 0000

0x0000 010C

0x4000 410C

VGMCFG

RW

32

0x0000 0000

0x0000 0110

0x4000 4110

VGMTRIMDBG

RW

32

0x0000 0000

0x0000 0114

0x4000 4114

TSDTEST

WO

32

0x0000 0000

0x0000 0120

0x4000 4120

DEVICEID

RO

32

0x0BB9 802F

0x0000 03FC

0x4000 43FC

TIMMUTE0

RW

32

0x0000 0000

0x0000 0400

0x4000 4400

TIMMUTE1

RW

32

0x0000 0000

0x0000 0404

0x4000 4404

TIMMUTE2

RW

32

0x7FF8 0000

0x0000 0408

0x4000 4408

TIMMUTE3

WO

32

0x0000 0000

0x0000 040C

0x4000 440C

PARTID

RW

32

0x0000 0000

0x0000 07F8

0x4000 47F8

LIFECYC

RW

32

0x0000 0000

0x0000 07FC

0x4000 47FC

TMUTE0

RW

32

0x0000 0000

0x0000 0800

0x4000 4800

TMUTE1

RW

32

0x0000 0000

0x0000 0804

0x4000 4804

TMUTE2

RW

32

0x0080 0000

0x0000 0808

0x4000 4808

TMUTE3

RW

32

0x0000 0000

0x0000 080C

0x4000 480C

TMUTE4

RW

32

0xB02E 603F

0x0000 0810

0x4000 4810

TMUTE5

RW

32

0x0000 0000

0x0000 0814

0x4000 4814

TOP:SYS0 Register Descriptions

TOP:SYS0:DESC

Address Offset 0x0000 0000
Physical Address 0x4000 4000 Instance 0x4000 4000
Description This register identifies the peripheral
Type RO
Bits Field Name Description Type Reset
31:16 MODID Module identification contains a unique peripheral identification number. RO 0x6B4E
15:12 STDIPOFF Standard IP registers offset. Value 0 indicates Standard IP registers are not present. Any other value between 1 to 15 indicates standard IP registers start from address offset 64 * STDIPOFF from base address. RO 0x0
11:8 INSTIDX Instance Index within the device. This will be a parameter to the RTL for modules that can have multiple instances. RO 0x0
7:4 MAJREV Major revision of the IP RO 0x1
3:0 MINREV Minor revision of the IP RO 0x0

TOP:SYS0:DESCEX

Address Offset 0x0000 0004
Physical Address 0x4000 4004 Instance 0x4000 4004
Description This register identifies the configuration of the peripheral
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED20 Reserved RO 0x0000
15:0 TBITS Total number of trim bits RO 0x0129

TOP:SYS0:GLOCK

Address Offset 0x0000 0008
Physical Address 0x4000 4008 Instance 0x4000 4008
Description Global Lock Register. Locks both registers in both mutable and immutable sections
Type WO
Bits Field Name Description Type Reset
31:1 RESERVED1 RESERVED RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 LOCK When LOCK is set, write access to registers in mutable and immutable section are not allowed. Registers in mutable section can be temporarily unlocked by writing the KEY to UNLOCK.KEY
Value ENUM Name Description
0x0 NOEFFECT No effect
0x1 SET Global Lock is set
WO 0

TOP:SYS0:MUNLOCK

Address Offset 0x0000 000C
Physical Address 0x4000 400C Instance 0x4000 400C
Description Unlocks registers in mutable section
Type WO
Bits Field Name Description Type Reset
31:0 KEY Write the unlock key 0xC5AF_6927 to temporarily unlock registers in mutable section. The lock is set automatically if no write accesses, to the mutable section, is detected for consecutive 32 CLKULL (24MHz) clock cycles. Writing any value other that the unlock key will immediately lock the mutable register space for write access. WO 0x0000 0000

TOP:SYS0:STATUS

Address Offset 0x0000 0010
Physical Address 0x4000 4010 Instance 0x4000 4010
Description Lock Status Register
Type RO
Bits Field Name Description Type Reset
31 VGMTIE Internal VGM Enable Signal RO 1
30 EMTIE Internal EM Sensor Enable Signal RO 1
29:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
1 MLOCK Lock status of registers in mutable section.
Value ENUM Name Description
0x0 UNLOCKED Registers in the mutable section are not locked, and are writable
0x1 LOCKED Registers in the mutable section are locked for write
RO 0
0 GLOCK Status of Global lock
Value ENUM Name Description
0x0 UNLOCKED Unlocked
0x1 LOCKED Locked
RO 0

TOP:SYS0:ATESTCFG

Address Offset 0x0000 0100
Physical Address 0x4000 4100 Instance 0x4000 4100
Description This register is used to configure analog switches in ATEST module
Type RW
Bits Field Name Description Type Reset
31:24 KEY Key must be written with value 0x5A for successful write to ATESTCFG and to unlock register state.
Write with any value other than 0x5A to KEY will be ignored and register content is not updated.
It is recommended to write this register with incorrect KEY to lock back register state after necessary ATESTCFG updates are done.
Read value of KEY is 0x0.		 WO 0x00
23:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000
8 VSEL Selects supply for ATEST switches.
Value ENUM Name Description
0x0 VDDBST selects VDDBOOST
0x1 VDDA selects VDDA
RW 0
7 VA2VA1 Enables isolation switch between VA_ATEST_A1 and VA_PAD_A1.
Value ENUM Name Description
0x0 OPEN Switch is open
0x1 CLOSE Switch is closed
RW 0
6 VA2VA0 Enables isolation switch between VA_ATEST_A0 and VA_PAD_A0.
Value ENUM Name Description
0x0 OPEN Switch is open
0x1 CLOSE Switch is closed
RW 0
5 VR2VA1 Enables isolation switch between VR_ATEST_A1 and VA_ATEST_A1.
Value ENUM Name Description
0x0 OPEN Switch is open
0x1 CLOSE Switch is closed
RW 0
4 VR2VA0 Enables isolation switch between VR_ATEST_A0 and VA_ATEST_A0.
Value ENUM Name Description
0x0 OPEN Switch is open
0x1 CLOSE Switch is closed
RW 0
3 SHTVA1 Shorts VA_ATEST_A1 to ground.
Value ENUM Name Description
0x0 OPEN Switch is open
0x1 CLOSE Switch is closed
RW 1
2 SHTVA0 Shorts VA_ATEST_A0 to ground.
Value ENUM Name Description
0x0 OPEN Switch is open
0x1 CLOSE Switch is closed
RW 1
1 SHTVR1 Shorts VR_ATEST_A1 to ground.
Value ENUM Name Description
0x0 OPEN Switch is open
0x1 CLOSE Switch is closed
RW 1
0 SHTVR0 Shorts VR_ATEST_A0 to ground.
Value ENUM Name Description
0x0 OPEN Switch is open
0x1 CLOSE Switch is closed
RW 1

TOP:SYS0:I2VCFG

Address Offset 0x0000 0104
Physical Address 0x4000 4104 Instance 0x4000 4104
Description This register is used to configure I2V (current to voltage converter) module.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 RESERVED RO 0x000 0000
3:1 RESVAL Enables I2V module and selects resistor value.
Value ENUM Name Description
0x0 OFF I2V module is disabled
0x1 KO2 resistor value is 2kOhm
0x2 KO10 resistor value is 10kOhm
0x3 KO20 resistor value is 20kOhm
0x4 KO50 resistor value is 50kOhm
0x5 KO100 resistor value is 100kOhm
0x6 MO1 resistor value is 1MOhm
0x7 OFF_RES I2V module is disabled
RW 0b000
0 SEL Selects ATEST_A0 between VR and VA domains and forwards to ATEST.
Value ENUM Name Description
0x0 VR_ATEST_A0 selects VR_ATEST_A0
0x1 VA_ATEST_A0 selects VA_ATEST_A0
RW 0

TOP:SYS0:TSENSCFG

Address Offset 0x0000 0108
Physical Address 0x4000 4108 Instance 0x4000 4108
Description This register is used to configure temperature sensor module.
Type RW
Bits Field Name Description Type Reset
31:26 SPARE1 Spare bits
Value ENUM Name Description
0x0 MIN minimum value
0x3F MAX maximum value
RW 0b00 0000
25:12 RESERVED12 RESERVED RO 0b00 0000 0000 0000
11 TSENS2EN This is the enable bit for the second temperature sensor in AUX.
Value ENUM Name Description
0x0 DIS Second temperature sensor is disabled.
0x1 EN Second temperature sensor is enabled.
RW 0
10:8 SPARE Spare bits
Value ENUM Name Description
0x0 MIN minimum value
0xF MAX maximum value
RW 0b000
7:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
1:0 SEL Used to enable and configure temperature sensor module. Setting the value to 0x3 will disable the temperature sensor.
Value ENUM Name Description
0x0 DISABLE Temperature sensor is disabled
0x1 VALUE 20uA current is injected on VR_ATEST_A0 and voltage measured on VR_ATEST_A1
0x2 GND 20uA current is injected on VR_ATEST_A0 and ground measured on VR_ATEST_A1
RW 0b00

TOP:SYS0:LPCMPCFG

Address Offset 0x0000 010C
Physical Address 0x4000 410C Instance 0x4000 410C
Description This register is used to configure and check the status of low-power comparator (LPCOMP) module.
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 RESERVED RO 0
30 HYSPOL Spare bit for LPCOMP RW 0
29:28 ATESTMUX Used to configure ATEST mux in comparator module and provides chosen output on VA_ATEST_A0.
Note: This bit field is write-protected using global lock indicator on production device.
Value ENUM Name Description
0x0 OFF ATEST mux is off
0x1 COMPOUT Selects comparator output
0x2 COMP_VIN_NEG Selects voltage divider output
0x3 IBIASOUT Selects bias current output
RW 0b00
27:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
24 EVTIFG Event flag. The event flag is set when the comparator output transition is qualified based on the edge polarity configuration in EDGCFG.
Value ENUM Name Description
0x0 CLR clear
0x1 SET set
RW 0
23:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
21 COUTEN Enables LPCOMP output on device pin.
Value ENUM Name Description
0x0 DISABLED Disabled
0x1 ENABLED Enabled
RW 0
20 COUT LPCOMP output status. This bit captures the value LPCOMP raw output.
Value ENUM Name Description
0x0 LOW Output is low
0x1 HIGH Output is high
RO 0
19 RESERVED19 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
18 WUENSB Enables lpcmpcfg output to wake device from standby.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0
17 EVTEN Enables event generation. Comparator module will produce event on ULL event fabric when EVTIFG is set.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0
16 EDGCFG Selects positive edge or negative edge detection on comparator output to set the event flag
Value ENUM Name Description
0x0 RISE Rise edge detection
0x1 FALL Fall edge detection
RW 0
15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
14:12 NSEL Negative input selection. Setting values 0x5-0x7 will open all the switches.
Value ENUM Name Description
0x0 OPEN all switches are open
0x1 VA_PAD_A2 selects VA_PAD_A2
0x2 VA_PAD_A3 selects VA_PAD_A3
0x3 VDDA selects VDDA
0x4 VDDD selects VDDD
RW 0b000
11:8 PSEL Positive input selection. Setting values 0x9-0xF will open all the switches.
Value ENUM Name Description
0x0 OPEN all switches are open
0x1 VA_PAD_A1 selects VA_PAD_A1
0x2 VA_PAD_A2 selects VA_PAD_A2
0x3 VA_PAD_A3 selects VA_PAD_A3
0x4 VR_ATEST_A0 selects VR_ATEST_A0
0x5 VR_ATEST_A1 selects VR_ATEST_A1
0x6 VA_ATEST_A0 selects VA_ATEST_A0
0x7 VA_ATEST_A1 selects VA_ATEST_A1
0x8 VDDA selects VDDA
RW 0x0
7:5 HYSSEL Used to enable and select hysteresis level.
Value ENUM Name Description
0x0 VAL0 hysteresis is disabled
0x1 VAL1 hysteresis value: TBD
0x2 VAL2 hysteresis value: TBD
0x3 VAL3 hysteresis value: TBD
0x4 VAL4 hysteresis value: TBD
0x5 VAL5 hysteresis value: TBD
0x6 VAL6 hysteresis value: TBD
0x7 VAL7 hysteresis value: TBD
RW 0b000
4 DIVPATH Used to select the path on which voltage divider is applied
Value ENUM Name Description
0x0 NSIDE divider is applied on N-side
0x1 PSIDE divider is applied on P-side
RW 0
3:1 DIV Used to configure reference divider. Setting values 0x5-0x7 will set the divide value to 1.
Value ENUM Name Description
0x0 VAL0 divide value is 1
0x1 VAL1 divide value is 3/4
0x2 VAL2 divide value is 1/2
0x3 VAL3 divide value is 1/3
0x4 VAL4 divide value is 1/4
RW 0b000
0 EN Used to enable comparator module.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0

TOP:SYS0:VGMCFG

Address Offset 0x0000 0110
Physical Address 0x4000 4110 Instance 0x4000 4110
Description This register is used to configure the VGM module.
Type RW
Bits Field Name Description Type Reset
31:24 KEY Key must be written with value 0x5A for successful write to VGMCFG and to unlock register state.
Write with any value other than 0x5A to KEY will be ignored and the register content is not updated.
Read value of KEY is 0x0.		 WO 0x00
23:20 RESERVED20 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
19:16 SPARE Spare bits RW 0x0
15:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
11:8 ATBMUXSEL These bits are used to generate VGM ATB mux selection control. RW 0x0
7:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000
1 OSHDETDIS Disables overshoot detector in VGM.
Value ENUM Name Description
0x0 EN Enable
0x1 DIS Disable
RW 0
0 USHTDETDIS Disables undershoot detector in VGM.
Value ENUM Name Description
0x0 EN Enable
0x1 DIS Disable
RW 0

TOP:SYS0:VGMTRIMDBG

Address Offset 0x0000 0114
Physical Address 0x4000 4114 Instance 0x4000 4114
Description This register is used to trim and debug VGM module.
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 RESERVED RO 0
30 TMODE5 Test mode bit for glitchy supply mux selection. RW 0
29:27 TMODE4 Test mode bits for VREF mux selection for overshoot detector. RW 0b000
26:24 TMODE3 Test mode bits for VREF mux selection for undershoot detector. RW 0b000
23:22 RESERVED22 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
21:20 TMODE2 Test mode for level shifter isolation. RW 0b00
19:18 TMODE1 Test mode bits for low voltage SR latch reset. RW 0b00
17:16 TMODE0 Test mode bits for 3V SR latch reset. RW 0b00
15:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
11:8 IBPROG These bits are used to program VGM bias current generator. RW 0x0
7:4 OSHDETTRIM These bits are used to trim VGM overshoot detector. RW 0x0
3:0 USHTDETTRIM These bits are used to trim VGM undershoot detector. RW 0x0

TOP:SYS0:TSDTEST

Address Offset 0x0000 0120
Physical Address 0x4000 4120 Instance 0x4000 4120
Description This register is used to set or clear the bits in 3V register bank for TSD comparator test control.
Internal note: DFT static gating to be applied on set[2:0] and clear[2:0] outputs.
Type WO
Bits Field Name Description Type Reset
31:6 RESERVED6 RESERVED RO 0b00 0000 0000 0000 0000 0000 0000
5:3 ATBCLR Clears ATB mux select in TSD comparator. WO 0b000
2:0 ATBSET Sets ATB mux select in TSD comparator.
Value ENUM Name Description
0x0 OPEN ATB is disabled. All switches are open in ATB mux
0x1 VSENSE Used for VSENSE trimming
0x2 VREF Used for VREF trimming
0x3 EA_CUR Brings out 100nA current from error amplifier
0x4 EN_DELAY Brings out delayed enable signal
0x5 COMPOUT Brings out comparator output
0x6 TSDOUT Brings out final TSD output before gating based on mux select bits
0x7 RESERVED Not used
WO 0b000

TOP:SYS0:DEVICEID

Address Offset 0x0000 03FC
Physical Address 0x4000 43FC Instance 0x4000 43FC
Description This register provides Device ID information.
Note: This 32-bit register value is provided as output to DEBUGSS.
Type RO
Bits Field Name Description Type Reset
31:28 VERSION Monotonic increasing value indicating new hardware revision. A newer hardware revision shall never have a lower version than an older revision of hardware. RO 0x0
27:12 DEVICE Value generated by RAMP for the SOC. This value uniquely identifies the die from any other TI device. RO 0xBB98
11:1 MANFACTURER JEP 106 assigned manufacturer ID. This field identifies the device as a Texas Instruments device. RO 0b000 0001 0111
0 ALWAYSONE Value 1 in this bit field means that a 32-bit scan register exists. RO 1

TOP:SYS0:TIMMUTE0

Address Offset 0x0000 0400
Physical Address 0x4000 4400 Instance 0x4000 4400
Description TIMMUTE0 trim Register
Type RW
Bits Field Name Description Type Reset
31:28 RESERVED28 RESERVED RO 0x0
27 GLDODISANA PMUREG: GLDO disable control selection between digital and analog schemes. 0: digital control, 1: analog control. RW 0
26 GLDOCOMPDIS PMUREG: Disables DCDC load meter based comparison and GLDO turn off scheme. RW 0
25 DISSAHYST PMUREG: Disable hysteresis in the supply awareness circuit. RW 0
24 VDDROKHYST PMUREG: Increase the hysteresis for when VDDR is considered ok. RW 0
23 SPARE REFSYS: Spare RW 0
22:21 TSENSE REFSYS: Temperature sensor trim RW 0b00
20:16 IREF REFSYS: IREF trim RW 0b0 0000
15 BGTRIMEN REFSYS: BOD BG trim enable RW 0
14:10 VDDSBOD REFSYS: VDDS BOD trim RW 0b0 0000
9:4 VBG REFSYS: VBG trim RW 0b00 0000
3:0 VREF REFSYS: VREF trim RW 0x0

TOP:SYS0:TIMMUTE1

Address Offset 0x0000 0404
Physical Address 0x4000 4404 Instance 0x4000 4404
Description TIMMUTE1 trim Register
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 RESERVED RO 0
30:28 DELTA PMUREG: Delta trim RW 0b000
27:24 COARSE PMUREG: Coarse trim RW 0x0
23:20 DIG PMUREG: DIG LDO trim RW 0x0
19:16 UDIG PMUREG: UDIG LDO trim RW 0x0
15:12 BOD PMUREG: BOD trim RW 0x0
11 EN_LOW_IQQ_GLDO This bit is used to enable low IQQ mode for GLDO.
Value ENUM Name Description
0x0 DISABLE Disable
0x1 ENABLE Enable
RW 0
10 DIS_HS_DCDC_COMP This bit is used to disable high speed DCDC comparator.
Value ENUM Name Description
0x0 ENABLE Enable
0x1 DISABLE Disable
RW 0
9:5 VDDRSL PMUREG: VDDR sleep trim RW 0b0 0000
4:0 VDDR PMUREG: VDDR trim RW 0b0 0000

TOP:SYS0:TIMMUTE2

Address Offset 0x0000 0408
Physical Address 0x4000 4408 Instance 0x4000 4408
Description TIMMUTE2 trim Register
Type RW
Bits Field Name Description Type Reset
31 CKMDIGLOCKSEL CKMKDIG: Selects between soft lock and global lock protection for HFOSCCTL register. 0: Soft lock, 1: Global lock. RW 0
30:25 WTOSSEP PMCTL: Separation between last stage with weak switch and first strong switch RW 0b11 1111
24:19 WSTGSEP PMCTL: Separation between weak switch stages RW 0b11 1111
18:17 SPARE PMUREG: Spare RW 0b00
16 GLDOEACDIS PMUREG: GLDO error amplifier clamp disable RW 0
15 GLDOISINKEN PMUREG: GLDO current sink enable RW 0
14:13 VDDRBCMP PMUREG: VDDR boost mode compensation RW 0b00
12:8 RECOMPOS PMUREG: Recharge comparator offset trim RW 0b0 0000
7:5 ITUDIG PMUREG: ITRIM UDIG LDO RW 0b000
4:2 ITDIG PMUREG: ITRIM DIG LDO RW 0b000
1:0 ITDUMMY PMUREG: ITRIM dummy RW 0b00

TOP:SYS0:TIMMUTE3

Address Offset 0x0000 040C
Physical Address 0x4000 440C Instance 0x4000 440C
Description TIMMUTE3 trim Register
Type WO
Bits Field Name Description Type Reset
31:28 RESERVED28 RESERVED RO 0x0
27 ATBRESBYPCLK TSD ATB series resistance bypass clear value. WO 0
26 HYDISCLR TSD hysteresis disable clear value. WO 0
25:20 TSENSCLR TSD comparator temperature sensor trim clear value WO 0b00 0000
19 TMODECLR TSD comparator bandgap reference trim clear value WO 0
18:14 BGRCLR TSD comparator bandgap reference trim clear value WO 0b0 0000
13 ATBRESBYPSET TSD ATB series resistance bypass set value.
Value ENUM Name Description
0x0 CONN Resistor connected
0x1 BYPASS Resistor bypassed
WO 0
12 HYSDISSET TSD hysteresis disable set value.
Value ENUM Name Description
0x0 EN Enable
0x1 DIS Disable
WO 0
11:6 TSENSSET TSD comparator temperature sensor trim set value WO 0b00 0000
5 TMODESET TSD test mode select set value for trim and test.
Value ENUM Name Description
0x0 ATB ATB mode
0x1 ADC ADC mode
WO 0
4:0 BGRSET TSD comparator bandgap reference trim set value WO 0b0 0000

TOP:SYS0:PARTID

Address Offset 0x0000 07F8
Physical Address 0x4000 47F8 Instance 0x4000 47F8
Description This register is programmed by boot code with Part ID information.Note: This 32-bit register value is provided as output to DEBUGSS
Type RW
Bits Field Name Description Type Reset
31 START Start bit
Value ENUM Name Description
0x0 CLR Clear
0x1 SET Set
RW 0
30:28 MAJORREV Monotonic increasing value indicating a new revision of the SKU significant enough that users of the device may have to revise PCB or or software design RW 0b000
27:24 MINORREV Monotonic increasing value indicating a new revision of the SKU that preserves compatibility with lesser MINORREV values RW 0x0
23:16 VARIANT Bit pattern uniquely identifying a part RW 0x00
15:0 PART Bit pattern uniquely identifying a part RW 0x0000

TOP:SYS0:LIFECYC

Address Offset 0x0000 07FC
Physical Address 0x4000 47FC Instance 0x4000 47FC
Description This register is programmed by boot code with device life cycle information
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 RESERVED RO 0x00 0000
7:0 VAL Device life cycle value
Value ENUM Name Description
0x0 LCYCLE_POSSIBLE_1STBDAY Possible first birthday
0x1 LCYCLE_1STBDAY First birthday
0x2 LCYCLE_TESTPT Test PT
0x3 LCYCLE_TESTFT Test FT
0x4 LCYCLE_ENGRDEV Engineering device
0x5 LCYCLE_PRODDEV Production device
0x6 LCYCLE_RETEST Re-test
0xFF LCYCLE_ILLEGAL Illegal
RW 0x00

TOP:SYS0:TMUTE0

Address Offset 0x0000 0800
Physical Address 0x4000 4800 Instance 0x4000 4800
Description TMUTE0 trim Register
Type RW
Bits Field Name Description Type Reset
31:0 CDACL SOCADC: Lower 32 bits of CDAC trim. These bits are used in DTC. RW 0x0000 0000

TOP:SYS0:TMUTE1

Address Offset 0x0000 0804
Physical Address 0x4000 4804 Instance 0x4000 4804
Description TMUTE1 trim Register
Type RW
Bits Field Name Description Type Reset
31:0 CDACM SOCADC: Middle 32 bits of CDAC trim. These bits are used in DTC. RW 0x0000 0000

TOP:SYS0:TMUTE2

Address Offset 0x0000 0808
Physical Address 0x4000 4808 Instance 0x4000 4808
Description TMUTE2 trim Register
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 RESERVED RO 0
30:26 IBTRIM LPCOMP: Bias current trim, 250nA to be terminated across I2V, 1M ohm setting. Resulting target trim voltage 250mV. RW 0b0 0000
25:23 TRIM ADC REFBUF trim bits. RW 0b001
22:16 LATCH SOC ADC: Latch trim bits. These bits are used in the analog IP. RW 0b000 0000
15:4 OFFSET SOCADC: Offset trim bits. These bits are used in DTC. RW 0x000
3:2 RES SOCADC: Resistor trim bits. These bits are used in the analog IP. RW 0b00
1:0 CDACU SOCADC: Upper 2 bits of CDAC trim. These bits are used in DTC. RW 0b00

TOP:SYS0:TMUTE3

Address Offset 0x0000 080C
Physical Address 0x4000 480C Instance 0x4000 480C
Description TMUTE3 trim Register
Type RW
Bits Field Name Description Type Reset
31:26 BATC1 BATMON: Battery calculation coefficient 1 RW 0b00 0000
25:19 BATC0 BATMON: Battery calculation coefficient 0 RW 0b000 0000
18:14 TEMPC2 BATMON: Temperature calculation coefficient 2 RW 0b0 0000
13:8 TEMPC1 BATMON: Temperature calculation coefficient 1 RW 0b00 0000
7:0 TEMPC0 BATMON: Temperature calculation coefficient 0 RW 0x00

TOP:SYS0:TMUTE4

Address Offset 0x0000 0810
Physical Address 0x4000 4810 Instance 0x4000 4810
Description TMUTE4 trim Register
Type RW
Bits Field Name Description Type Reset
31:28 RECHCOMPREFLVL PMUREG: Recharge comparator reference level. Valid values are 0x2 to 0xA. Recommended default value is 0x9. Setting 0x2 corresponds to VDDR = 1.35V and 0xA corresponds to VDDR = 1.47V with 15mV linear increase for every step. RW 0xB
27:26 IOSTRCFG2 BATMON: IO drive strength conversion parameter for the second stage RW 0b00
25:22 IOSTRCFG1 BATMON: IO drive strength conversion parameter for the first stage RW 0x0
21:19 MAX IOC: Maximum IO drive strength RW 0b101
18:16 MED IOC: Medium IO drive strength RW 0b110
15:13 MIN IOC: Minimum IO drive strength RW 0b011
12:11 DCDCLOAD DCDC: Set DCDC load current threshold RW 0b00
10:8 IPEAK DCDC: Set inductor peak current RW 0b000
7:6 DTIME DCDC: Dead time trim RW 0b00
5:3 LENSEL DCDC: Control NMOS switch strength RW 0b111
2:0 HENSEL DCDC: Control PMOS switch strength RW 0b111

TOP:SYS0:TMUTE5

Address Offset 0x0000 0814
Physical Address 0x4000 4814 Instance 0x4000 4814
Description TMUTE5 trim Register
Type RW
Bits Field Name Description Type Reset
31:13 RESERVED13 RESERVED RO 0b000 0000 0000 0000 0000
12:10 DCDCDRVDS DCDC: Driver drive strength configuration RW 0b000
9:5 GLDOISCLR GLDO current source trim clear value WO 0b0 0000
4:0 GLDOISSET GLDO current source trim set value WO 0b0 0000
4:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000


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