AES

Instance: AES
Component: AES
Base address: 0x400C0000

The Loki AES-128 crypto peripheral accellerates AES-128 block cipher encryption (ECB). The peripheral does also offer HW features to accellerate cipher modes implemented in SW:

* CBC-MAC
* CBC
* CTR
* CFB
* OFB
* PCBC

The module provides two data registers that can be input to ECB encryption. These are termed TXT and BUF. TXT is the AES-128 work buffer, and content changes during an ECB encryption. SW cannot update TXT during encryption. BUF is an auxiliary 128-bit buffer with multiple purposes:
* initialization vector(IV) storage
* counter in CTR cipher mode
* hold next value of TXT

SW can update BUF during an ECB enryption. This allows SW to write next TXT during an encryption an hence save ECB idle times.

TOP:AES Register Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset	Physical Address
DESC	RO	32	0x6B42 4010	0x0000 0000	0x400C 0000
TRG	WO	32	0x0000 0000	0x0000 0010	0x400C 0010
ABORT	WO	32	0x0000 0000	0x0000 0014	0x400C 0014
CLR	WO	32	0x0000 0000	0x0000 0018	0x400C 0018
STA	RO	32	0x0000 0000	0x0000 001C	0x400C 001C
DMA	RW	32	0x0000 0000	0x0000 0020	0x400C 0020
DMACHA	RW	32	0x0000 0000	0x0000 0024	0x400C 0024
DMACHB	RW	32	0x0000 0000	0x0000 0028	0x400C 0028
AUTOCFG	RW	32	0x0000 0000	0x0000 002C	0x400C 002C
KEY0	WO	32	0x0000 0000	0x0000 0050	0x400C 0050
KEY1	WO	32	0x0000 0000	0x0000 0054	0x400C 0054
KEY2	WO	32	0x0000 0000	0x0000 0058	0x400C 0058
KEY3	WO	32	0x0000 0000	0x0000 005C	0x400C 005C
TXT0	RW	32	0x0000 0000	0x0000 0070	0x400C 0070
TXT1	RW	32	0x0000 0000	0x0000 0074	0x400C 0074
TXT2	RW	32	0x0000 0000	0x0000 0078	0x400C 0078
TXT3	RW	32	0x0000 0000	0x0000 007C	0x400C 007C
TXTX0	WO	32	0x0000 0000	0x0000 0080	0x400C 0080
TXTX1	WO	32	0x0000 0000	0x0000 0084	0x400C 0084
TXTX2	WO	32	0x0000 0000	0x0000 0088	0x400C 0088
TXTX3	WO	32	0x0000 0000	0x0000 008C	0x400C 008C
BUF0	RW	32	0x0000 0000	0x0000 0090	0x400C 0090
BUF1	RW	32	0x0000 0000	0x0000 0094	0x400C 0094
BUF2	RW	32	0x0000 0000	0x0000 0098	0x400C 0098
BUF3	RW	32	0x0000 0000	0x0000 009C	0x400C 009C
TXTXBUF0	RO	32	0x0000 0000	0x0000 00A0	0x400C 00A0
TXTXBUF1	RO	32	0x0000 0000	0x0000 00A4	0x400C 00A4
TXTXBUF2	RO	32	0x0000 0000	0x0000 00A8	0x400C 00A8
TXTXBUF3	RO	32	0x0000 0000	0x0000 00AC	0x400C 00AC
IMASK	RW	32	0x0000 0000	0x0000 0104	0x400C 0104
RIS	RO	32	0x0000 0000	0x0000 0108	0x400C 0108
MIS	RO	32	0x0000 0000	0x0000 010C	0x400C 010C
ISET	WO	32	0x0000 0000	0x0000 0110	0x400C 0110
ICLR	WO	32	0x0000 0000	0x0000 0114	0x400C 0114
IMSET	WO	32	0x0000 0000	0x0000 0118	0x400C 0118
IMCLR	WO	32	0x0000 0000	0x0000 011C	0x400C 011C

TOP:AES Register Descriptions

TOP:AES:DESC

Address Offset	0x0000 0000
Physical Address	0x400C 0000	Instance	0x400C 0000
Description	Description
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	MODID	Module Identifier	RO	0x6B42
15:12	STDIPOFF	64 B Standard IP MMR Block 0: These MMRs do not exist 1:15: These MMRs begin at offset 64*STDIPOFF from IP base address	RO	0x4
11:8	INSTIDX	Instance Number	RO	0x0
7:4	MAJREV	Major Revision	RO	0x1
3:0	MINREV	Minor Revision	RO	0x0

TOP:AES:TRG

Address Offset	0x0000 0010
Physical Address	0x400C 0010	Instance	0x400C 0010
Description	Trigger Use this register to manually trigger operations.
Type	WO

Bits

Field Name

Description

Type

Reset

31:4

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0x000 0000

DMACHA

Write 1 to this field to manually trigger channel A request.

DMACHB

Write 1 to this field to manually trigger channel B request.

1:0

ECBOP

Electronic Codebook (ECB) Operation

Write an enumerated value to this field when STA.STATE = IDLE to manually trigger an ECB encryption. If condition is not met, the trigger is ignored. Non-enumerated values are ignored.

Value	ENUM Name	Description
0x1	TXT	TXT = ECB(KEY,TXT)
0x2	BUF	TXT = ECB(KEY,BUF)
0x3	TXTXBUF	TXT = ECB(KEY, TXT XOR BUF)

0b00

TOP:AES:ABORT

Address Offset	0x0000 0014
Physical Address	0x400C 0014	Instance	0x400C 0014
Description	Abort Use this register to abort current ECB encryption.
Type	WO

Bits	Field Name	Description	Type	Reset
31:1	RESERVED1	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	WO	0b000 0000 0000 0000 0000 0000 0000 0000
0	ECB	Electronic Codebook Write 1 to this field to abort an ongoing ECB encryption. An abort will clear TXT, BUF, DMA, AUTOCFG registers	WO	0

TOP:AES:CLR

Address Offset	0x0000 0018
Physical Address	0x400C 0018	Instance	0x400C 0018
Description	Clear Use this register to clear contents of TXT and BUF when STA.STATE = IDLE. If condition is not met, the contents remain unchanged.
Type	WO

Bits	Field Name	Description	Type	Reset
31:2	RESERVED2	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	WO	0b00 0000 0000 0000 0000 0000 0000 0000
1	TXT	Write 1 to this field to clear TXT.	WO	0
0	BUF	Write 1 to this field to clear BUF.	WO	0

TOP:AES:STA

Address Offset	0x0000 001C
Physical Address	0x400C 001C	Instance	0x400C 001C
Description	Status This register provides information on ECB accellerator state and BUF status.
Type	RO

Bits

Field Name

Description

Type

Reset

31:5

RESERVED5

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b000 0000 0000 0000 0000 0000 0000

4:3

KEYMST

This field gives the status of which master has written KEY MMR's.

Value	ENUM Name	Description
0x0	CORE	Value of Key MMRs written by CM33
0x3	HSM	Value of Keys written by HSM

0b00

KEYSTATE

This field gives status of valid data in KEY MMR's

Value	ENUM Name	Description
0x0	EMPTY	KEY MMRs are empty or partially written
0x1	VALID	KEY MMR's are written with valid data

BUFSTA

BUF Status

Field gives the status of BUF, indicating EMPTY or FULL, when AUTOCFG.TRGECB = WRBUF3.
If AUTOCFG.TRGECB != WRBUF3, then STA.BUFSTA will hold the value 0.
Note : Useful for CBC-MAC

Value	ENUM Name	Description
0x0	EMPTY	Data stored in BUF is already consumed by the AES engine and next block of data can be written in BUF
0x1	FULL	Data stored in BUF is not yet consumed by the AES engine. Next block of data cannot be written into BUF until STA.STATE = IDLE.

STATE

State

Field gives the state of the ECB encryption engine.

Value	ENUM Name	Description
0x0	IDLE	ECB is IDLE.
0x1	BUSY	ECB encryption active.

TOP:AES:DMA

Address Offset	0x0000 0020
Physical Address	0x400C 0020	Instance	0x400C 0020
Description	Direct Memory Access This register controls the conditions that will generate burst requests on each DMA channel.
Type	RW

Bits

Field Name

Description

Type

Reset

31:20

RESERVED19

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0x000

19:16

DONEACT

Done Action

This field determines the side effects of DMA done. It is allowed to configure this field with an OR-combination of supported enums, with the exception that GATE_TRGECB_ON_CHA and GATE_TRGECB_ON_CHA_DEL shall be mutually exclusive

Value	ENUM Name	Description
0x0	DIS	DMA done has no side effect.
0x1	GATE_TRGECB_ON_CHA	Triggers defined in AUTOCFG.TRGECB are gated when RIS.CHADONE = SET.
0x2	GATE_TRGECB_ON_CHA_DEL	Due to the pipelining of BUF writes, in certain modes, DMA CHA Done appears before the last but one ECB has completed. Setting this bit, will gate the triggers defined in AUTOCFG.TRGECB only after the last write by CHA is consumed by AES FSM. Used in ECB,CBC,CBC-MAC modes (having multiple blocks encryption) to avoid spurious ECB triggered on last read by CHB. For single mode encryption, DMA.GATE_TRGECB_ON_CHA should be used.
0x4	CLR_TXT_ON_CHA	DMA channel A done event clears TXT0 thru TXT3 if STA.STATE = IDLE. Event is ignored if condition is not met.
0x8	CLR_TXT_ON_CHB	DMA channel B done event clears TXT0 thru TXT3 if STA.STATE = IDLE. Event is ignored if condition is not met.

0x0

15:14

RESERVED14

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00

13:12

ADRCHB

Channel B Read Write Address

The DMA accesses DMACHB to read or write contents of TXT and BUF as a response to a burst request. This field specifes the start address of the first DMA transfer that follows the burst request. The internal address gets incremented automatically for subsequent accesses. The DMA shall transfer 8-bit, 16-bit, or 32-bit words, and shall always complete a 16-byte transfer before re-arbitration.

Value	ENUM Name	Description
0x0	TXT0	Start address is TXT0.
0x1	TXTX0	Start address is TXTX0.
0x2	BUF0	Start address is BUF0.
0x3	TXTXBUF0	Start address is TXTXBUF0.

0b00

RESERVED11

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

10:8

TRGCHB

Channel B Trigger

Select the condition that trigger DMA channel B request. Non-enumerated values are not supported and ignored.

Value	ENUM Name	Description
0x0	DIS	DMA requests are disabled.
0x1	ECBSTART	Start of ECB encryption triggers request.
0x2	ECBDONE	Completion of ECB encryption triggers request.
0x3	WRTXT3	Writes to TXT3, TXTX3, or TXTXBUF3 generates request.
0x4	RDTXT3	Reads of TXT3, or TXTXBUF3 generates request.

0b000

7:6

RESERVED6

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00

5:4

ADRCHA

Channel A Read Write Address

The DMA accesses DMACHA to read or write contents of TXT and BUF as a response to a burst request. This field specifes the start address of the first DMA transfer that follows the burst request. The internal address gets incremented automatically for subsequent accesses. The DMA shall transfer 8-bit, 16-bit, or 32-bit words, and shall always complete a 16-byte transfer before re-arbitration.

Value	ENUM Name	Description
0x0	TXT0	Start address is TXT0.
0x1	TXTX0	Start address is TXTX0.
0x2	BUF0	Start address is BUF0.
0x3	TXTXBUF0	Start address is TXTXBUF0.

0b00

RESERVED3

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2:0

TRGCHA

Channel A Trigger

Select the condition that trigger DMA channel A request. Non-enumerated values are not supported and ignored.

Value	ENUM Name	Description
0x0	DIS	DMA requests are disabled.
0x1	ECBSTART	Start of ECB encryption trigger request.
0x2	ECBDONE	Completion of ECB encryption trigger request.
0x3	WRTXT3	Writes to TXT3 or TXTX3 trigger request.
0x4	RDTXT3	Reads of TXT3 or TXTXBUF3 trigger request.

0b000

TOP:AES:DMACHA

Address Offset	0x0000 0024
Physical Address	0x400C 0024	Instance	0x400C 0024
Description	DMA Channel A Read Write DMA accesses this register to read or write contents from sequential addresses specifed by DMA.ADRCHA.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Value			RW	0x0000 0000

TOP:AES:DMACHB

Address Offset	0x0000 0028
Physical Address	0x400C 0028	Instance	0x400C 0028
Description	DMA Channel B Read Write DMA accesses this register to read or write contents from sequential addresses specifed by DMA.ADRCHB.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	Value			RW	0x0000 0000

TOP:AES:AUTOCFG

Address Offset	0x0000 002C
Physical Address	0x400C 002C	Instance	0x400C 002C
Description	Automatic Configuration This register configures automatic HW updates to TXT and BUF. Configure this register to reduce SW overhead during ciper modes.
Type	RW

Bits

Field Name

Description

Type

Reset

31:29

RESERVED29

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b000

CHBDONECLR

This field enable auto-clear of RIS.CHBDONE interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 .

Value	ENUM Name	Description
0x0	DIS	Disable auto-clear of RIS.CHBDONE interrupt
0x1	EN	Enable auto-clear of RIS.CHBDONE interrupt

CHADONECLR

This field enables auto-clear of RIS.CHADONE interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 .

Value	ENUM Name	Description
0x0	DIS	Disable auto-clear of RIS.CHADONE interrupt
0x1	EN	Enable auto-clear of RIS.CHADONE interrupt

ECBSTARTCLR

This field enables auto-clear of RIS.ECBSTART interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 .

Value	ENUM Name	Description
0x0	DIS	Disable auto-clear of RIS.ECBSTART interrupt
0x1	EN	Enable auto-clear of RIS.ECBSTART interrupt

ECBDONECLR

This field enables auto-clear of RIS.ECBDONE interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 .

Value	ENUM Name	Description
0x0	DIS	Disable auto-clear of RIS.ECBDONE interrupt
0x1	EN	Enable auto-clear of RIS.ECBDONE interrupt

BUSHALT

Bus Halt

This field decides if bus halts on access to KEY, TXT, BUF, TXTX and TXTXBUF when STA.STATE = BUSY.

Value	ENUM Name	Description
0x0	DIS	Disable bus halt When STA.STATE = BUSY, writes to KEY, TXT, TXTX are ignored, reads from TXT, TXTXBUF return zero. When STA.STATE = BUSY and if either STA.BUFSTA = FULL or AUTOCFG.CTRSIZE != DISABLE, writes to BUF are ignored, reads return zero.
0x1	EN	Enable bus halt When STA.STATE = BUSY, access to KEY, TXT, TXTX, TXTXBUF halt the bus until STA.STATE = IDLE. When STA.STATE = BUSY and if either STA.BUFSTA = FULL or AUTOCFG.CTRSIZE != DISABLE, access to BUF halts the bus until STA.STATE = IDLE.

23:22

RESERVED22

Reserved for future use. Any writes to this field are ignored

0b00

21:19

CTRSIZE

Configures size of counter as either 8,16,32,64 or 128
Non-enumerated values are not supported and ignored

Value	ENUM Name	Description
0x0	DIS	Disable CTR operation
0x1	CTR8	Configures counter size as 8 bit
0x2	CTR16	Configures counter size as 16 bit
0x3	CTR32	Configures counter size as 32 bit
0x4	CTR64	Configures counter size as 64 bit
0x5	CTR128	Configures counter size as 128 bit

0b000

CTRALIGN

Value	ENUM Name	Description
0x0	LEFTALIGN	Indicates Left Aligned Counter Not applicable for 128 bit counter size. For 128 bit counter, all octets will be considered When left aligned,,octet 0-7 will be considered , based on counter size and endianness
0x1	RIGHTALIGN	Indicates right aligned counter Not applicable when counter size is 128bit For 128 bit counter, all octets will be considered If right aligned, octet 8-15 will be considered based on endianness and counter size

CTRENDIAN

Counter Endianness

Specifies Endianness of counter

Value	ENUM Name	Description
0x0	LITTLEENDIAN	Specifies Little Endian Counter. Carry will flow from octet 'n' to octet 'n+1'
0x1	BIGENDIAN	Specifies Big Endian Counter Carry will flow from octet 'n' to octet 'n-1'

16:10

RESERVED11

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b000 0000

9:8

TRGTXT

Trigger for TXT

This field determines if and when HW automatically XORs BUF into TXT. Non-enumerated values are not supported and ignored. It is allowed to configure this field with an OR-combination of supported enums.

Value	ENUM Name	Description
0x0	DIS	No HW update of TXT
0x1	RDTXT3	HW XORs content of BUF into TXT upon read of TXT3.
0x2	RDTXTXBUF3	HW XORs content of BUF into TXT upon read of TXTXBUF3.

0b00

7:6

RESERVED6

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00

5:4

ECBSRC

Electronic Codebook Source

This field specifies the data source to HW-triggered ECB encryptions. Non-enumerated values are not supported and ignored.

Value	ENUM Name	Description
0x1	TXT	TXT = ECB(KEY,TXT)
0x2	BUF	TXT = ECB(KEY,BUF)
0x3	TXTXBUF	TXT = ECB(KEY, TXT XOR BUF)

0b00

3:0

TRGECB

Trigger Electronic Codebook

This field specifies one or more actions that indirectly trigger operation selected in ECB.
It is allowed to configure this field with an OR-combination of supported enums.

Value	ENUM Name	Description
0x0	DIS	No user action indirectly trigger ECB.
0x1	WRTXT3	When STA.STATE = IDLE, all writes to TXT3 or TXTX3 trigger action. No action gets triggered unless condition is met.
0x2	RDTXT3	When STA.STATE = IDLE, all reads of TXT3 or TXTXBUF3 trigger action. No action gets triggered unless condition is met.
0x4	WRBUF3	When AUTOCFG.CTRSIZE = DIS, all writes to BUF3 schedule to trigger action once STA.STATE is or becomes IDLE. No action gets triggered unless condition is met.
0x8	WRBUF3S	Write to BUF3 schedules to trigger single action once STA.STATE is or becomes IDLE. No action gets triggered unless condition is met. Subsequent writes does not trigger any action unless you write this setting again to this field.

0x0

TOP:AES:KEY0

Address Offset	0x0000 0050
Physical Address	0x400C 0050	Instance	0x400C 0050
Description	Key Word 0 Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the HW. It is hence not required to reloaded the key for subsequent block encryptions unless required by the application.
Type	WO

Bits	Field Name	Description			Type	Reset
31:0	VAL	Value of KEY[31:0].			WO	0x0000 0000

TOP:AES:KEY1

Address Offset	0x0000 0054
Physical Address	0x400C 0054	Instance	0x400C 0054
Description	Key Word 1 Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the HW. It is hence not required to reloaded the key for subsequent block encryptions unless required by the application.
Type	WO

Bits	Field Name	Description			Type	Reset
31:0	VAL	KEY[63:32]			WO	0x0000 0000

TOP:AES:KEY2

Address Offset	0x0000 0058
Physical Address	0x400C 0058	Instance	0x400C 0058
Description	Key Word 2 Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the HW. It is hence not required to reloaded the key for subsequent block encryptions unless required by the application.
Type	WO

Bits	Field Name	Description			Type	Reset
31:0	VAL	KEY[95:64]			WO	0x0000 0000

TOP:AES:KEY3

Address Offset	0x0000 005C
Physical Address	0x400C 005C	Instance	0x400C 005C
Description	Key Word 3 Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the HW. It is hence not required to reloaded the key for subsequent block encryptions unless required by the application.
Type	WO

Bits	Field Name	Description			Type	Reset
31:0	VAL	KEY[127:96]			WO	0x0000 0000

TOP:AES:TXT0

Address Offset	0x0000 0070
Physical Address	0x400C 0070	Instance	0x400C 0070
Description	Text Word 0 TXT is the 128-bit buffer the AES-128 encryption algorithm performs its operations on. Write ECB input to TXT, read ciphertext from TXT.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	TXT[31:0]			RW	0x0000 0000

TOP:AES:TXT1

Address Offset	0x0000 0074
Physical Address	0x400C 0074	Instance	0x400C 0074
Description	Text Word 1 TXT is the 128-bit buffer the AES-128 encryption algorithm performs its operations on. Write ECB input to TXT, read ciphertext from TXT.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	TXT[63:32]			RW	0x0000 0000

TOP:AES:TXT2

Address Offset	0x0000 0078
Physical Address	0x400C 0078	Instance	0x400C 0078
Description	Text Word 2 TXT is the 128-bit buffer the AES-128 encryption algorithm performs its operations on. Write ECB input to TXT, read ciphertext from TXT.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	TXT[95:64]			RW	0x0000 0000

TOP:AES:TXT3

Address Offset	0x0000 007C
Physical Address	0x400C 007C	Instance	0x400C 007C
Description	Text Word 3 TXT is the 128-bit buffer the AES-128 encryption algorithm performs its operations on. Write ECB input to TXT, read ciphertext from TXT.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	TXT[127:96] AUTOCFG.TRGECB decides if a write to or a read of this field trigger an encryption.			RW	0x0000 0000

TOP:AES:TXTX0

Address Offset	0x0000 0080
Physical Address	0x400C 0080	Instance	0x400C 0080
Description	Text Word 0 XOR Write data to this register to XOR data with contents in TXT0.VAL.
Type	WO

Bits	Field Name	Description			Type	Reset
31:0	VAL	TXT0.VAL = VAL XOR TXT0.VAL			WO	0x0000 0000

TOP:AES:TXTX1

Address Offset	0x0000 0084
Physical Address	0x400C 0084	Instance	0x400C 0084
Description	Text Word 1 XOR Write data to this register to XOR data with contents in TXT1.VAL.
Type	WO

Bits	Field Name	Description			Type	Reset
31:0	VAL	TXT1.VAL = VAL XOR TXT1.VAL			WO	0x0000 0000

TOP:AES:TXTX2

Address Offset	0x0000 0088
Physical Address	0x400C 0088	Instance	0x400C 0088
Description	Text Word 2 XOR Write data to this register to XOR data with contents in TXT2.VAL.
Type	WO

Bits	Field Name	Description			Type	Reset
31:0	VAL	TXT2.VAL = VAL XOR TXT2.VAL			WO	0x0000 0000

TOP:AES:TXTX3

Address Offset	0x0000 008C
Physical Address	0x400C 008C	Instance	0x400C 008C
Description	Text Word 3 XOR Write data to this register to XOR data with contents in TXT3.VAL. AUTOCFG.TRGECB decides if a write to or a read of this field trigger an encryption.
Type	WO

Bits	Field Name	Description			Type	Reset
31:0	VAL	TXT3.VAL = VAL XOR TXT3.VAL			WO	0x0000 0000

TOP:AES:BUF0

Address Offset	0x0000 0090
Physical Address	0x400C 0090	Instance	0x400C 0090
Description	Buffer Word 0 BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	BUF[31:0]			RW	0x0000 0000

TOP:AES:BUF1

Address Offset	0x0000 0094
Physical Address	0x400C 0094	Instance	0x400C 0094
Description	Buffer Word 1 BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	BUF[63:32]			RW	0x0000 0000

TOP:AES:BUF2

Address Offset	0x0000 0098
Physical Address	0x400C 0098	Instance	0x400C 0098
Description	Buffer Word 2 BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	BUF[95:64]			RW	0x0000 0000

TOP:AES:BUF3

Address Offset	0x0000 009C
Physical Address	0x400C 009C	Instance	0x400C 009C
Description	Buffer Word 3 BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes. AUTOCFG.TRGECB decides if a write to this field trigger an encryption.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	BUF[127:96]			RW	0x0000 0000

TOP:AES:TXTXBUF0

Address Offset	0x0000 00A0
Physical Address	0x400C 00A0	Instance	0x400C 00A0
Description	Text Word 0 XOR Buffer Word 0 Read this register to obtain plaintext during CFB decryption.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	VAL	VAL = TXT0.VAL XOR BUF0.VAL			RO	0x0000 0000

TOP:AES:TXTXBUF1

Address Offset	0x0000 00A4
Physical Address	0x400C 00A4	Instance	0x400C 00A4
Description	Text Word 1 XOR Buffer Word 1 Read this register to obtain plaintext during CFB decryption.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	VAL	VAL = TXT1.VAL XOR BUF1.VAL			RO	0x0000 0000

TOP:AES:TXTXBUF2

Address Offset	0x0000 00A8
Physical Address	0x400C 00A8	Instance	0x400C 00A8
Description	Text Word 2 XOR Buffer Word 2 Read this register to obtain plaintext during CFB decryption.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	VAL	VAL = TXT2.VAL XOR BUF2.VAL			RO	0x0000 0000

TOP:AES:TXTXBUF3

Address Offset	0x0000 00AC
Physical Address	0x400C 00AC	Instance	0x400C 00AC
Description	Text Word 3 XOR Buffer Word3 Read this register to obtain plaintext during CFB decryption.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	VAL	VAL = TXT3.VAL XOR BUF3.VAL			RO	0x0000 0000

TOP:AES:IMASK

Address Offset	0x0000 0104
Physical Address	0x400C 0104	Instance	0x400C 0104
Description	Interrupt Mask This register contains the current interrupt mask settings.
Type	RW

Bits

Field Name

Description

Type

Reset

31:4

RESERVED2

0x000 0000

CHBDONE

DMA Channel B Done Interrupt

Value	ENUM Name	Description
0x0	DIS
0x1	EN

CHADONE

DMA Channel A Done Interrupt

Value	ENUM Name	Description
0x0	DIS
0x1	EN

ECBSTART

ECB Start Interrupt

Value	ENUM Name	Description
0x0	DIS
0x1	EN

ECBDONE

ECB Done Interrupt

Value	ENUM Name	Description
0x0	DIS
0x1	EN

TOP:AES:RIS

Address Offset	0x0000 0108
Physical Address	0x400C 0108	Instance	0x400C 0108
Description	Raw Interrupt Status This register holds the current raw interrupt status.
Type	RO

Bits

Field Name

Description

Type

Reset

31:4

RESERVED2

0x000 0000

CHBDONE

DMA Channel B Done Interrupt

Value	ENUM Name	Description
0x0	CLR
0x1	SET

CHADONE

DMA Channel A Done Interrupt

Value	ENUM Name	Description
0x0	CLR
0x1	SET

ECBSTART

ECB Start Interrupt

Value	ENUM Name	Description
0x0	CLR
0x1	SET

ECBDONE

ECB Done Interrupt

Value	ENUM Name	Description
0x0	CLR
0x1	SET

TOP:AES:MIS

Address Offset	0x0000 010C
Physical Address	0x400C 010C	Instance	0x400C 010C
Description	Masked Interrupt Status This register holds the masked interrupt status.
Type	RO

Bits

Field Name

Description

Type

Reset

31:4

RESERVED2

0x000 0000

CHBDONE

DMA Channel B Done Interrupt

Value	ENUM Name	Description
0x0	CLR
0x1	SET

CHADONE

DMA Channel A Done Interrupt

Value	ENUM Name	Description
0x0	CLR
0x1	SET

ECBSTART

ECB Start Interrupt

Value	ENUM Name	Description
0x0	CLR
0x1	SET

ECBDONE

ECB Done Interrupt

Value	ENUM Name	Description
0x0	CLR
0x1	SET

TOP:AES:ISET

Address Offset	0x0000 0110
Physical Address	0x400C 0110	Instance	0x400C 0110
Description	Interrupt Set Write this register to set one or more interrupts.
Type	WO

Bits

Field Name

Description

Type

Reset

31:4

RESERVED2

0x000 0000

CHBDONE

DMA Channel B Done Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	SET

CHADONE

DMA Channel A Done Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	SET

ECBSTART

ECB Start Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	SET

ECBDONE

ECB Done Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	SET

TOP:AES:ICLR

Address Offset	0x0000 0114
Physical Address	0x400C 0114	Instance	0x400C 0114
Description	Interrupt Clear Write this register to clear one or more interrupts.
Type	WO

Bits

Field Name

Description

Type

Reset

31:4

RESERVED2

0x000 0000

CHBDONE

DMA Channel B Done Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	CLR

CHADONE

DMA Channel A Done Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	CLR

ECBSTART

ECB Start Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	CLR

ECBDONE

ECB Done Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	CLR

TOP:AES:IMSET

Address Offset	0x0000 0118
Physical Address	0x400C 0118	Instance	0x400C 0118
Description	Interrupt Mask Set Write this register to set individual bits in IMASK.
Type	WO

Bits

Field Name

Description

Type

Reset

31:4

RESERVED2

0x000 0000

CHBDONE

DMA Channel B Done Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	SET

CHADONE

DMA Channel A Done Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	SET

ECBSTART

ECB Start Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	SET

ECBDONE

ECB Done Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	SET

TOP:AES:IMCLR

Address Offset	0x0000 011C
Physical Address	0x400C 011C	Instance	0x400C 011C
Description	Interrupt Mask Clear Write this register to clear individual bits in IMASK.
Type	WO

Bits

Field Name

Description

Type

Reset

31:4

RESERVED2

0x000 0000

CHBDONE

DMA Channel B Done Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	CLR

CHADONE

DMA Channel A Done Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	CLR

ECBSTART

ECB Start Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	CLR

ECBDONE

ECB Done Interrupt

Value	ENUM Name	Description
0x0	NO_EFFECT
0x1	CLR