Instance: FLASH
Component: FLASH
Base address: 0x40021000
This is the MMR space for the flash wrapper. The flash wrapper is targeting
multiple microcontroller platforms. The flash wrapper is a module
that manages complex flash read, program and erase memory operations.
The system is also given direct access to read flash memory contents directly for
each instantiated flash bank through FBAP ports.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x4002 1028 |
|
RO |
32 |
0x0000 0000 |
0x0000 0030 |
0x4002 1030 |
|
RO |
32 |
0x0000 0000 |
0x0000 0038 |
0x4002 1038 |
|
WO |
32 |
0x0000 0000 |
0x0000 0040 |
0x4002 1040 |
|
WO |
32 |
0x0000 0000 |
0x0000 0048 |
0x4002 1048 |
|
RO |
32 |
0x0B40 4010 |
0x0000 00FC |
0x4002 10FC |
|
RW |
32 |
0x0000 0000 |
0x0000 0100 |
0x4002 1100 |
|
RW |
32 |
0x0000 0000 |
0x0000 0104 |
0x4002 1104 |
|
RW |
32 |
0x0000 0000 |
0x0000 0108 |
0x4002 1108 |
|
RW |
32 |
0x0000 0000 |
0x0000 0120 |
0x4002 1120 |
|
RW |
32 |
0x0000 0000 |
0x0000 0124 |
0x4002 1124 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0130 |
0x4002 1130 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0134 |
0x4002 1134 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0138 |
0x4002 1138 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 013C |
0x4002 113C |
|
RW |
32 |
0xFFFF FFFF |
0x0000 01D0 |
0x4002 11D0 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 01D4 |
0x4002 11D4 |
|
RW |
32 |
0x0000 0003 |
0x0000 0210 |
0x4002 1210 |
|
RW |
32 |
0x0000 0001 |
0x0000 0214 |
0x4002 1214 |
|
RW |
32 |
0x0000 0001 |
0x0000 0218 |
0x4002 1218 |
|
RW |
32 |
0x0000 0002 |
0x0000 03B0 |
0x4002 13B0 |
|
RW |
32 |
0x0000 0000 |
0x0000 03B4 |
0x4002 13B4 |
|
RO |
32 |
0x0000 0000 |
0x0000 03D0 |
0x4002 13D0 |
|
RO |
32 |
0x0001 0000 |
0x0000 03D4 |
0x4002 13D4 |
|
RO |
32 |
0x0000 0000 |
0x0000 03D8 |
0x4002 13D8 |
|
RO |
32 |
0x0000 0000 |
0x0000 03DC |
0x4002 13DC |
|
RO |
32 |
0x0002 0800 |
0x0000 03F0 |
0x4002 13F0 |
|
RO |
32 |
0x0004 0080 |
0x0000 03F4 |
0x4002 13F4 |
|
RO |
32 |
0x0000 0001 |
0x0000 03F8 |
0x4002 13F8 |
|
RO |
32 |
0x0000 0100 |
0x0000 0400 |
0x4002 1400 |
|
RO |
32 |
0x0001 0102 |
0x0000 0404 |
0x4002 1404 |
|
RO |
32 |
0x0000 0100 |
0x0000 0410 |
0x4002 1410 |
|
RO |
32 |
0x0001 0102 |
0x0000 0414 |
0x4002 1414 |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4002 1028 | Instance | 0x4002 1028 |
Description | Interrupt Mask Register: The IMASK register holds the current interrupt mask settings. Masked interrupts are read in the MIS register. PSD compliant register. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED_31_1 | Reserved | RW | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | DONE | Interrupt mask for DONE: 0: Interrupt is disabled in MIS register 1: Interrupt is enabled in MIS register
|
RW | 0 |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x4002 1030 | Instance | 0x4002 1030 |
Description | Raw Interrupt Status Register: The RIS register reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing a 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled. A flag can be set by software by writing a 1 to the ISET register. Reading the IIDX register will also clear the corresponding bit in RIS. PSD compliant register. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED_31_1 | Reserved | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | DONE | Flash wrapper operation completed. This interrupt bit is set by firmware or the corresponding bit in the ISET register. It is cleared by the corresponding bit in in the ICLR register or reading the IIDX register when this interrupt is the highest priority.
|
RO | 0 |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x4002 1038 | Instance | 0x4002 1038 |
Description | Masked Interrupt Status Register: The MIS register is a bit-wise AND of the contents of the IMASK and RIS registers. This is kept mainly for ARM compatibility, and has limited use since the highest priority interrupt index is returned through the IIDX register. PSD compliant register. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED_31_1 | Reserved | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | DONE | Flash wrapper operation completed. This masked interrupt bit reflects the bitwise AND of the corresponding RIS and IMASK bits.
|
RO | 0 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x4002 1040 | Instance | 0x4002 1040 |
Description | Interrupt Set Register: The ISET register allows software to write a 1 to set corresponding interrupt. Safety: This meets a safety requirement to allow software diagnostics to trigger interrupts. PSD compliant register. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED_31_1 | Reserved | WO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | DONE | 0: No effect 1: Set the DONE interrupt in the RIS register
|
WO | 0 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4002 1048 | Instance | 0x4002 1048 |
Description | Interrupt Clear Register. The ICLR register allows allows software to write a 1 to clear corresponding interrupt. PSD compliant register. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED_31_1 | Reserved | WO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | DONE | 0: No effect 1: Clear the DONE interrupt in the RIS register
|
WO | 0 |
Address Offset | 0x0000 00FC | ||
Physical Address | 0x4002 10FC | Instance | 0x4002 10FC |
Description | Hardware Version Description Register: This register identifies the flash wrapper hardware version and feature set used. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:16 | MODULEID | Module ID
|
RO | 0x0B40 | |||||||||||
15:12 | FEATUREVER | Feature set
|
RO | 0x4 | |||||||||||
11:8 | INSTNUM | Instance number
|
RO | 0x0 | |||||||||||
7:4 | MAJREV | Major Revision
|
RO | 0x1 | |||||||||||
3:0 | MINREV | Minor Revision
|
RO | 0x0 |
Address Offset | 0x0000 0100 | ||
Physical Address | 0x4002 1100 | Instance | 0x4002 1100 |
Description | Command Execute Register: Initiates execution of the command specified in the CMDTYPE register. This register is blocked for writes after being written to 1 and prior to STATCMD.DONE being set by the flash wrapper hardware. flash wrapper hardware clears this register after the processing of the command has completed. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED_31_1 | Reserved | RW | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | VAL | Command Execute value Initiates execution of the command specified in the CMDTYPE register.
|
RW | 0 |
Address Offset | 0x0000 0104 | ||
Physical Address | 0x4002 1104 | Instance | 0x4002 1104 |
Description | Command Type Register This register specifies the type of command to be executed by the flash wrapper hardware. This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by the hardware to indicate that command execution has completed. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||
31:7 | RESERVED_31_7 | Reserved | RW | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||
6:4 | SIZE | Command size
|
RW | 0b000 | ||||||||||||||||||||||||||
3 | RESERVED_3 | Reserved | RW | 0 | ||||||||||||||||||||||||||
2:0 | COMMAND | Command type
|
RW | 0b000 |
Address Offset | 0x0000 0108 | ||
Physical Address | 0x4002 1108 | Instance | 0x4002 1108 |
Description | Command Control Register This register configures specific capabilities of the state machine for related to the execution of a command. This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by the hardware to indicate that command execution has completed. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||
31:22 | RESERVED_31_22 | Reserved | RW | 0b00 0000 0000 | ||||||||||||||||||||||||||||||||||||||
21 | DATAVEREN | Enable invalid data verify. This checks for 0->1 transitions in the memory when a program operation is initiated. If such a transition is found, the program will fail with an error without executing the program.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||
20 | SSERASEDIS | Disable Stair-Step Erase. If set, the default VHV trim voltage setting will be used for all erase pulses. By default, this bit is reset, meaning that the VHV voltage will be stepped during successive erase pulses. The step count, step voltage, begin and end voltages are all hard-wired.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||
19:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||||||||||||||||||||||||||||||||||||||
16 | ADDRXLATEOVR | Override hardware address translation of address in CMDADDR from a system address to a bank address and bank ID. Use data written to CMDADDR directly as the bank address. Use the value written to CMDCTL.BANKSEL directly as the bank ID. Use the value written to CMDCTL.REGIONSEL directly as the region ID.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||
15:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||||||||||||||||||||||||||||||||||||||
13 | RESERVED_13 | Reserved | RW | 0 | ||||||||||||||||||||||||||||||||||||||
12:9 | REGIONSEL | Bank Region A specific region ID can be written to this field to indicate to which region an operation is to be applied if CMDCTL.ADDRXLATEOVR is set.
|
RW | 0x0 | ||||||||||||||||||||||||||||||||||||||
8:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||||||||||||||||||||||||||||||||||||||
5:4 | BANKSEL | Bank Select A specific Bank ID can be written to this field to indicate to which bank an operation is to be applied if CMDCTL.ADDRXLATEOVR is set.
|
RW | 0b00 | ||||||||||||||||||||||||||||||||||||||
3:0 | MODESEL | Mode This field is only used for the Mode Change command type. Otherwise, bank and pump modes are set automaticlly through the NW hardware.
|
RW | 0x0 |
Address Offset | 0x0000 0120 | ||
Physical Address | 0x4002 1120 | Instance | 0x4002 1120 |
Description | Command Address Register: This register forms the target address of a command. The use cases are as follows: 1) For single-word program, this address indicates the flash bank word to be programmed. 2) For multi-word program, this address indicates the first flash bank address for the program. The address will be incremented for further words. 3) For sector erase, this address indicates the sector to be erased. 4) For bank erase, the address indicates the bank to be erased. 5) For read verify, the address indications follow program/erase listed above. Note the address written to this register will be submitted for translation to the flash wrapper address translation interface, and the translated address will be used to access the bank. However, if the CMDCTL.ADDRXLATEOVR bit is set, then the address written to this register will be used directly as the bank address. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the flash wrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | Address value
|
RW | 0x0000 0000 |
Address Offset | 0x0000 0124 | ||
Physical Address | 0x4002 1124 | Instance | 0x4002 1124 |
Description | Command Program Byte Enable Register: This register forms a per-byte enable for programming data. For data bytes to be programmed, a 1 must be written to the corresponding bit in this register. Normally, all bits are written to 1, allowing program of full flash words. However, leaving some bits 0 allows programming of 8-bit, 16-bit, 32-bit or 64-bit portions of a flash word. In addtion, the read verify command will ignore data bytes read from the flash in its comparison if the corresponding CMDBYTEN bit is 0. ECC data bytes are protected by the 1-2 MSB bits in this register, depending on the presence of ECC and the flash word data width. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the flash wrapper hardware. This register is written to all 0 after the completion of all flash wrapper commands. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:18 | RESERVED_31_18 | Reserved | RW | 0b00 0000 0000 0000 | |||||||||||
17:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||
15:0 | VAL | Command Byte Enable value. A 1-bit per flash word byte value is placed in this register.
|
RW | 0x0000 |
Address Offset | 0x0000 0130 | ||
Physical Address | 0x4002 1130 | Instance | 0x4002 1130 |
Description | Command Data Register 0 This register forms the data for a command. For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 0. For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 0. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the flash wrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all flash wrapper commands. Use cases for the CMDDATA* registers are as follows: 1) Program - These registers contain the data to be programmed. 2) Erase - These registers are not used. 3) Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0134 | ||
Physical Address | 0x4002 1134 | Instance | 0x4002 1134 |
Description | Command Data Register 1 This register forms the data for a command. For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 0. For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 0. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to CMDSTAT.DONE being set by the flash wrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all flash wrapper commands. Use cases for the CMDDATA* registers are as follows: 1) Program - These registers contain the data to be programmed. 2) Erase - These registers are not used. 3) Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0138 | ||
Physical Address | 0x4002 1138 | Instance | 0x4002 1138 |
Description | Command Data Register 2 This register forms the data for a command. For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 0. For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 1. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the flash wrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all flash wrapper commands. Use cases for the CMDDATA* registers are as follows: 1) Program - These registers contain the data to be programmed. 2) Erase - These registers are not used. 3) Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 013C | ||
Physical Address | 0x4002 113C | Instance | 0x4002 113C |
Description | Command Data Register 3 This register forms the data for a command. For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 0. For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 1. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the flash wrapper hardware. This register is used to aggregate masking for bits that do not require additional program pulses during program operations, and will be written to all 1 after the completion of all flash wrapper commands. Use cases for the CMDDATA* registers are as follows: 1) Program - These registers contain the data to be programmed. 2) Erase - These registers are not used. 3) Read Verify - These registers contain data to be verified. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | A 32-bit data value is placed in this field.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 01D0 | ||
Physical Address | 0x4002 11D0 | Instance | 0x4002 11D0 |
Description | Command WriteErase Protect A Register This register allows the first 32 sectors of the main region to be protected from program or erase, with 1 bit protecting each sector. If the main region size is smaller than 32 sectors, then this register provides protection for the whole region. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the flash wrapper hardware. In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all flash wrapper commands. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | Each bit protects 1 sector. bit [0]: When 1, sector 0 of the flash memory will be protected from program and erase. bit [1]: When 1, sector 1 of the flash memory will be protected from program and erase. : : bit [31]: When 1, sector 31 of the flash memory will be protected from program and erase.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 01D4 | ||
Physical Address | 0x4002 11D4 | Instance | 0x4002 11D4 |
Description | Command WriteErase Protect B Register This register allows main region sectors to be protected from program and erase. Each bit corresponds to a group of 8 sectors. There are 3 cases for how these protect bits are applied: 1. Single-bank system: In the case where only a single flash bank is present, the first 32 sectors are protected via the CMDWEPROTA register. Thus, the protection give by the bits in CMDWEPROTB begin with sector 32. 2. Multi-bank system, Bank 0: When multiple flash banks are present, the first 32 sectors of bank 0 are protected via the CMDWEPROTA register. Thus, only bits 4 and above of CMDWEPROTB would be applicable to bank 0. The protection of bit 4 and above would begin at sector 32. Bits 3:0 of WEPROTB are ignored for bank 0. 3. Multi-bank system, Banks 1-N: For banks other than bank 0 in a multi-bank system, CMDWEPROTA has no effect, so the bits in CMDWEPROTB will protect these banks starting from sector 0. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the flash wrapper hardware. In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all flash wrapper commands. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:0 | VAL | Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. A maximum of 256 sectors can be protected with this register.
|
RW | 0xFFFF FFFF |
Address Offset | 0x0000 0210 | ||
Physical Address | 0x4002 1210 | Instance | 0x4002 1210 |
Description | Command WriteErase Protect Non-Main Register This register allows non-main region region sectors to be protected from program and erase. Each bit corresponds to 1 sector. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the flash wrapper hardware. In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all flash wrapper commands. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
1:0 | VAL | Each bit protects 1 sector. bit [0]: When 1, sector 0 of the non-main region will be protected from program and erase. bit [1]: When 1, sector 1 of the non-main region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the non-main will be protected from program and erase.
|
RW | 0b11 |
Address Offset | 0x0000 0214 | ||
Physical Address | 0x4002 1214 | Instance | 0x4002 1214 |
Description | Command WriteErase Protect Trim Register This register allows trim region sectors to be protected from program and erase. Each bit corresponds to 1 sector. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the flash wrapper hardware. In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all flash wrapper commands. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | VAL | Each bit protects 1 sector. bit [0]: When 1, sector 0 of the engr region will be protected from program and erase. bit [1]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the engr region will be protected from program and erase.
|
RW | 1 |
Address Offset | 0x0000 0218 | ||
Physical Address | 0x4002 1218 | Instance | 0x4002 1218 |
Description | Command WriteErase Protect Engr Register This register allows engr region sectors to be protected from program and erase. Each bit corresponds to 1 sector. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the flash wrapper hardware. In addition, this register is used to aggregate masking for sectors that do not require additional erase pulses during bank erase operations, and will be written to all 1 after the completion of all flash wrapper commands. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | VAL | Each bit protects 1 sector. bit [0]: When 1, sector 0 of the engr region will be protected from program and erase. bit [1]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the engr region will be protected from program and erase.
|
RW | 1 |
Address Offset | 0x0000 03B0 | ||
Physical Address | 0x4002 13B0 | Instance | 0x4002 13B0 |
Description | Command Configuration Register This register configures specific capabilities of the state machine for related to the execution of a command. This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by the hardware to indicate that command execution has completed. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:7 | RESERVED_31_7 | Reserved | RW | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||
6:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
3:0 | WAITSTATE | Wait State setting for program verify, erase verify and read verify
|
RW | 0x2 |
Address Offset | 0x0000 03B4 | ||
Physical Address | 0x4002 13B4 | Instance | 0x4002 13B4 |
Description | Pulse Counter Configuration Register This register allows further configuration of maximum pulse counts for program and erase operations. This register is blocked for writes after a 1 is written to the CMDEXEC register and prior to STATCMD.DONE being set by the flash wrapper hardware. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | |||||||||||
19:17 | RESERVED_17_19 | Reserved | RW | 0b000 | |||||||||||
16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
15:12 | RESERVED_15_12 | Reserved | RW | 0x0 | |||||||||||
11:4 | MAXPCNTVAL | Override maximum pulse counter with this value. If MAXPCNTOVR = 0, then this field is ignored. If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used to override the max pulse count for both program and erase. Full max value will be {4'h0, MAXPCNTVAL} . If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for program only. Full max value will be {4'h0, MAXPCNTVAL}.
|
RW | 0x00 | |||||||||||
3:1 | RESERVED_3_1 | Reserved | RW | 0b000 | |||||||||||
0 | MAXPCNTOVR | Override hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count setting for program. By default, this bit is 0, and a hard-wired max pulse count is used.
|
RW | 0 |
Address Offset | 0x0000 03D0 | ||
Physical Address | 0x4002 13D0 | Instance | 0x4002 13D0 |
Description | Command Status Register This register contains status regarding completion and errors of command execution. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:13 | RESERVED_31_13 | Reserved | RO | 0b000 0000 0000 0000 0000 | |||||||||||
12 | FAILMISC | Command failed due to error other than write/erase protect violation or verify error. This is an extra bit in case a new failure mechanism is added which requires a status bit.
|
RO | 0 | |||||||||||
11:9 | RESERVED_11_9 | Reserved | RO | 0b000 | |||||||||||
8 | FAILINVDATA | Program command failed because an attempt was made to program a stored 0 value to a 1.
|
RO | 0 | |||||||||||
7 | FAILMODE | Command failed because a bank has been set to a mode other than READ. Program and Erase commands cannot be initiated unless all banks are in READ mode.
|
RO | 0 | |||||||||||
6 | FAILILLADDR | Command failed due to the use of an illegal address
|
RO | 0 | |||||||||||
5 | FAILVERIFY | Command failed due to verify error
|
RO | 0 | |||||||||||
4 | FAILWEPROT | Command failed due to Write/Erase Protect Sector Violation
|
RO | 0 | |||||||||||
3 | RESERVED_3 | Reserved | RO | 0 | |||||||||||
2 | CMDINPROGRESS | Command In Progress
|
RO | 0 | |||||||||||
1 | CMDPASS | Command Pass - valid when CMD_DONE field is 1
|
RO | 0 | |||||||||||
0 | CMDDONE | Command Done
|
RO | 0 |
Address Offset | 0x0000 03D4 | ||
Physical Address | 0x4002 13D4 | Instance | 0x4002 13D4 |
Description | Current Address Counter Value Read only register giving read access to the state machine current address. A bank id, region id and address are stored in this register and are incremented as necessary during execution of a command. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||
31:26 | RESERVED_31_26 | Reserved | RO | 0b00 0000 | ||||||||||||||||||||
25:21 | BANKID | Current Bank ID A bank indicator is stored in this register which represents the current bank on which the state machine is operating. There is 1 bit per bank.
|
RO | 0b0 0000 | ||||||||||||||||||||
20:16 | REGIONID | Current Region ID A region indicator is stored in this register which represents the current flash region on which the state machine is operating.
|
RO | 0b0 0001 | ||||||||||||||||||||
15:0 | BANKADDR | Current Bank Address A bank offset address is stored in this register.
|
RO | 0x0000 |
Address Offset | 0x0000 03D8 | ||
Physical Address | 0x4002 13D8 | Instance | 0x4002 13D8 |
Description | Current Pulse Count Register: Read only register giving read access to the state machine current pulse count value for program/erase operations. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED_31_12 | Reserved | RO | 0x0 0000 | |||||||||||
11:0 | PULSECNT | Current Pulse Counter Value
|
RO | 0x000 |
Address Offset | 0x0000 03DC | ||
Physical Address | 0x4002 13DC | Instance | 0x4002 13DC |
Description | Mode Status Register Indicates one or more banks which not in READ mode, and it indicates the mode which the bank(s) are in. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||
31:18 | RESERVED_31_18 | Reserved | RO | 0b00 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||
17 | BANK1TRDY | Bank 1T Ready. Bank(s) are ready for 1T access. This is accomplished when the bank and pump have been trimmed.
|
RO | 0 | ||||||||||||||||||||||||||||||||||||||
16 | BANK2TRDY | Bank 2T Ready. Bank(s) are ready for 2T access. This is accomplished when the pump has fully driven power rails to the bank(s).
|
RO | 0 | ||||||||||||||||||||||||||||||||||||||
15:12 | RESERVED_15_12 | Reserved | RO | 0x0 | ||||||||||||||||||||||||||||||||||||||
11:8 | BANKMODE | Indicates mode of bank(s) that are not in READ mode
|
RO | 0x0 | ||||||||||||||||||||||||||||||||||||||
7:5 | RESERVED_7_5 | Reserved | RO | 0b000 | ||||||||||||||||||||||||||||||||||||||
4:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||||||||||||||||||||||||||||||||||||||
1:0 | BANKNOTINRD | Bank not in read mode. Indicates which banks are not in READ mode. There is 1 bit per bank.
|
RO | 0b00 |
Address Offset | 0x0000 03F0 | ||
Physical Address | 0x4002 13F0 | Instance | 0x4002 13F0 |
Description | Global Info 0 Register Read only register detailing information about sector size and number of banks present. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:19 | RESERVED_31_19 | Reserved | RO | 0b0 0000 0000 0000 | |||||||||||
18:16 | NUMBANKS | Number of banks instantiated Minimum: 1 Maximum: 5
|
RO | 0b010 | |||||||||||
15:0 | SECTORSIZE | Sector size in bytes
|
RO | 0x0800 |
Address Offset | 0x0000 03F4 | ||
Physical Address | 0x4002 13F4 | Instance | 0x4002 13F4 |
Description | Global Info 1 Register Read only register detailing information about data, ecc and redundant data widths in bits. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:19 | RESERVED_31_19 | Reserved | RO | 0b0 0000 0000 0000 | ||||||||||||||
18:16 | REDWIDTH | Redundant data width in bits
|
RO | 0b100 | ||||||||||||||
15:13 | RESERVED_15_13 | Reserved | RO | 0b000 | ||||||||||||||
12:8 | ECCWIDTH | ECC data width in bits
|
RO | 0b0 0000 | ||||||||||||||
7:0 | DATAWIDTH | Data width in bits
|
RO | 0x80 |
Address Offset | 0x0000 03F8 | ||
Physical Address | 0x4002 13F8 | Instance | 0x4002 13F8 |
Description | Global Info 2 Register Read only register detailing information about the number of data registers present. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:4 | RESERVED_31_4 | Reserved | RO | 0x000 0000 | |||||||||||
3:0 | DATAREGISTERS | Number of data registers present.
|
RO | 0x1 |
Address Offset | 0x0000 0400 | ||
Physical Address | 0x4002 1400 | Instance | 0x4002 1400 |
Description | Bank Info 0 Register for bank 0. Read only register detailing information about Main region size in the bank. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED_31_12 | Reserved | RO | 0x0 0000 | |||||||||||
11:0 | MAINSIZE | Main region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512)
|
RO | 0x100 |
Address Offset | 0x0000 0404 | ||
Physical Address | 0x4002 1404 | Instance | 0x4002 1404 |
Description | Bank Info1 Register for bank 0. Read only register detailing information about Non-Main, Trim, and Engr region sizes in the bank. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:24 | RESERVED_31_24 | Reserved | RO | 0x00 | |||||||||||
23:16 | ENGRSIZE | Engr region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)
|
RO | 0x01 | |||||||||||
15:8 | TRIMSIZE | Trim region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)
|
RO | 0x01 | |||||||||||
7:0 | NONMAINSIZE | Non-main region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)
|
RO | 0x02 |
Address Offset | 0x0000 0410 | ||
Physical Address | 0x4002 1410 | Instance | 0x4002 1410 |
Description | Bank Info 0 Register for bank 1. Read only register detailing information about Main region size in the bank. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:12 | RESERVED_31_12 | Reserved | RO | 0x0 0000 | |||||||||||
11:0 | MAINSIZE | Main region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512)
|
RO | 0x100 |
Address Offset | 0x0000 0414 | ||
Physical Address | 0x4002 1414 | Instance | 0x4002 1414 |
Description | Bank Info1 Register for bank 1. Read only register detailing information about Non-Main, Trim, and Engr region sizes in the bank. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:24 | RESERVED_31_24 | Reserved | RO | 0x00 | |||||||||||
23:16 | ENGRSIZE | Engr region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)
|
RO | 0x01 | |||||||||||
15:8 | TRIMSIZE | Trim region size in sectors
|
RO | 0x01 | |||||||||||
7:0 | NONMAINSIZE | Non-main region size in sectors
|
RO | 0x02 |
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