Instance: SPI1
Component: SPI
Base address: 0x40031000
Serial Peripheral Interface (SPI) module with peripheral and controller capabilities.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x604D 1010 |
0x0000 0000 |
0x4003 1000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x4003 1044 |
|
RO |
32 |
0x0000 0000 |
0x0000 0048 |
0x4003 1048 |
|
RO |
32 |
0x0000 0000 |
0x0000 004C |
0x4003 104C |
|
WO |
32 |
0x0000 0000 |
0x0000 0050 |
0x4003 1050 |
|
WO |
32 |
0x0000 0000 |
0x0000 0054 |
0x4003 1054 |
|
WO |
32 |
0x0000 0000 |
0x0000 0058 |
0x4003 1058 |
|
WO |
32 |
0x0000 0000 |
0x0000 005C |
0x4003 105C |
|
RW |
32 |
0x0000 0000 |
0x0000 0060 |
0x4003 1060 |
|
RW |
32 |
0x0000 0000 |
0x0000 0100 |
0x4003 1100 |
|
RW |
32 |
0x0000 0004 |
0x0000 0104 |
0x4003 1104 |
|
RW |
32 |
0x0000 0000 |
0x0000 0108 |
0x4003 1108 |
|
RW |
32 |
0x0000 0000 |
0x0000 010C |
0x4003 110C |
|
RW |
32 |
0x0000 0202 |
0x0000 0110 |
0x4003 1110 |
|
RW |
32 |
0x0000 0000 |
0x0000 0114 |
0x4003 1114 |
|
RW |
32 |
0x0000 0000 |
0x0000 0118 |
0x4003 1118 |
|
RW |
32 |
0x0000 0000 |
0x0000 011C |
0x4003 111C |
|
WO |
32 |
0x0000 0000 |
0x0000 0120 |
0x4003 1120 |
|
WO |
32 |
0x0000 0000 |
0x0000 0124 |
0x4003 1124 |
|
WO |
32 |
0x0000 0000 |
0x0000 0128 |
0x4003 1128 |
|
WO |
32 |
0x0000 0000 |
0x0000 012C |
0x4003 112C |
|
RW |
32 |
0x0000 0000 |
0x0000 0130 |
0x4003 1130 |
|
RO |
32 |
0x0000 0000 |
0x0000 0140 |
0x4003 1140 |
|
RW |
32 |
0x0000 0000 |
0x0000 0150 |
0x4003 1150 |
|
RW |
32 |
0x0000 000F |
0x0000 0160 |
0x4003 1160 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4003 1000 | Instance | 0x4003 1000 |
Description | Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | MODID | Module identifier used to uniquely identify this IP. | RW | 0x604D | ||
15:12 | STDIPOFF | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) |
RW | 0x1 | ||
11:8 | INSTIDX | IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15). | RW | 0x0 | ||
7:4 | MAJREV | Major revision of IP (0-15). | RW | 0x1 | ||
3:0 | MINREV | Minor revision of IP (0-15). | RW | 0x0 |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x4003 1044 | Instance | 0x4003 1044 |
Description | Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | DMATX | DMA Done TX event mask.
|
RW | 0 | |||||||||||
7 | DMARX | DMA Done RX event mask.
|
RW | 0 | |||||||||||
6 | IDLE | SPI Idle event mask.
|
RW | 0 | |||||||||||
5 | TXEMPTY | Transmit FIFO Empty event mask.
|
RW | 0 | |||||||||||
4 | TX | Transmit FIFO event mask.
|
RW | 0 | |||||||||||
3 | RX | Receive FIFO event.
|
RW | 0 | |||||||||||
2 | RTOUT | SPI Receive Time-Out event mask.
|
RW | 0 | |||||||||||
1 | PER | Parity error event mask.
|
RW | 0 | |||||||||||
0 | RXOVF | RXFIFO overflow event mask.
|
RW | 0 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4003 1048 | Instance | 0x4003 1048 |
Description | Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | DMATX | DMA Done event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the TX DMA event inside SPI.
|
RW | 0 | |||||||||||
7 | DMARX | DMA Done event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows handling of the DMA RX event inside SPI.
|
RW | 0 | |||||||||||
6 | IDLE | SPI has completed transfers and moved to IDLE mode. This bit is set when STA.BUSY goes low.
|
RW | 0 | |||||||||||
5 | TXEMPTY | Transmit FIFO Empty interrupt mask. This interrupt is set when all data in the Transmit FIFO has been moved to the shift register.
|
RW | 0 | |||||||||||
4 | TX | Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
|
RW | 0 | |||||||||||
3 | RX | Receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
|
RW | 0 | |||||||||||
2 | RTOUT | SPI Receive Time-Out event. This interrupt is set if no activity is detected on the input clock line within the time period dictated by CTL1.RTOUT value. This is applicable only in peripheral mode.
|
RW | 0 | |||||||||||
1 | PER | Parity error event. This bit is set if a Parity error has been detected
|
RW | 0 | |||||||||||
0 | RXOVF | RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
|
RW | 0 |
Address Offset | 0x0000 004C | ||
Physical Address | 0x4003 104C | Instance | 0x4003 104C |
Description | Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | DMATX | Masked DMA Done event for TX.
|
RW | 0 | |||||||||||
7 | DMARX | Masked DMA Done event for RX.
|
RW | 0 | |||||||||||
6 | IDLE | Masked SPI IDLE event.
|
RW | 0 | |||||||||||
5 | TXEMPTY | Masked Transmit FIFO Empty event.
|
RW | 0 | |||||||||||
4 | TX | Masked Transmit FIFO event.
|
RW | 0 | |||||||||||
3 | RX | Masked receive FIFO event.
|
RW | 0 | |||||||||||
2 | RTOUT | Masked SPI Receive Time-Out event.
|
RW | 0 | |||||||||||
1 | PER | Masked Parity error event.
|
RW | 0 | |||||||||||
0 | RXOVF | Masked RXFIFO overflow event.
|
RW | 0 |
Address Offset | 0x0000 0050 | ||
Physical Address | 0x4003 1050 | Instance | 0x4003 1050 |
Description | Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | DMATX | Set DMA Done event for TX.
|
RW | 0 | |||||||||||
7 | DMARX | Set DMA Done event for RX.
|
RW | 0 | |||||||||||
6 | IDLE | Set SPI IDLE event.
|
RW | 0 | |||||||||||
5 | TXEMPTY | Set Transmit FIFO Empty event.
|
RW | 0 | |||||||||||
4 | TX | Set Transmit FIFO event.
|
RW | 0 | |||||||||||
3 | RX | Set Receive FIFO event.
|
RW | 0 | |||||||||||
2 | RTOUT | Set SPI Receive Time-Out Event.
|
RW | 0 | |||||||||||
1 | PER | Set Parity error event.
|
RW | 0 | |||||||||||
0 | RXOVF | Set RXFIFO overflow event.
|
RW | 0 |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x4003 1054 | Instance | 0x4003 1054 |
Description | Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | DMATX | Clear DMA Done event for TX.
|
RW | 0 | |||||||||||
7 | DMARX | Clear DMA Done event for RX.
|
RW | 0 | |||||||||||
6 | IDLE | Clear SPI IDLE event.
|
RW | 0 | |||||||||||
5 | TXEMPTY | Clear Transmit FIFO Empty event.
|
RW | 0 | |||||||||||
4 | TX | Clear Transmit FIFO event.
|
RW | 0 | |||||||||||
3 | RX | Clear Receive FIFO event.
|
RW | 0 | |||||||||||
2 | RTOUT | Clear SPI Receive Time-Out Event.
|
RW | 0 | |||||||||||
1 | PER | Clear Parity error event.
|
RW | 0 | |||||||||||
0 | RXOVF | Clear RXFIFO overflow event.
|
RW | 0 |
Address Offset | 0x0000 0058 | ||
Physical Address | 0x4003 1058 | Instance | 0x4003 1058 |
Description | Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding IMASK bit. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | DMATX | Set DMA Done for TX event mask
|
RW | 0 | |||||||||||
7 | DMARX | Set DMA Done for RX event mask
|
RW | 0 | |||||||||||
6 | IDLE | Set SPI IDLE event mask
|
RW | 0 | |||||||||||
5 | TXEMPTY | Set Transmit FIFO Empty event mask
|
RW | 0 | |||||||||||
4 | TX | Set Transmit FIFO event mask
|
RW | 0 | |||||||||||
3 | RX | Set Receive FIFO event mask
|
RW | 0 | |||||||||||
2 | RTOUT | Set SPI Receive Time-Out event mask
|
RW | 0 | |||||||||||
1 | PER | Set Parity error event mask
|
RW | 0 | |||||||||||
0 | RXOVF | Set RXFIFO overflow event mask
|
RW | 0 |
Address Offset | 0x0000 005C | ||
Physical Address | 0x4003 105C | Instance | 0x4003 105C |
Description | Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding IMASK bit. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | DMATX | Clear DMA Done for TX event mask
|
RW | 0 | |||||||||||
7 | DMARX | Clear DMA Done for RX event mask
|
RW | 0 | |||||||||||
6 | IDLE | Clear SPI IDLE event mask
|
RW | 0 | |||||||||||
5 | TXEMPTY | Clear Transmit FIFO Empty event mask
|
RW | 0 | |||||||||||
4 | TX | Clear Transmit FIFO event mask
|
RW | 0 | |||||||||||
3 | RX | Clear Receive FIFO event mask
|
RW | 0 | |||||||||||
2 | RTOUT | Clear SPI Receive Time-Out event mask
|
RW | 0 | |||||||||||
1 | PER | Clear Parity error event mask
|
RW | 0 | |||||||||||
0 | RXOVF | Clear RXFIFO overflow event mask
|
RW | 0 |
Address Offset | 0x0000 0060 | ||
Physical Address | 0x4003 1060 | Instance | 0x4003 1060 |
Description | Emulation control register. This register controls the behavior of the IP related to core halted input. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
0 | HALT | Halt control
|
RW | 0 |
Address Offset | 0x0000 0100 | ||
Physical Address | 0x4003 1100 | Instance | 0x4003 1100 |
Description | SPI control register 0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||
31:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||
17 | IDLEPOCI | The Idle value of POCI - when TXFIFO is empty and before data is written into TXFIFO - can be controlled by this field.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||
16 | GPCRCEN | General purpose CRC enable. This bit enables transmit side CRC unit for general purpose use by software when SPI is disabled (CTL1.EN = 0). This bit must be 0 when SPI is enabled.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||
15 | CRCPOLY | CRC polynomial selection.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||
14 | AUTOCRC | Auto insert CRC
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||
13 | CRCEND | CRC16 Endianness
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||
12 | CSCLR | Clear shift register counter on CS inactive. This bit is relevant only in the peripheral mode, when CTL1.MS=0.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||
11 | FIFORST | This bit is used to reset transmit and receive FIFO pointers. This bit is auto cleared once the FIFO pointer reset operation is completed.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||
10 | HWCSN | Hardware controlled chip select (CS) value. When set CS is zero till TX FIFO is empty, as in - a. CS is de-asserted b. All data bytes are transmitted c. CS is asserted
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||
9 | SPH | SCLK phase (Motorola SPI frame format only). This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture clock edge.
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||
8 | SPO | SCLK polarity (Motorola SPI frame format only).
|
RW | 0 | ||||||||||||||||||||||||||||||||||||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||||||||||||||||||||||||||||||||||||||||||||
6:5 | FRF | Frame format select
|
RW | 0b00 | ||||||||||||||||||||||||||||||||||||||||||||
4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||||||||||||||||||||||||||||||||||||||||||||
3:0 | DSS | Data size select. The applicable DSS values for controller mode operation are 0x3 to 0xF and for peripheral mode operation are 0x6 to 0xF. DSS values 0x0 to 0x2 are reserved and must not be used.
|
RW | 0x0 |
Address Offset | 0x0000 0104 | ||
Physical Address | 0x4003 1104 | Instance | 0x4003 1104 |
Description | SPI control register 1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:30 | RESERVED30 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||
29:24 | RTOUT | Receive Timeout (only for Peripheral mode) Defines the number of CLKSVT clock cycles after which the Receive Timeout flag RIS.RTOUT is set. A value of 0 disables this function. |
RW | 0b00 0000 | |||||||||||
23:16 | REPTX | Counter to repeat last transfer (only in controller mode) 0: repeat last transfer is disabled. x: repeat the last transfer with the provided value. The transfer will be started with writing a data into the TX FIFO. Sending the data will be repeated REPTX number of times, so the data will be transferred x+1 times in total. It can be used to clean a transfer or to pull a certain amount of data by a peripheral.
|
RW | 0x00 | |||||||||||
15:12 | CDMODE | Commnd Data Mode. This bit field value determines the behavior of C/D or CS signal when CDEN = 1. CS pin held low indicates command phase and CS pin held high indicates data phase. When CDMODE = 0x0, the CS pin is always held high during transfer indicating data phase only operation (manual mode). When CDMODE = 0xF, the CS pin is always held low during transfer indicating command phase only operation (manual mode). When CDMODE = 0x1 to 0xE, the CS pin is held low for the number of bytes indicated by CDMODE value for the command phase and held high for the remaining transfers in the data phase (automatic mode). When CDMODE is set to value 0x1 to 0xE, reading CDMODE during operation indicates the remaining bytes to be transferred in the command phase.
|
RW | 0x0 | |||||||||||
11 | CDEN | Command/Data mode enable. This feature is applicable only in controller mode and for 8-bit transfers (CTL0.DSS = 7). The chip select pin is used for command/data signaling in Motorola SPI frame format (3-wire) operation.
|
RW | 0 | |||||||||||
10:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | |||||||||||
7 | PBS | Parity bit select
|
RW | 0 | |||||||||||
6 | PES | Even parity select.
|
RW | 0 | |||||||||||
5 | PEN | Parity enable. If enabled the last bit will be used as parity to evaluate the correct reception of the previous bits. In case of parity mismatch the parity error flag RIS.PER will be set. This feature is available only in SPI controller mode.
|
RW | 0 | |||||||||||
4 | MSB | MSB first select. Controls the direction of receive and transmit shift register. MSB first configuration (MSB = 1) must be selected when CRC feature is used for SPI communication.
|
RW | 0 | |||||||||||
3 | POD | Peripheral data output disable. This bit is relevant only in the peripheral mode, MS=1. In multiple-peripheral systems, it is possible for a SPI controller to broadcast a message to all peripherals in the system while ensuring that only one peripheral drives data onto its serial output line. In such systems the POCI lines from multiple peripherals could be tied together. To operate in such systems, this bit field can be set if the SPI peripheral is not supposed to drive the POCI output.
|
RW | 0 | |||||||||||
2 | MS | Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.EN=0.
|
RW | 1 | |||||||||||
1 | LBM | Loop back mode control
|
RW | 0 | |||||||||||
0 | EN | SPI enable. NOTE: This bit field must be set to 1 using a separate write access, after the other bit fields have been configured.
|
RW | 0 |
Address Offset | 0x0000 0108 | ||
Physical Address | 0x4003 1108 | Instance | 0x4003 1108 |
Description | Clock configuration register 0. This register is used to configure the clock prescaler. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
2:0 | PRESC | Prescaler configuration
|
RW | 0b000 |
Address Offset | 0x0000 010C | ||
Physical Address | 0x4003 110C | Instance | 0x4003 110C |
Description | Clock configuration register 1. This register is used to configure serial clock rate and clock count for delayed sampling in controller mode. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | ||
19:16 | DSAMPLE | Delayed sampling. In controller mode the data on the POCI pin will be delayed sampled by the defined CLKSVT clock cycles. DSAMPLE values can range from 0 to SCR+1. Typically, values of 1 or 2 would suffice. | RW | 0x0 | ||
15:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | ||
9:0 | SCR | Serial clock divider. This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate: (SPI functional clock frequency)/((SCR+1)*2). SCR value can be from 0 to 1023. |
RW | 0b00 0000 0000 |
Address Offset | 0x0000 0110 | ||
Physical Address | 0x4003 1110 | Instance | 0x4003 1110 |
Description | Interrupt FIFO level select register. This register can be used to define the levels at which the RIS.TX, RIS.RX flags are triggered. The interrupts are generated based on FIFO level. Out of reset, the IFLS.TXSEL and IFLS.RXSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
10:8 | RXSEL | Receive FIFO Level Select. The trigger points for the receive interrupt are as follows:
|
RW | 0b010 | |||||||||||||||||||||||||||||
7:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 | |||||||||||||||||||||||||||||
2:0 | TXSEL | Transmit FIFO Level Select. The trigger points for the transmit interrupt are as follows:
|
RW | 0b010 |
Address Offset | 0x0000 0114 | ||
Physical Address | 0x4003 1114 | Instance | 0x4003 1114 |
Description | uDMA Control Register | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
8 | TXEN | Transmit DMA enable. If this bit is set to 1, DMA for the trasmit FIFO is enabled.
|
RW | 0 | |||||||||||
7:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | |||||||||||
0 | RXEN | Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
|
RW | 0 |
Address Offset | 0x0000 0118 | ||
Physical Address | 0x4003 1118 | Instance | 0x4003 1118 |
Description | Receive CRC register. Reading this register provides the computed CRC value from the receive side CRC unit. Reading this register or writing to this register with any value auto initializes the seed. The seed value is 0xFF when CTL0.CRCPOLY = 0 and 0xFFFF when CTL0.CRCPOLY = 1 for CCITT CRC polynomials. Bits[15:8] are don't care when CTL0.CRCPOLY = 0. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | DATA | CRC value SW should read RXCRC register at the end of data transmission to reinitiaze the seed value to all ones |
RW | 0x0000 |
Address Offset | 0x0000 011C | ||
Physical Address | 0x4003 111C | Instance | 0x4003 111C |
Description | Transmit CRC register. Reading this register provides the computed CRC value from the transmit side CRC unit. Reading this register or writing to this register with any value auto initializes the seed. The seed value is 0xFF when CTL0.CRCPOLY = 0 and 0xFFFF when CTL0.CRCPOLY = 1 for CCITT CRC polynomials. Bits[15:8] are don't care when CTL0.CRCPOLY = 0. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31 | AUTOCRCINS | Status to indicate if Auto CRC has been inserted into TXFIFO. This is applicable only if CTL0.AUTOCRC enable bit is set. SW should read TXCRC register to clear auto inserted CRC at the end of the transfer.
|
RO | 0 | |||||||||||
30:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 | |||||||||||
15:0 | DATA | CRC value | RW | 0x0000 |
Address Offset | 0x0000 0120 | ||
Physical Address | 0x4003 1120 | Instance | 0x4003 1120 |
Description | Header update reigster for 32 bits of header data into the TXFIFO. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | DATA | This field can be used to write four bytes of header data into the TXFIFO | WO | 0x0000 0000 |
Address Offset | 0x0000 0124 | ||
Physical Address | 0x4003 1124 | Instance | 0x4003 1124 |
Description | Header update reigster for 24 bits of header data into the TXFIFO. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | DATA | This field can be used to write three bytes of header data into the TXFIFO. | WO | 0x0000 0000 |
Address Offset | 0x0000 0128 | ||
Physical Address | 0x4003 1128 | Instance | 0x4003 1128 |
Description | Header update reigster for 16 bits of data into the TXFIFO. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | DATA | This field can be used to write two bytes of header data into the TXFIFO. | WO | 0x0000 0000 |
Address Offset | 0x0000 012C | ||
Physical Address | 0x4003 112C | Instance | 0x4003 112C |
Description | Header update reigster for 8 bits of header data into the TXFIFO. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | DATA | This field can be used to write one byte of header data into the TXFIFO. | WO | 0x0000 0000 |
Address Offset | 0x0000 0130 | ||
Physical Address | 0x4003 1130 | Instance | 0x4003 1130 |
Description | Atomic Header Control register | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||
3 | CSGATE | Chip Select Gating control register. If this bit is set, header update register writes are blocked when chip select (CS) is active low, and HDRIGN bit is set. This bit resets to 0.
|
RW | 0 | |||||||||||
2 | HDRCMT | Header Committed field. This bit is set when the HDREN bit is set and CS is sampled low. This bit remains 0 otherwise. When set, this bit can be written to a value of 0 to clear.
|
RW | 0 | |||||||||||
1 | HDRIGN | Header Ignored field. When CSGATE is set to BLK, this bit is set when the last Header update register TXFHDRn is written when CS is low or HDRCMT is already set. When CSGATE is set to UNBLK, this bit is set only when the header update register is written when HDRCMT is already set. This bit remains 0 otherwise. When set, this bit can be written to a value of 0 to clear.
|
RW | 0 | |||||||||||
0 | HDREN | Header enable field. When CSGATE is set to BLK, this bit has to be set by software to enable atomic header feature. When CSGATE is set to UNBLK, this field is set automatically whenever a write to header update registers TXFHDRn occurs.
|
RW | 0 |
Address Offset | 0x0000 0140 | ||
Physical Address | 0x4003 1140 | Instance | 0x4003 1140 |
Description | RXDATA Register. Reading this register returns first value in the RX FIFO. If the FIFO is empty the last read value is returned. Writing has no effect and is ignored. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | DATA | Received Data. When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer is accessed. As data values are read by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current RX FIFO write pointer. Received data less than 16 bits is automatically right-justified in the receive buffer. |
RO | 0x0000 |
Address Offset | 0x0000 0150 | ||
Physical Address | 0x4003 1150 | Instance | 0x4003 1150 |
Description | TXDATA Register. Writing a value in this register puts the data into the TX FIFO. Reading this register returns the last writen value. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | DATA | Transmit Data. When read, the last entry in the transmit FIFO, pointed to by the current FIFO write pointer is accessed. When written, the entry in the TX FIFO pointed to by the write pointer, is written to. Data values are read from the transmit FIFO by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. |
RW | 0x0000 |
Address Offset | 0x0000 0160 | ||
Physical Address | 0x4003 1160 | Instance | 0x4003 1160 |
Description | Status Register | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 | |||||||||||
13:8 | TXFIFOLVL | Indicates how many locations of TXFIFO are currently filled with data | RO | 0b00 0000 | |||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
6 | TXDONE | Transmit done. Indicates whether the last bit has left the Shift register after a transmission
|
RW | 0 | |||||||||||
5 | CSD | Detection of CS deassertion in the middle of a data frame transmission results in this error being set. This feature is only available in the peripheral mode.
|
RW | 0 | |||||||||||
4 | BUSY | SPI Busy status
|
RO | 0 | |||||||||||
3 | RNF | Receive FIFO not full status.
|
RO | 1 | |||||||||||
2 | RFE | Receive FIFO empty status.
|
RO | 1 | |||||||||||
1 | TNF | Transmit FIFO not full status.
|
RO | 1 | |||||||||||
0 | TFE | Transmit FIFO empty status.
|
RO | 1 |
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