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Data Structures | |
struct | SDFM_CfgSdClk |
Structure defining SDFM clock configuration parameters. More... | |
struct | SDFM_CfgTrigger |
Structure defining SDFM triggered mode trigger times. More... | |
struct | SDFM_CfgIep |
Structure defining SDFM IEP configuration. More... | |
struct | SDFM_GpioParams |
Structure defining SDFM base address and values to toggle GPIO pins. More... | |
struct | SDFM_ChCtrl |
Structure defining SDFM channel control fields. More... | |
struct | SDFM_ClkSourceParms |
Structure defining clk source for sdfm ch. More... | |
struct | SDFM_ThresholdParms |
Structure defining SDFM thresholds parametrs. More... | |
struct | SDFM_Cfg |
Structure defining SDFM configuration interface. More... | |
struct | SDFM_Ctrl |
Structure defining SDFM control fields. More... | |
struct | SDFM_Interface |
struct | SDFM |
Structure defining SDFM interface. More... | |
#define PRU_ICSSG_DRAM0_SLV_RAM ( CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE ) |
ICSSG DMEM0/1 base addresses.
#define PRU_ICSSG_DRAM1_SLV_RAM ( CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE ) |
#define DEF_SD_CH_CTRL_CH_EN ( 0 ) /* default all chs disabled */ |
SD channel control, channel disable/enable.
#define BF_CH_EN_MASK ( 0x1 ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH0_EN_SHIFT ( 0 ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH0_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH0_EN_SHIFT ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH1_EN_SHIFT ( 1 ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH1_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH1_EN_SHIFT ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH2_EN_SHIFT ( 2 ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH2_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH2_EN_SHIFT ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH3_EN_SHIFT ( 3 ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH3_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH3_EN_SHIFT ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH4_EN_SHIFT ( 4 ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH4_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH4_EN_SHIFT ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH5_EN_SHIFT ( 5 ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH5_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH5_EN_SHIFT ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH6_EN_SHIFT ( 6 ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH6_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH6_EN_SHIFT ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH7_EN_SHIFT ( 7 ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH7_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH7_EN_SHIFT ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH8_EN_SHIFT ( 8 ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH8_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH8_EN_SHIFT ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH9_EN_SHIFT ( 9 ) |
#define SDFM_CH_CTRL_CH_EN_BF_CH9_EN_MASK ( BF_CH_EN_MASK << SDFM_CH_CTRL_CH_EN_BF_CH9_EN_SHIFT ) |
#define SDFM_CH_CTRL_CH_EN_SHIFT ( SDFM_CH_CTRL_CH_EN_BF_CH0_EN_SHIFT ) |
#define SDFM_CH_CTRL_CH_EN_MASK |
#define SDFM_MAIN_FILTER_MASK ( 1 ) |
#define SDFM_MAIN_FILTER_SHIFT ( 0 ) |
#define SDFM_MAIN_INTERRUPT_MASK ( 1 ) |
#define SDFM_MAIN_INTERRUPT_SHIFT ( 1 ) |
#define SDFM_RECFG_REINIT ( SDFM_RECFG_BF_RECFG_REINIT_MASK ) |
reinitialize PRU SDFM
#define SDFM_RECFG_CLK ( SDFM_RECFG_BF_RECFG_CLK_MASK ) |
reconfigure SD clock
#define SDFM_RECFG_OSR ( SDFM_RECFG_BF_RECFG_OSR_MASK ) |
reconfigure SD OSR
#define SDFM_RECFG_TRIG_SAMP_TIME ( SDFM_RECFG_BF_RECFG_TRIG_SAMPLE_TIME_MASK ) |
reconfigure Trigger mode sample time
#define SDFM_RECFG_TRIG_SAMP_CNT ( SDFM_RECFG_BF_RECFG_TRIG_SAMPLE_CNT_MASK ) |
reconfigure Trigger mode sample count
#define SDFM_RECFG_CH_EN ( 1<<6 ) |
reconfigure SD channel disable/enable
#define SDFM_RECFG_FD ( SDFM_RECFG_BF_RECFG_FD_MASK ) |
reconfigure SD channel disable/enable
#define SDFM_RECFG_TRIG_OUT_SAMP_BUF ( SDFM_RECFG_BF_RECFG_TRIG_OUT_SAMP_BUF_MASK ) |
reconfigure Trigger mode output sample buffer
#define IEP_DEFAULT_INC 0x1 |
IEP_CFG.
#define ICSSG_SD_SAMP_CH_BUF_SZ ( 128 ) |
#define NUM_CH_SUPPORTED ( 3 ) |