SDL ECC SEC

Introduction

This example takes an aggregator index as input from the user and performs single bit error test for the corresponding aggregator. It involves the following steps:

  • Setup of an ESM application callback to receive Single Error Correction (SEC) and setup of ECC Aggregators in general

  • Triggering of ECC events for all the RAM IDs, including Interconnect type and Wrapper type

  • Capturing ESM interrupt and ECC error details in the application callbacks for subsequent reporting, including the interrupt level, ESM source, RAM ID, and bit error information

Aggregators Supported

The following aggregators can be tested using this example.

Aggregator Index

ECC Aggregator

0

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0

1

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1

2

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE2

3

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE3

4

SDL_COMPUTE_CLUSTER0_SAM62_A53_512KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC

5

SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR

6

SDL_DMASS0_DMSS_AM62_ECCAGGR

7

SDL_ECC_AGGR0_SAM62_SEC_ECC_AGGR

8

SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR

9

SDL_GICSS0_GIC500SS_1_4_ECC_AGGR

10

SDL_ICSSM0_ICSS_M_CORE_BORG_ECC_AGGR

11

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

12

SDL_MCU_ECC_AGGR0_SAM62_MCU_ECC_AGGR

13

SDL_MCU_M4FSS0_BLAZAR_ECC

14

SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

15

SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

16

SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM

17

SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM

18

SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM

19

SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM

20

SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM

21

SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM

22

SDL_PDMA0_SAM62_PDMA_SPI_ECCAGGR

23

SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR

24

SDL_PSRAMECC_16K0_PSRAM16KX32E_ECC_AGGR

25

SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR

26

SDL_SA3_SS0_SA3SS_AM62_DMSS_ECCAGGR

27

SDL_SA3_SS0_SA3SS_AM62_SA_UL_ECC_AGGR

28

SDL_SMS0_SMS_HSM_ECC

29

SDL_SMS0_SMS_TIFS_ECC

30

SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR

31

SDL_USB1_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR

32

SDL_WKUP_ECC_AGGR0_SAM62_DM_ECC_AGGR

33

SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR

34

SDL_WKUP_SAFE_ECC_AGGR0_SAM62_WKUP_SAFE_ECC_AGGR

35

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR

36

SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR

Supported Combinations

Parameter

Value

CPU + OS

r5fss0-0 nortos

CPU + OS

m4fss0-0 nortos

Toolchain

ti-arm-clang

Board

am62x-sk

Example folder

examples/sdl/ecc_sec/

Steps to Run the Example

Sample Output

Shown below is a sample output when the application is run for a couple of aggregators,

[MAIN_Cortex_R5_0_0] Sciclient direct init..... SUCCESS

ECC Example Application

ECC_Test_init: Init MCU ESM complete

ECC_Test_init: Init MAIN ESM complete

ECC_Test_init: ECC Callback Init complete for MCU ESM

ECC_Test_init: ECC Callback Init complete for Main ESM

ECC SDL API tests: starting

Refer the User Guide for the aggregator information

Select the memory to test...
14

...selected 14

ecc_aggrtest: [14] single bit error self test: SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR starting

ECC_Memory_init: [14] SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR ECC Init complete

Self test started accessable RamId 0  starting

Self Test completed for accessable RamId 0

Self test started RamId 1  starting

Self test started RamId 1  completed

Select the memory to test...
20

...selected 20

ecc_aggrtest: [20] single bit error self test: SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM starting

ECC_Memory_init: [20] SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM ECC Init complete

Inject test started not accessable RamId 0 starting

Injected ECC error and got ESM Interrupt

Select the memory to test...