gpadc/v0/gpadc.h

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/*
 * Copyright (C) 2021-23 Texas Instruments Incorporated
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *   Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 *
 *   Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the
 *   distribution.
 *
 *   Neither the name of Texas Instruments Incorporated nor the names of
 *   its contributors may be used to endorse or promote products derived
 *   from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef GPADC_H_
#define GPADC_H_
 
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
 
#include <drivers/hw_include/cslr_soc.h>
#include <kernel/dpl/HwiP.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ========================================================================== */
/*                             Macros & Typedefs                              */
/* ========================================================================== */
 
#define GPADC_DISABLE               (0U)
 
#define GPADC_ENABLE                (1U)
 
#define GPADC_ASSERT_RESET          (1U)
 
#define GPADC_DEASSERT_RESET        (0U)
 
#define GPADC_FSM_ASSERT_RESET      (0x7U)
 
#define GPADC_FSM_DEASSERT_RESET    (0U)
 
#define GPADC_MODE_DISABLE        (0U)
 
#define GPADC_MODE_IFM            (1U)
 
#define GPADC_MODE_CTM            (2U)
 
#define GPADC_MON_INSTR_RAM_ST_IND    (224U)
 
#define GPADC_MAX_MON_INSTR_RAM       (32U)
 
#define MAX_CTM_GPADC_PARAMS        (1U)
 
#define GPADC_TIMEOUT_MAX         (200000U)
 
#define GPADC_REGS_PTR            ((T_GPADC_REGS*)CSL_MSS_GPADC_REG_U_BASE)
 
#define GPADCPKTRAM_REGS_PTR      ((T_GPADCPKTRAM_REGS*)CSL_MSS_GPADC_PKT_RAM_U_BASE)
 
#define GPADCOUT_RAM_PTR          ((T_GPADCOUT_RAM*)CSL_MSS_GPADC_DATA_RAM_U_BASE)
 
#define MSS_GPADC_RST_CTRL_ADDR     (CSL_MSS_RCM_U_BASE + CSL_MSS_RCM_MSS_GPADC_RST_CTRL)
 
#define MSS_GPADC_RST_CTRL_PTR      ((MSS_GPADC_RST_CTRL_REG*)MSS_GPADC_RST_CTRL_ADDR)
 
#define MSS_GPADC_CLK_DIV_VAL_ADDR  (CSL_MSS_RCM_U_BASE + CSL_MSS_RCM_MSS_GPADC_CLK_DIV_VAL)
 
#define MSS_GPADC_CLK_DIV_VAL_PTR   ((MSS_GPADC_CLK_DIV_VAL_REG*)MSS_GPADC_CLK_DIV_VAL_ADDR)
 
#define MSS_GPADC_CLK_GATE_ADDR     (CSL_MSS_RCM_U_BASE + CSL_MSS_RCM_MSS_GPADC_CLK_GATE)
 
#define MSS_GPADC_CLK_GATE_PTR      ((MSS_GPADC_CLK_GATE_REG*)MSS_GPADC_CLK_GATE_ADDR)
 
#define MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_ADDR (CSL_MSS_TOPRCM_U_BASE + CSL_MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV)
 
#define MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_PTR  ((MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_REG*)MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_ADDR)
 
#define MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_ADDR (CSL_MSS_TOPRCM_U_BASE + CSL_MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV)
 
#define MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_PTR  ((MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_REG*)MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_ADDR)
 
#define MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_ADDR (CSL_MSS_TOPRCM_U_BASE + CSL_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV)
 
#define MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_PTR  ((U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG*)MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_ADDR)
 
#define MSS_CTRL_MSS_GPADC_MEM_INIT_ADDR    (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_MSS_GPADC_MEM_INIT)
 
#define MSS_CTRL_MSS_GPADC_MEM_INIT_PTR     ((MSS_CTRL_MSS_GPADC_MEM_INIT_REG*)MSS_CTRL_MSS_GPADC_MEM_INIT_ADDR)
 
#define REG_STRUCT_SWRITE(w_hwRegStruct, w_regVal, w_regWrSts)   \
                do { (w_hwRegStruct) = (w_regVal); \
                     REG32_SCOMPARE((w_hwRegStruct), (w_regVal), (w_regWrSts)); \
                   } while (0)
 
#define REG32_SCOMPARE(w_hwVal, w_swVal, w_regWrSts)  \
                do { \
                     (w_regWrSts) |= (((uint32_t)(w_swVal)) ^ ((uint32_t)(w_hwVal))); \
                   } while (0)
 
#define REG_STRUCT_SCLEAR(w_hwRegStruct, w_regVal, w_regWrSts)   \
                do { (w_hwRegStruct) = (w_regVal); \
                     (w_regWrSts) |= ((((uint32_t)(w_hwRegStruct)) & (uint32_t)(w_regVal))); \
                   } while (0)
 
/* ========================================================================== */
/*                         Structures and Enums                               */
/* ========================================================================== */
 
typedef enum
{
    GPADC_TRIG_SRC_GPIO_0 = 0,
    GPADC_TRIG_SRC_GPIO_1,
    GPADC_TRIG_SRC_GPIO_2,
    GPADC_TRIG_SRC_GPIO_3,
    GPADC_TRIG_SRC_RSS_CSI2A_EOL_INT,
    GPADC_TRIG_SRC_RSS_CSI2A_SOF_INT0,
    GPADC_TRIG_SRC_RSS_CSI2A_SOF_INT1,
    GPADC_TRIG_SRC_RSS_CSI2A_SOF_INT,
    GPADC_TRIG_SRC_RSS_CSI2B_SOF_INT,
    GPADC_TRIG_SRC_HW_Sync_FE1,
    GPADC_TRIG_SRC_HW_Sync_FE2,
    GPADC_TRIG_SRC_DSS_RTIA_1,
    GPADC_TRIG_SRC_DSS_RTIB_1,
    GPADC_TRIG_SRC_MSS_RTIA_INT1,
    GPADC_TRIG_SRC_MSS_RTIB_INT1,
    GPADC_TRIG_SRC_MMR_Based_SW_Trigger
}GPADC_CtmTrigSrcType;
 
typedef enum
{
    GPADC_ONESHOT_CONV_MODE = 0,
 
    GPADC_CONTINUOUS_CONV_MODE
}GPADC_ChannelConvModeType;
 
typedef enum
{
    GPADC_TRIGG_SRC_SW = 0,
    GPADC_TRIGG_SRC_HW
}GPADC_TriggerSourceType;
 
typedef enum
{
    GPADC_MEAS_EXT_CH1 = 0,
    GPADC_MEAS_EXT_CH2,
    GPADC_MEAS_EXT_CH3,
    GPADC_MEAS_EXT_CH4,
    GPADC_MEAS_EXT_CH5,
    GPADC_MEAS_EXT_CH6,
    GPADC_MEAS_EXT_CH7,
    GPADC_MEAS_EXT_CH8,
    GPADC_MEAS_EXT_CH9,
    MAX_GPADC_MEAS_SOURCES
}GPADC_MeasExtSrcType;
 
typedef enum
{
    GPADC_CONV_ERROR = 0,
    GPADC_CONV_DONE,
    GPADC_CONV_CHANNEL_CONFIG_MISSING
}GPADC_ConvResultType;
 
typedef enum
{
    GPADC_IDLE,
    GPADC_BUSY,
    GPADC_COMPLETED
}GPADC_StatusType;
 
typedef enum
{
    GPADC_DIG_DSP_TEMP_SENSOR = 0,
    GPADC_DIG_HWA_TEMP_SENSOR ,
    GPADC_DIG_HSM_TEMP_SENSOR ,
    MAX_GPADC_TEMP_SENSORS
}GPADC_TempSensorSrcType;
 
typedef struct
{
    GPADC_MeasExtSrcType  channelID;
 
    uint32_t channelConfigValue;
 
    uint8_t channelParamValue;
 
    Bool     isConfigured;
    Bool     isBufferedMode;
    uint32_t skipSamples;
    uint8_t  collectSamples;
    Bool     useLuTable;
}GPADC_ChannelConfigType;
 
typedef struct
{
    GPADC_ChannelConvModeType        convMode;
    GPADC_TriggerSourceType          triggSrc;
    GPADC_ChannelConfigType   channelConfig[MAX_GPADC_MEAS_SOURCES];
}GPADC_ConfigType;
 
typedef union
{
    struct
    {
        uint32_t b8_ParamValue             : 8;    /*  bits  7:  0  */
        uint32_t b8_CollectSamples         : 8;    /*  bits 15:  8  */
        /* Skip samples = Mantissa[3:0] * 2^(Exponent[6:4]) */
        uint32_t b7_SkipSamples            : 7;    /*  bits 22: 16 - */
        uint32_t b9_Reserved               : 9;    /*  bits 31: 23 - */
    } bits;
    uint32_t b32_Val;
}GPADC_ParamInfoType;
 
typedef union
{
    struct
    {
        uint16_t b9_ChannelSelectionBitMap             : 9;    /*  bits  8:  0  */
        uint16_t b7_Reserved                           : 7;    /*  bits  15: 9  */
    } bits;
    uint16_t b16_Val;
}GPADC_channelsGroupSelectType;
 
typedef struct
{
    Bool                  isChannelBufferedMode;
    uint32_t              channelConfigValue;
    GPADC_ParamInfoType   channelParamValue;
    Bool                  isChannelConfigured;
}GPADC_DriverChannelConfigType;
 
typedef struct
{
    GPADC_ChannelConvModeType        convMode;
    GPADC_TriggerSourceType          triggSrc;
    GPADC_StatusType                 driverStatus;
    GPADC_DriverChannelConfigType   driverChannelConfig[MAX_GPADC_MEAS_SOURCES];
    uint16_t                        *ResultBufferPtr;
}GPADC_DriverObjectType;
 
typedef struct
{
    uint32_t channelConfigValue;
    uint8_t channelParamValue;
    uint32_t skipSamples;
    uint8_t  collectSamples;
} GPADC_TempSensMuxType;
 
typedef struct
{
   int16_t     DigDspTempValue;
   int16_t     DigHwaTempValue;
   int16_t     DigHsmTempValue;
} GPADC_TempSensValueType;
 
typedef struct
{
    uint32_t b3_Assert                    :   3;           
    uint32_t b29_Nu1                      :  29;         
} MSS_GPADC_RST_CTRL_REG;
 
typedef struct
{
    uint32_t b24_Clkdivr                    :  24;           
    uint32_t b8_Nu1                         :  8;         
} MSS_GPADC_CLK_DIV_VAL_REG;
 
typedef struct
{
    uint32_t b3_Gated                     :   3;           
    uint32_t b29_Nu1                      :  29;         
} MSS_GPADC_CLK_GATE_REG;
 
typedef struct
{
    uint32_t b30_Reserved1                     : 30;           
    uint32_t b1_ClkTmuxEsdCtrl                 :  1;           
    uint32_t b1_AnaTestEn                      :  1;           
} MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_REG;
 
typedef struct
{
    uint32_t b30_Reserved1                     : 31;           
    uint32_t b1_AnaogTestTmuxEsdCtrl           :  1;           
} MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_REG;
 
typedef struct
{
    uint32_t b1_AdcEn                          :  1;           
    uint32_t b1_AdcStartConv                   :  1;           
    uint32_t b1_AdcReset                       :  1;           
    uint32_t b1_AdcInpBufEn                    :  1;           
    uint32_t b1_AdcRefBufEn                    :  1;           
    uint32_t b3_AdcRefSel_2_0                  :  3;           
    uint32_t b1_TsDiffInpBufEn                 :  1;           
    uint32_t b1_TsSeInpBufEn                   :  1;           
    uint32_t b1_IforceExtCtrl                  :  1;           
    uint32_t b1_VrefExtCtrl                    :  1;           
    uint32_t b1_VinExtCtrl                     :  1;           
    uint32_t b1_AnaTmuxBufBypass               :  1;           
    uint32_t b1_AnaTmuxBufEn                   :  1;           
    uint32_t b5_RtrimTw_4_0                    :  5;           
    uint32_t b12_Reserved1                     : 12;           
} U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG;
 
 
typedef struct
{
    uint32_t b2_DcbistMode                :  2;           
    uint32_t b6_Nu1                       :  6;           
    uint32_t b1_GpadcFsmClkEnable         :  1;           
    uint32_t b3_Gpadc2adcbufPathEn        :  3;           
    uint32_t b4_Nu2                       :  4;           
    uint32_t b1_GpadcDebugModeEnable      :  1;           
    uint32_t b15_Nu3                      : 15;           
} GPADCREG_REG0;
 
typedef struct
{
    uint32_t b1_GpadcTrigger              :  1;           
    uint32_t b7_Nu1                       :  7;           
    uint32_t b1_GpadcInit                 :  1;           
    uint32_t b7_Nu2                       :  7;           
    uint32_t b1_GpadcFsmBypass            :  1;           
    uint32_t b7_Nu3                       :  7;           
    uint32_t b1_GpadcStartBypVal          :  1;           
    uint32_t b7_Nu4                       :  7;           
} GPADCREG_REG1;
 
typedef struct
{
    uint32_t b32_ConfigValueIfm           : 32;           
} GPADCREG_REG2;
 
typedef union
{
    struct
    {
        uint32_t b8_ParamValIfm               :  8;           
        uint32_t b8_CollectSamplesIfm         :  8;           
        uint32_t b7_SkipSamplesIfm            :  7;           
        uint32_t b9_Nu                        :  9;           
    } bits;  
    uint32_t b32_Reg;  
} U_GPADCREG_REG3;
 
typedef union
{
    struct
    {
        uint32_t b8_PktRamBaseAddrCp0         :  8;           
        uint32_t b8_PktRamBaseAddrCp1         :  8;           
        uint32_t b8_PktRamBaseAddrCp2         :  8;           
        uint32_t b8_PktRamBaseAddrCp3         :  8;           
    } bits;  
    uint32_t b32_Reg;  
} U_GPADCREG_REG4;
 
typedef struct
{
    uint32_t b8_PktRamBaseAddrCp4         :  8;           
    uint32_t b8_PktRamBaseAddrCp5         :  8;           
    uint32_t b8_PktRamBaseAddrCp6         :  8;           
    uint32_t b8_PktRamBaseAddrCp7         :  8;           
} GPADCREG_REG5;
 
typedef struct
{
    uint32_t b8_PktRamBaseAddrCp8         :  8;           
    uint32_t b8_PktRamBaseAddrCp9         :  8;           
    uint32_t b8_PktRamBaseAddrCp10        :  8;           
    uint32_t b8_PktRamBaseAddrCp11        :  8;           
} GPADCREG_REG6;
 
typedef struct
{
    uint32_t b8_PktRamBaseAddrCp12        :  8;           
    uint32_t b8_PktRamBaseAddrCp13        :  8;           
    uint32_t b8_PktRamBaseAddrCp14        :  8;           
    uint32_t b8_PktRamBaseAddrCp15        :  8;           
} GPADCREG_REG7;
 
typedef struct
{
    uint32_t b8_GpadcClkDiv               :  8;           
    uint32_t b1_GpadcClkEnable            :  1;           
    uint32_t b23_Nu                       : 23;           
} GPADCREG_REG8;
 
typedef struct
{
    uint32_t b32_ParamNotUsedTxEna1Off    : 32;           
} GPADCREG_REG9;
 
typedef struct
{
    uint32_t b32_ParamNotUsedTxEna2Off    : 32;           
} GPADCREG_REG10;
 
typedef struct
{
    uint32_t b32_ParamNotUsedTxEna3Off    : 32;           
} GPADCREG_REG11;
 
typedef struct
{
    uint32_t b1_DramEccEnable             :  1;           
    uint32_t b7_Nu1                       :  7;           
    uint32_t b1_DramEccErrClr             :  1;           
    uint32_t b7_Nu2                       :  7;           
    uint32_t b8_DramEccErrAddr            :  8;           
    uint32_t b8_DramRepairedBit           :  8;           
} GPADCREG_REG12;
 
typedef struct
{
    uint32_t b32_SpareWr2                 : 32;           
} GPADCREG_REG13;
 
typedef struct
{
    uint32_t b20_SumIfm                   : 20;           
    uint32_t b12_Nu                       : 12;           
} GPADCREG_REG14;
 
typedef struct
{
    uint32_t b10_MinGpadc                 : 10;           
    uint32_t b6_Nu1                       :  6;           
    uint32_t b10_MaxGpadc                 : 10;           
    uint32_t b6_Nu2                       :  6;           
} GPADCREG_REG15;
 
typedef struct
{
    uint32_t b1_GpadcMemInitDoneStat      :  1;           
    uint32_t b31_Nu                       : 31;           
} GPADCREG_REG16;
 
typedef struct
{
    uint32_t b1_GpadcIfmDoneStatus        :  1;           
    uint32_t b31_Nu                       : 31;           
} GPADCREG_REG17;
 
typedef struct
{
    uint32_t b1_GpadcIfmDoneClr           :  1;           
    uint32_t b31_Nu                       : 31;           
} GPADCREG_REG18;
 
typedef struct
{
    uint32_t b16_GpadcSamplesFrame        : 16;           
    uint32_t b16_Nu                       : 16;           
} GPADCREG_REG19;
 
typedef struct
{
    uint32_t b32_SpareRd1                 : 32;           
} GPADCREG_REG20;
 
typedef struct
{
    uint32_t b32_SpareRd2                 : 32;           
} GPADCREG_REG21;
 
typedef struct
{
    uint32_t b32_SpareWr1                 : 32;           
} GPADCREG_REG22;
 
 
typedef volatile struct
{
    GPADCREG_REG0                       r_Reg0              ;        
    GPADCREG_REG1                       r_Reg1              ;        
    GPADCREG_REG2                       r_Reg2              ;        
    U_GPADCREG_REG3                     r_Reg3              ;        
    U_GPADCREG_REG4                     r_PacketRamAdd[4]   ;        
    GPADCREG_REG8                       r_Reg8              ;        
    GPADCREG_REG9                       r_Reg9              ;        
    GPADCREG_REG10                      r_Reg10             ;        
    GPADCREG_REG11                      r_Reg11             ;        
    GPADCREG_REG12                      r_Reg12             ;        
    GPADCREG_REG13                      r_Reg13             ;        
    GPADCREG_REG14                      r_Reg14             ;        
    GPADCREG_REG15                      r_Reg15             ;        
    GPADCREG_REG16                      r_Reg16             ;        
    GPADCREG_REG17                      r_Reg17             ;        
    GPADCREG_REG18                      r_Reg18             ;        
    GPADCREG_REG19                      r_Reg19             ;        
    GPADCREG_REG20                      r_Reg20             ;        
    GPADCREG_REG21                      r_Reg21             ;        
    GPADCREG_REG22                      r_Reg22             ;        
} T_GPADC_REGS;
 
typedef struct
{
    uint32_t b1_mem0_init                 :   1;         
    uint32_t b31_Reserved                 :  31;         
} MSS_CTRL_MSS_GPADC_MEM_INIT_REG;
 
typedef struct
{
    uint32_t             UnbuffConfigValue;
    uint32_t             BuffConfigValue;
    GPADC_ParamInfoType  ParamInfo;
    uint16_t             TotalTime;
}GPADC_CfgAndParamValuesType;
 
typedef struct
{
    uint16_t Avg;
    uint16_t Min;
    uint16_t Max;
    uint32_t Sum;
}GPADC_ResultType;
 
 
/* ========================================================================== */
/*                  Internal/Private Structure Declarations                   */
/* ========================================================================== */
 
 
/* ========================================================================== */
/*                         Global Variables Declarations                      */
/* ========================================================================== */
 
 
/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
 
void GPADC_init(void);
 
void GPADC_deinit(void);
 
int32_t GPADC_open(GPADC_ConfigType *CfgPtr);
 
int32_t GPADC_close(void);
 
 GPADC_ConvResultType GPADC_startGroupConversion(GPADC_channelsGroupSelectType channels, uint8_t numChannels);
 
GPADC_ConvResultType GPADC_startSingleChannelConversion(GPADC_MeasExtSrcType channelID, uint16_t *gpadcValue);
 
int32_t GPADC_stopConversion(void);
 
int32_t GPADC_setupResultBuffer(uint16_t * ResBufferPtr);
 
int32_t GPADC_readResultBuffer(uint16_t *ResBufferPtr);
 
GPADC_StatusType GPADC_getStatus(void);
 
int32_t GPADC_readTemperature(uint8_t numAverages, uint8_t numChannels, GPADC_TempSensValueType * tempValuesPtr);
 
void GPADC_initTempMeasurement(void);
 
/* ========================================================================== */
/*                       Static Function Definitions                          */
/* ========================================================================== */
 
/* None */
 
#ifdef __cplusplus
}
#endif
 
#endif  /* #ifndef GPADC_H_ */