AM273x MCU+ SDK  08.02.00
hwa/v0/hwa.h
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1 /*
2  * Copyright (C) 2021 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  */
33 
67 #ifndef HWA_H_
68 #define HWA_H_
69 
70 /* ========================================================================== */
71 /* Include Files */
72 /* ========================================================================== */
73 
74 #include <stdint.h>
75 #include <stddef.h>
76 #include <stdbool.h>
77 #include <drivers/hw_include/csl_complex_math_types.h>
78 #include <kernel/dpl/HwiP.h>
79 #include <drivers/hw_include/cslr_hwa.h>
80 
81 #ifdef __cplusplus
82 extern "C" {
83 #endif
84 
85 /* ========================================================================== */
86 /* Macros & Typedefs */
87 /* ========================================================================== */
88 
90 #define HWADRV_ADDR_TRANSLATE_CPU_TO_HWA(x) (uint32_t)((uint32_t)(x) & 0x000FFFFFU)
91 
99 #define HWA_ERRNO_BASE (-2800)
100 
101 #define HWA_EINVAL (HWA_ERRNO_BASE-1)
102 
103 #define HWA_ENOINIT (HWA_ERRNO_BASE-2)
104 
105 #define HWA_EOUTOFRANGE (HWA_ERRNO_BASE-3)
106 
107 #define HWA_EOUTOFMEM (HWA_ERRNO_BASE-4)
108 
109 #define HWA_ENOTSUPP (HWA_ERRNO_BASE-5)
110 
111 #define HWA_EINUSE (HWA_ERRNO_BASE-6)
112 
113 #define HWA_ENOTALIGNED (HWA_ERRNO_BASE-7)
114 
115 #define HWA_EINVAL_COMMON_REGISTER_PARAMSET (HWA_ERRNO_BASE-8)
116 
117 #define HWA_EINVAL_COMMON_REGISTER_PARAMSET_ALT (HWA_ERRNO_BASE-9)
118 
119 #define HWA_EINVAL_COMMON_REGISTER_FFTCONFIG (HWA_ERRNO_BASE-10)
120 
121 #define HWA_EINVAL_COMMON_REGISTER_DCEST (HWA_ERRNO_BASE-11)
122 
123 #define HWA_EINVAL_COMMON_REGISTER_CFAR (HWA_ERRNO_BASE-12)
124 
125 #define HWA_EINVAL_COMMON_REGISTER_INTERFERENCE (HWA_ERRNO_BASE-13)
126 
127 #define HWA_EINVAL_COMMON_REGISTER_COMPLEXMULT (HWA_ERRNO_BASE-14)
128 
129 #define HWA_EINVAL_COMMON_REGISTER_CHANCOMB (HWA_ERRNO_BASE-15)
130 
131 #define HWA_EINVAL_COMMON_REGISTER_ZEROINSERT (HWA_ERRNO_BASE-16)
132 
133 #define HWA_EINVAL_COMMON_REGISTER_ADVSTAT (HWA_ERRNO_BASE-17)
134 
135 #define HWA_EINVAL_COMMON_REGISTER_COMPRESS (HWA_ERRNO_BASE-18)
136 
137 #define HWA_EINVAL_COMMON_REGISTER_LOCALMAXIMUM (HWA_ERRNO_BASE-19)
138 
139 #define HWA_EINVAL_PARAMSET_GENERALCONFIG (HWA_ERRNO_BASE - 20)
140 
141 #define HWA_EINVAL_PARAMSET_SOURCE (HWA_ERRNO_BASE - 21)
142 
143 #define HWA_EINVAL_PARAMSET_DEST (HWA_ERRNO_BASE - 22)
144 
145 #define HWA_EINVAL_PARAMSET_SRCDST_ADDRESS (HWA_ERRNO_BASE - 23)
146 
147 #define HWA_EINVAL_PARAMSET_FFTMODE_GENERALCONFIG (HWA_ERRNO_BASE - 24)
148 
149 #define HWA_EINVAL_PARAMSET_FFTMODE_SIZE (HWA_ERRNO_BASE - 25)
150 
151 #define HWA_EINVAL_PARAMSET_FFTMODE_POSTPROC (HWA_ERRNO_BASE - 26)
152 
153 #define HWA_EINVAL_PARAMSET_FFTMODE_PREPROC (HWA_ERRNO_BASE - 27)
154 
155 #define HWA_EINVAL_PARAMSET_FFTMODE_PREPROC_INTERF (HWA_ERRNO_BASE - 28)
156 
157 #define HWA_EINVAL_PARAMSET_FFTMODE_PREPROC_COMPLEXMULT (HWA_ERRNO_BASE - 29)
158 
159 #define HWA_EINVAL_PARAMSET_CFARMODE_GENERALCONFIG (HWA_ERRNO_BASE - 30)
160 
161 #define HWA_EINVAL_PARAMSET_CFARMODE_OSCONFIG (HWA_ERRNO_BASE - 31)
162 
163 #define HWA_EINVAL_PARAMSET_CFARMODE_CACONFIG (HWA_ERRNO_BASE - 32)
164 
165 #define HWA_EINVAL_PARAMSET_COMPRESSMODE (HWA_ERRNO_BASE - 33)
166 
167 #define HWA_EINVAL_PARAMSET_LOCALMAXMODE (HWA_ERRNO_BASE - 34)
168 
169 #define HWA_PARAMSET_POLLINGNOTALLOWED (HWA_ERRNO_BASE - 35)
170 
173 #define HWA_NUM_RXCHANNELS (12U)
174 
175 #define HWA_NUM_INTERFMITG_WINARRAY (5U)
176 
177 #define HWA_BPMPATTERN_LENGTH_INWORDS (8U)
178 
179 #define HWA_CHANCOMB_LENGTH_INWORDS (8U)
180 
181 #define HWA_ZEROINSERT_LENGTH_INWORDS (8U)
182 
183 #define HWA_NUM_RAMS (10U)
184 
185 #define HWA_MAXNUM_LOOPS (4095U)
186 
187 #define HWA_CMP_K_ARR_LEN (8U)
188 
202 #define HWA_DONE_INTERRUPT_PRIORITY (1U)
203 
204 #define HWA_ALTDONE_INTERRUPT_PRIORITY (1U)
205 
206 #define HWA_PARAMSETDONE_INTERRUPT1_PRIORITY (1U)
207 
208 #define HWA_PARAMSETDONE_INTERRUPT2_PRIORITY (1U)
209 
216 #define HWA_FEATURE_BIT_ENABLE ((uint8_t)1U)
217 #define HWA_FEATURE_BIT_DISABLE ((uint8_t)0U)
225 #define HWA_SAMPLES_WIDTH_16BIT ((uint8_t)0U)
226 #define HWA_SAMPLES_WIDTH_32BIT ((uint8_t)1U)
234 #define HWA_SAMPLES_FORMAT_COMPLEX ((uint8_t)0U)
235 #define HWA_SAMPLES_FORMAT_REAL ((uint8_t)1U)
243 #define HWA_SAMPLES_UNSIGNED ((uint8_t)0U)
244 #define HWA_SAMPLES_SIGNED ((uint8_t)1U)
252 #define HWA_FFT_WINDOW_NONSYMMETRIC ((uint8_t)0U)
253 #define HWA_FFT_WINDOW_SYMMETRIC ((uint8_t)1U)
265 #define HWA_FFT_WINDOW_INTERPOLATE_MODE_NONE ((uint8_t)0U)
266 #define HWA_FFT_WINDOW_INTERPOLATE_MODE_4K ((uint8_t)2U)
267 #define HWA_FFT_WINDOW_INTERPOLATE_MODE_8K ((uint8_t)1U)
275 #define HWA_FFT_MODE_MAGNITUDE_LOG2_DISABLED ((uint8_t)0U)
276 #define HWA_FFT_MODE_MAGNITUDE_ONLY_ENABLED ((uint8_t)2U)
277 #define HWA_FFT_MODE_MAGNITUDE_LOG2_ENABLED ((uint8_t)3U)
285 #define HWA_FFT_MODE_OUTPUT_DEFAULT ((uint8_t)0U)
286 #define HWA_FFT_MODE_OUTPUT_MAX_STATS ((uint8_t)2U)
287 #define HWA_FFT_MODE_OUTPUT_SUM_STATS ((uint8_t)3U)
295 #define HWA_NOISE_AVG_MODE_CFAR_CA ((uint8_t)0U)
296 #define HWA_NOISE_AVG_MODE_CFAR_CAGO ((uint8_t)1U)
297 #define HWA_NOISE_AVG_MODE_CFAR_CASO ((uint8_t)2U)
298 #define HWA_NOISE_AVG_MODE_CFAR_OS ((uint8_t)3U)
306 #define HWA_TRIG_MODE_IMMEDIATE ((uint8_t)0U)
307 #define HWA_TRIG_MODE_SOFTWARE ((uint8_t)1U)
308 #define HWA_TRIG_MODE_RESERVED1 ((uint8_t)2U)
309 #define HWA_TRIG_MODE_DMA ((uint8_t)3U)
310 #define HWA_TRIG_MODE_HARDWARE ((uint8_t)4U)
311 #define HWA_TRIG_MODE_RESERVED2 ((uint8_t)5U)
312 #define HWA_TRIG_MODE_RESERVED3 ((uint8_t)6U)
313 #define HWA_TRIG_MODE_M4CONTROL ((uint8_t)7U)
321 #define HWA_CONTEXTSWITCH_TRIG_MODE_DMA ((uint8_t)3U)
322 #define HWA_CONTEXTSWITCH_TRIG_MODE_HARDWARE ((uint8_t)4U)
323 #define HWA_CONTEXTSWITCH_TRIG_MODE_SOFTWARE ((uint8_t)5U)
331 #define HWA_THREAD_BACKGROUNDCONTEXT ((uint8_t)0U)
332 #define HWA_THREAD_ALTCONTEXT ((uint8_t)1U)
340 #define HWA_ACCELMODE_FFT ((uint8_t)0U)
341 #define HWA_ACCELMODE_CFAR ((uint8_t)1U)
342 #define HWA_ACCELMODE_COMPRESS ((uint8_t)2U)
343 #define HWA_ACCELMODE_LOCALMAX ((uint8_t)3U)
344 #define HWA_ACCELMODE_NONE ((uint8_t)7U)
364 #define HWA_CFAR_OPER_MODE_LOG_INPUT_REAL 0U
365 #define HWA_CFAR_OPER_MODE_LOG_INPUT_COMPLEX 1U
366 #define HWA_CFAR_OPER_MODE_MAG_INPUT_REAL 2U
367 #define HWA_CFAR_OPER_MODE_MAG_INPUT_COMPLEX 3U
368 #define HWA_CFAR_OPER_MODE_MAG_SQR_INPUT_REAL 4U
369 #define HWA_CFAR_OPER_MODE_MAG_SQR_INPUT_COMPLEX 5U
370 #define HWA_CFAR_OPER_MODE_LOG_INPUT_COMPLEX_LINEARCFAR 6U
388 #define HWA_CFAR_OUTPUT_MODE_I_nAVG_ALL_Q_CUT ((uint8_t)0U)
390 #define HWA_CFAR_OUTPUT_MODE_I_nAVG_ALL_Q_DET_FLAG ((uint8_t)1U)
392 #define HWA_CFAR_OUTPUT_MODE_I_PEAK_IDX_Q_NEIGHBOR_NOISE_VAL ((uint8_t)2U)
394 #define HWA_CFAR_OUTPUT_MODE_I_PEAK_IDX_Q_CUT ((uint8_t)3U)
396 #define HWA_CFAR_OUTPUT_MODE_FILTER_LARGE_PEAK ((uint8_t)4U)
405 #define HWA_RAM_TYPE_WINDOW_RAM ((uint8_t)0U)
406 #define HWA_RAM_TYPE_VECTORMULTIPLY_RAM ((uint8_t)1U)
407 #define HWA_RAM_TYPE_LUT_FREQ_DEROTATE_RAM ((uint8_t)2U)
408 #define HWA_RAM_TYPE_SHUFFLE_RAM ((uint8_t)3U)
409 #define HWA_RAM_TYPE_HIST_THRESH_RAM ((uint8_t)4U)
410 #define HWA_RAM_TYPE_2DSTAT_ITER_VAL ((uint8_t)5U)
411 #define HWA_RAM_TYPE_2DSTAT_ITER_IDX ((uint8_t)6U)
412 #define HWA_RAM_TYPE_2DSTAT_SAMPLE_VAL ((uint8_t)7U)
413 #define HWA_RAM_TYPE_2DSTAT_SAMPLE_IDX ((uint8_t)8U)
414 #define HWA_RAM_TYPE_HISTOGRAM_RAM ((uint8_t)9U)
422 #define HWA_CLIPREG_TYPE_DCACC ((uint8_t)0U)
423 #define HWA_CLIPREG_TYPE_DCEST ((uint8_t)1U)
424 #define HWA_CLIPREG_TYPE_DCSUB ((uint8_t)2U)
425 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGACC ((uint8_t)3U)
426 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGDIFFACC ((uint8_t)4U)
427 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGTHRESHOLD ((uint8_t)5U)
428 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGDIFFTHRESHOLD ((uint8_t)6U)
429 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGSUM ((uint8_t)7U)
430 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGDIFFSUM ((uint8_t)8U)
431 #define HWA_CLIPREG_TYPE_TWIDINCR_DELTAFRAC ((uint8_t)9U)
432 #define HWA_CLIPREG_TYPE_CHANCOMB ((uint8_t)10U)
433 #define HWA_CLIPREG_TYPE_FFT ((uint8_t)11U)
434 #define HWA_CLIPREG_TYPE_INPUTFORMAT ((uint8_t)12U)
435 #define HWA_CLIPREG_TYPE_OUTPUTFORMAT ((uint8_t)13U)
443 #define HWA_ACCUMULATORREG_TYPE_DC ((uint8_t)0U)
444 #define HWA_ACCUMULATORREG_TYPE_INTERF_MAG ((uint8_t)1U)
445 #define HWA_ACCUMULATORREG_TYPE_INTERF_MAGDIFF ((uint8_t)2U)
446 #define HWA_ACCUMULATORREG_TYPE_INTERF ((uint8_t)3U)
454 #define HWA_INTERFERENCE_THRESHOLD_TYPE_MAG ((uint8_t)0U)
455 #define HWA_INTERFERENCE_THRESHOLD_TYPE_MAGDIFF ((uint8_t)1U)
465 #define HWA_PARAMDONE_INTERRUPT_TYPE_CPU_INTR1 ((uint8_t)1U)
466 #define HWA_PARAMDONE_INTERRUPT_TYPE_CPU_INTR2 ((uint8_t)2U)
467 #define HWA_PARAMDONE_INTERRUPT_TYPE_DMA ((uint8_t)4U)
476 #define HWA_COMMONCONFIG_MASK_STATEMACHINE_CFG ((uint64_t)0x00000001U)
477 #define HWA_COMMONCONFIG_MASK_STATEMACHINE_CFG_ALT ((uint64_t)0x00000002U)
478 #define HWA_COMMONCONFIG_CONTEXTSWITCH_TRIG_CFG ((uint64_t)0x00000004U)
479 #define HWA_COMMONCONFIG_MASK_BPMCFG ((uint64_t)0x00000008U)
480 #define HWA_COMMONCONFIG_MASK_TWIDDITHERENABLE ((uint64_t)0x00000010U)
481 #define HWA_COMMONCONFIG_MASK_LFSRSEED ((uint64_t)0x00000020U)
482 #define HWA_COMMONCONFIG_MASK_FFTSUMDIV ((uint64_t)0x00000040U)
483 #define HWA_COMMONCONFIG_MASK_CFARTHRESHOLDSCALE ((uint64_t)0x00000080U)
484 #define HWA_COMMONCONFIG_MASK_DCEST_SCALESHIFT ((uint64_t)0x00000100U)
485 #define HWA_COMMONCONFIG_MASK_DCSUB_SWVAL ((uint64_t)0x00000200U)
486 #define HWA_COMMONCONFIG_MASK_INTERFMAG_THRESHOLD ((uint64_t)0x00000400U)
487 #define HWA_COMMONCONFIG_MASK_INTERFMAGDIFF_THRESHOLD ((uint64_t)0x00000800U)
488 #define HWA_COMMONCONFIG_MASK_INTERFSUM_MAG ((uint64_t)0x00001000U)
489 #define HWA_COMMONCONFIG_MASK_INTERFSUM_MAGDIFF ((uint64_t)0x00002000U)
490 #define HWA_COMMONCONFIG_MASK_COMPLEXMULT_SCALEARRAY ((uint64_t)0x00004000U)
493 #define HWA_COMMONCONFIG_MASK_COMPLEXMULT_SCALECONST ((uint64_t)0x00008000U)
496 #define HWA_COMMONCONFIG_MASK_RECWIN_RESET ((uint64_t)0x00010000U)
497 #define HWA_COMMONCONFIG_MASK_TWIDINCR_DELTA_FRAC ((uint64_t)0x00020000U)
499 #define HWA_COMMONCONFIG_MASK_CHANCOMB_VEC_SIZE ((uint64_t)0x00400000U)
500 #define HWA_COMMONCONFIG_MASK_ZEROINSERT_NUM_MASK ((uint64_t)0x00800000U)
501 #define HWA_COMMONCONFIG_MASK_MAX2D_OFFSETBOTHDIM ((uint64_t)0x01000000U)
502 #define HWA_COMMONCONFIG_MASK_CDFCNT_THRESHOLD ((uint64_t)0x02000000U)
503 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMB_THRESHOLDSW ((uint64_t)0x04000000U)
504 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMC_THRESHOLDSW ((uint64_t)0x08000000U)
505 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMBTHRESH_OFFSET ((uint64_t)0x10000000U)
506 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMCTHRESH_OFFSET ((uint64_t)0x20000000U)
507 #define HWA_COMMONCONFIG_MASK_INTERF_MITG_WINDOW_PARAM ((uint64_t)0x40000000U)
508 #define HWA_COMMONCONFIG_MASK_EGECOMRESS_KPARAM ((uint64_t)0x80000000U)
516 #define HWA_SRC_SHUFFLE_AB_MODE_DISABLE ((uint8_t)0U)
517 #define HWA_SRC_SHUFFLE_AB_MODE_ADIM ((uint8_t)1U)
518 #define HWA_SRC_SHUFFLE_AB_MODE_BDIM ((uint8_t)2U)
526 #define HWA_COMPLEX_MULTIPLY_MODE_DISABLE ((uint8_t)0U)
527 #define HWA_COMPLEX_MULTIPLY_MODE_FREQ_SHIFTER ((uint8_t)1U)
528 #define HWA_COMPLEX_MULTIPLY_MODE_SLOW_DFT ((uint8_t)2U)
529 #define HWA_COMPLEX_MULTIPLY_MODE_FFT_STITCHING ((uint8_t)3U)
530 #define HWA_COMPLEX_MULTIPLY_MODE_MAG_SQUARED ((uint8_t)4U)
531 #define HWA_COMPLEX_MULTIPLY_MODE_SCALAR_MULT ((uint8_t)5U)
532 #define HWA_COMPLEX_MULTIPLY_MODE_VECTOR_MULT ((uint8_t)6U)
533 #define HWA_COMPLEX_MULTIPLY_MODE_VECTOR_MULT_2 ((uint8_t)7U)
534 #define HWA_COMPLEX_MULTIPLY_MODE_RECURSIVE_WIN ((uint8_t)8U)
535 #define HWA_COMPLEX_MULTIPLY_MODE_LUT_FREQ_DEROTATE ((uint8_t)9U)
536 #define HWA_COMPLEX_MULTIPLY_MODE_FREQSHIFT_FREQINCREMENT ((uint8_t)10U)
545 #define HWA_FFT_STITCHING_TWID_PATTERN_4K ((uint8_t)1U)
546 #define HWA_FFT_STITCHING_TWID_PATTERN_8K ((uint8_t)2U)
555 #define HWA_RECURSIVE_WIN_MODE_SELECT_ITERATION_COUNT ((uint8_t)0U)
556 #define HWA_FFT_STITCHING_TWID_PATTERN_EXE_COUNT ((uint8_t)1U)
564 #define HWA_WINDOW_MODE_18BITREAL ((uint8_t)0U)
566 #define HWA_WINDOW_MODE_16BITREAL ((uint8_t)1U)
568 #define HWA_WINDOW_MODE_COMPLEX ((uint8_t)2U)
577 #define HWA_FFT3x_BFLY_SCALING_MSBSATURATED ((uint8_t)0U)
578 #define HWA_FFT3x_BFLY_SCALING_MSBSATLSBRND ((uint8_t)1U)
580 #define HWA_FFT3x_BFLY_SCALING_LSBROUNDED ((uint8_t)2U)
589 #define HWA_DCEST_INTERFSUM_RESET_MODE_NOUPDATE ((uint8_t)0U)
590 #define HWA_DCEST_INTERFSUM_RESET_MODE_SOFTWARERESET ((uint8_t)1U)
591 #define HWA_DCEST_INTERFSUM_RESET_MODE_PARAMRESET ((uint8_t)2U)
592 #define HWA_DCEST_INTERFSUM_RESET_MODE_PARAMRESET_ZEROLPCONT ((uint8_t)3U)
600 #define HWA_INTERFTHRESH_MODE_MAG_OR_MAGDIF ((uint8_t)0U)
601 #define HWA_INTERFTHRESH_MODE_MAGDIFF ((uint8_t)1U)
602 #define HWA_INTERFTHRESH_MODE_MAG ((uint8_t)2U)
603 #define HWA_INTERFTHRESH_MODE_MAG_AND_MAGDIFF ((uint8_t)3U)
611 #define HWA_DCSUB_SELECT_DCSW ((uint8_t)0U)
612 #define HWA_DCSUB_SELECT_DCEST ((uint8_t)1U)
620 #define HWA_INTERFTHRESH_SELECT_SW ((uint8_t)0U)
622 #define HWA_INTERFTHRESH_SELECT_EST_AVERAGE ((uint8_t)1U)
624 #define HWA_INTERFTHRESH_SELECT_EST_INDIVIDUAL ((uint8_t)2U)
633 #define HWA_INTERFMITIGATION_PATH_ZEROOUT ((uint8_t)0U)
634 #define HWA_INTERFMITIGATION_PATH_WINDOWZEROOUT ((uint8_t)1U)
635 #define HWA_INTERFMITIGATION_PATH_LINEARINTERPOLATION ((uint8_t)2U)
636 #define HWA_INTERFMITIGATION_PATH_UNUSED ((uint8_t)3U)
647 #define HWA_LUT_FREQ_DEROTATE_RAMIDX_AUTOINCR_WRAPAROUND ((uint8_t)0U)
648 #define HWA_LUT_FREQ_DEROTATE_RAMIDX_AUTOINCR_SATURATED ((uint8_t)1U)
649 #define HWA_LUT_FREQ_DEROTATE_RAMIDX_NONINCR ((uint8_t)2U)
657 #define HWA_HISTOGRAM_MODE_DISABLED ((uint8_t)0U)
658 #define HWA_HISTOGRAM_MODE_HISTOGRAM ((uint8_t)1U)
659 #define HWA_HISTOGRAM_MODE_CDF ((uint8_t)2U)
660 #define HWA_HISTOGRAM_MODE_CDF_THRESHOLD ((uint8_t)3U)
668 #define HWA_LOCALMAX_THRESH_BITMASK_BOTH_EN ((uint8_t)0U)
669 #define HWA_LOCALMAX_THRESH_BITMASK_CDIM_EN ((uint8_t)1U)
670 #define HWA_LOCALMAX_THRESH_BITMASK_BDIM_EN ((uint8_t)2U)
671 #define HWA_LOCALMAX_THRESH_BITMASK_BOTH_DIS ((uint8_t)3U)
679 #define HWA_LOCALMAX_THRESH_SELECT_DIMBREG_DIMCREG ((uint8_t)0U)
680 #define HWA_LOCALMAX_THRESH_SELECT_DIMBRAM_DIMCREG ((uint8_t)1U)
681 #define HWA_LOCALMAX_THRESH_SELECT_DIMBREG_DIMCRAM ((uint8_t)2U)
682 #define HWA_LOCALMAX_THRESH_SELECT_DIMBRAM_DIMCRAM ((uint8_t)3U)
690 #define HWA_COMPRESS_METHOD_EGE ((uint8_t)0U)
698 #define HWA_CMP_DCMP_COMPRESS ((uint8_t)0U)
699 #define HWA_CMP_DCMP_DECOMPRESS ((uint8_t)1U)
707 #define HWA_COMPRESS_PATHSELECT_BOTHPASSES ((uint8_t)3U)
708 #define HWA_COMPRESS_PATHSELECT_SECONDPASS ((uint8_t)1U)
720 #define HWA_PARAMSET_CONTEXTSWITCH_DISABLE (0U)
721 
722 #define HWA_PARAMSET_CONTEXTSWITCH_NONFORCE_ENABLE (1U)
723 
725 #define HWA_PARAMSET_CONTEXTSWITCH_FORCE_ENABLE (2U)
726 
728 /* ========================================================================== */
729 /* Structures and Enums */
730 /* ========================================================================== */
731 
735 typedef void* HWA_Handle;
736 
743 typedef void (*HWA_ParamDone_IntHandlerFuncPTR)(uint32_t intrIdx, uint32_t paramSet, void * arg);
744 
751 typedef void (*HWA_Done_IntHandlerFuncPTR)(uint32_t threadIdx, void * arg);
752 
759 typedef struct HWA_Attrs_t {
760  uint32_t instanceNum;
761  volatile uint32_t ctrlBaseAddr;
762  volatile uint32_t paramBaseAddr;
763  volatile uint32_t ramBaseAddr;
764  volatile uint32_t dssBaseAddr;
765  uint32_t numHwaParamSets;
766  uint32_t intNum1ParamSet;
767  uint32_t intNum2ParamSet;
768  uint32_t intNumDone;
769  uint32_t intNumDoneALT;
770  uint32_t numDmaChannels;
771  volatile uint32_t accelMemBaseAddr;
772  uint32_t accelMemSize;
773  bool isConcurrentAccessAllowed;
775 } HWA_Attrs;
776 
783 typedef struct HWA_RAMAttrs_t
784 {
785  uint32_t ramBaseAddress;
786  uint32_t ramSizeInBytes;
787 } HWA_RAMAttrs;
788 
800 typedef struct HWA_SrcDMAConfig_t {
801  uint32_t srcAddr;
802  uint32_t destAddr;
803  uint16_t aCnt;
804  uint16_t bCnt;
805  uint16_t cCnt;
806 } HWA_SrcDMAConfig;
807 
814 typedef struct HWA_CommonConfig_t {
815  uint64_t configMask;
818  uint16_t numLoops;
822  uint16_t paramStartIdx;
825  uint16_t paramStopIdx;
828  uint16_t numLoopsALT;
831  uint16_t paramStartIdxALT;
834  uint16_t paramStopIdxALT;
837  uint8_t contextswitchTriggerMode;
840  uint8_t contextswitchTriggerSrc;
845  struct {
846  uint16_t bpmRate;
850  uint32_t bpmPattern[HWA_BPMPATTERN_LENGTH_INWORDS];
856  uint8_t twidDitherEnable;
861  uint32_t lfsrSeed;
864  uint8_t fftSumDiv;
868  } fftConfig;
869 
870 
871  struct {
872  uint16_t scale;
878  uint8_t shift;
883  } dcEstimateConfig;
884 
885  struct
886  {
887  int32_t swIVal[HWA_NUM_RXCHANNELS];
892  int32_t swQVal[HWA_NUM_RXCHANNELS];
896  } dcSubtractConfig;
897 
898 
899  struct {
900 
901  uint32_t thresholdMagSw[HWA_NUM_RXCHANNELS];
909  uint32_t thresholdMagDiffSw[HWA_NUM_RXCHANNELS];
917  uint8_t sumMagScale;
924  int8_t sumMagShift;
929  uint8_t sumMagDiffScale;
934  int8_t sumMagDiffShift;
939  uint8_t mitigationWindowParam[HWA_NUM_INTERFMITG_WINARRAY];
945  } interfConfig;
946 
947 
948  struct {
949 
950  int32_t Iscale[HWA_NUM_RXCHANNELS];
956  int32_t Qscale[HWA_NUM_RXCHANNELS];
962  int16_t twiddleDeltaFrac;
970  uint8_t recWindowReset;
973  } complexMultiplyConfig;
974 
975  struct {
976 
977  uint8_t size;
981  uint32_t vector[HWA_CHANCOMB_LENGTH_INWORDS];
989  } chanCombConfig;
990 
991  struct {
992 
993  uint8_t number;
997  uint32_t mask[HWA_ZEROINSERT_LENGTH_INWORDS];
1004  } zeroInsertConfig;
1005 
1006  struct {
1007 
1008  uint32_t thresholdScale;
1015  } cfarConfig;
1016 
1017  struct {
1018 
1019  int32_t max2DoffsetDim1;
1023  int32_t max2DoffsetDim2;
1028  uint16_t cdfCntThresh;
1034  } advStatConfig;
1035 
1036  struct {
1037 
1038  uint16_t dimBThreshold;
1043  uint16_t dimCThreshold;
1048  uint16_t dimBBaseAddress;
1053  uint16_t dimCBaseAddress;
1057  } localMaxConfig;
1058 
1059  struct {
1060 
1061  uint8_t EGEKparam[HWA_CMP_K_ARR_LEN];
1066  } compressConfig;
1067 
1068 } HWA_CommonConfig;
1069 
1076 typedef struct HWA_SourceConfig_t {
1077  uint32_t srcAddr;
1082  uint16_t srcAcnt;
1086  int32_t srcAIdx;
1089  uint16_t srcBcnt;
1091  int32_t srcBIdx;
1095  uint16_t srcCcnt;
1097  int32_t srcCIdx;
1101  uint16_t srcAcircShift;
1105  uint8_t srcAcircShiftWrap;
1112  uint16_t srcBcircShift;
1115  uint8_t srcBcircShiftWrap;
1122  uint16_t srcCcircShift;
1126  uint8_t srcCcircShiftWrap;
1133  uint8_t srcCircShiftWrap3;
1137  uint8_t shuffleMode ;
1140  uint8_t srcRealComplex;
1143  uint8_t srcWidth;
1146  uint8_t srcSign;
1153  uint8_t srcConjugate;
1162  uint8_t srcScale;
1169  uint8_t srcIQSwap;
1172  uint32_t wrapComb;
1176  uint8_t shuffleStart;
1179 } HWA_SourceConfig;
1180 
1187 typedef struct HWA_DestConfig_t {
1188 
1189  uint32_t dstAddr;
1194  uint16_t dstAcnt;
1199  int32_t dstAIdx;
1203  int32_t dstBIdx;
1208  uint8_t dstRealComplex;
1212  uint8_t dstWidth;
1216  uint8_t dstSign;
1223  uint8_t dstConjugate;
1232  uint8_t dstScale;
1235  uint16_t dstSkipInit;
1241  uint8_t dstIQswap; /* See \ref HWA_FEATURE_BIT macros for correct values
1242  sets bits DST_IQSWAP of register DST in paramset */
1243 } HWA_DestConfig;
1244 
1251 typedef struct HWA_PostProcStat_t {
1252 
1253  uint8_t magLogEn;
1258  uint8_t fftOutMode;
1266  uint8_t max2Denable;
1270  uint8_t histogramMode;
1275  uint8_t histogramScaleSelect;
1280  uint8_t histogramSizeSelect;
1284 } HWA_PostProcStat;
1285 
1292 typedef struct HWA_ComplexMultiply_t {
1293 
1294  uint8_t cmultMode;
1299  union {
1300  struct
1301  {
1302  uint16_t freqShiftTwiddleIncr;
1305  } freqShift;
1306 
1307  struct
1308  {
1309  uint16_t startFreq;
1314  } slowDFT;
1315 
1316  struct
1317  {
1318  uint16_t twiddlePattern;
1323  uint8_t winInterpolateMode;
1329  } FFTstitching;
1330 
1331  struct
1332  {
1333  uint8_t scaleCmultScaleEn;
1343  } scalerMultiply;
1344 
1345  struct
1346  {
1347  uint8_t cmultScaleEn;
1354  uint16_t vecMultiMode1RamAddrOffset;
1356  } vectorMultiplyMode1;
1357 
1358  struct
1359  {
1360  uint16_t vecMultiMode2RamAddrOffset;
1364  } vectorMultiplyMode2;
1365 
1366  struct
1367  {
1368  uint8_t recwinModeSel;
1371  } recursiveWin;
1372 
1373  struct
1374  {
1375  uint16_t ramAddrOffset;
1377  uint8_t ramIdxIncrMode;
1380  } lutFreqDerotate;
1381 
1382  struct
1383  {
1384  uint16_t twiddleIncr;
1387  } freqShiftWithFreIncrement;
1388  } modeCfg ;
1389 } HWA_ComplexMultiply;
1390 
1397 typedef struct HWA_PreProcessing_t {
1398 
1399  uint8_t dcEstResetMode;
1404  uint8_t dcSubEnable;
1408  uint8_t dcSubSelect;
1411  struct {
1412  uint8_t thresholdEnable;
1416  uint8_t thresholdMode;
1420  uint8_t thresholdSelect;
1425  } interfLocalize;
1426 
1427  struct {
1428  uint8_t resetMode;
1433  } interfStat;
1434 
1435  struct {
1436 
1437  uint8_t enable;
1441  uint8_t countThreshold;
1446  uint8_t pathSelect;
1450  uint8_t leftHystOrder;
1454  uint8_t rightHystOrder;
1458  } interfMitigation;
1459 
1460  uint8_t chanCombEn;
1465  uint8_t zeroInsertEn;
1470  HWA_ComplexMultiply complexMultiply;
1472 } HWA_PreProcessing;
1473 
1480 typedef struct HWA_AccelModeFFT_t{
1481  uint8_t fftEn;
1486  uint8_t fftSize;
1493  uint16_t butterflyScaling;
1500  uint8_t windowEn;
1504  uint16_t windowStart;
1509  uint8_t winSymm;
1514  uint8_t windowMode;
1517  uint8_t fftSize3xEn;
1522  uint8_t fftSizeDim2;
1527  uint8_t butterflyScalingFFT3x;
1532  uint8_t bpmEnable;
1538  uint8_t bpmPhase;
1541  HWA_PostProcStat postProcCfg;
1543  HWA_PreProcessing preProcCfg;
1544 } HWA_AccelModeFFT;
1545 
1552 typedef struct HWA_AccelModeCFAR_t{
1553  uint8_t numNoiseSamplesLeft;
1559  uint8_t numNoiseSamplesRight;
1564  uint8_t numGuardCells;
1566  uint8_t nAvgDivFactor;
1572  uint8_t nAvgMode;
1576  uint8_t cfarOsKvalue;
1579  uint8_t cfarOsEdgeKScaleEn;
1583  uint8_t operMode;
1586  uint8_t outputMode;
1590  uint8_t cfarAdvOutMode;
1595  uint8_t peakGroupEn;
1604  uint8_t cyclicModeEn;
1609 } HWA_AccelModeCFAR;
1610 
1617 typedef struct HWA_AccelModeLocalMax_t{
1618 
1619  uint8_t neighbourBitmask;
1623  uint8_t thresholdBitMask;
1627  uint8_t thresholdMode;
1630  uint8_t dimBNonCyclic;
1632  uint8_t dimCNonCyclic;
1634 } HWA_AccelModeLocalMax;
1635 
1642 typedef struct HWA_AccelModeCompress_t {
1643  uint8_t EGEKidx;
1646  uint8_t EGEKarrayLength;
1649  uint8_t scaleFactorBW;
1654  uint8_t passSelect;
1656  uint8_t headerEnable;
1660  uint8_t method;
1663  uint8_t compressDecompress;
1665  uint8_t ditherEnable;
1667 } HWA_AccelModeCompress;
1668 
1675 typedef struct HWA_ParamConfig_t {
1676  uint8_t triggerMode;
1678  uint8_t triggerSrc;
1684  uint8_t accelMode;
1689  HWA_SourceConfig source;
1690  HWA_DestConfig dest;
1692  union {
1693  HWA_AccelModeFFT fftMode;
1694  HWA_AccelModeCFAR cfarMode;
1695  HWA_AccelModeLocalMax localMaxMode;
1696  HWA_AccelModeCompress compressMode;
1697  } accelModeArgs;
1698 
1699  uint8_t contextswitchCfg;
1701 } HWA_ParamConfig;
1702 
1709 typedef struct HWA_InterruptConfig_t {
1710  uint8_t interruptTypeFlag;
1716  struct {
1717  HWA_ParamDone_IntHandlerFuncPTR callbackFn;
1718  void *callbackArg;
1719  } cpu;
1720  struct {
1721  uint8_t dstChannel;
1723  } dma;
1724 } HWA_InterruptConfig;
1725 
1732 typedef struct HWA_Stats_t {
1733  uint32_t maxValue;
1734  uint16_t maxIndex;
1735  uint8_t iSumMSB;
1736  uint8_t qSumMSB;
1737  uint32_t iSumLSB;
1738  uint32_t qSumLSB;
1739 } HWA_Stats;
1740 
1745 typedef struct HWA_AccmulatorVal_t {
1746  uint32_t accValLSB;
1747  uint16_t accValMSB;
1748 } HWA_AccmulatorVal;
1749 
1756 typedef struct HWA_DebugStats_t {
1757  uint8_t currentParamSet;
1762  uint8_t paramSetIdxCpuIntr0;
1763  uint8_t paramSetIdxCpuIntr1;
1764  uint16_t currentLoopCount;
1766  uint16_t otherThreadLoopCount;
1767  uint32_t trigStatus[2];
1768 } HWA_DebugStats;
1769 
1776 typedef struct HWA_MemInfo_t {
1777  uint32_t baseAddress;
1778  uint16_t bankSize;
1779  uint16_t numBanks;
1780 } HWA_MemInfo;
1781 
1788 typedef struct HWA_CdfThreshold_t {
1789 
1790  uint32_t pdfValue : 12;
1791  uint32_t cdfValue : 12;
1792  uint32_t binNumber : 6;
1793  uint32_t reserved : 2;
1795 } HWA_CdfThreshold;
1796 
1801 typedef struct HWA_InterruptPriority_t {
1802 
1803  uint32_t backgroundDone;
1804  uint32_t ALTDone;
1805  uint32_t paramsetDone1;
1806  uint32_t paramsetDone2;
1808 } HWA_InterruptPriority;
1809 
1814 typedef struct HWA_OpenConfig_t {
1815 
1816  HWA_InterruptPriority interruptPriority ;
1829 } HWA_OpenConfig;
1830  /* end of HWA_DRIVER_EXTERNAL_DATA_STRUCTURE*/
1832 
1833 /* ========================================================================== */
1834 /* Internal/Private Structure Declarations */
1835 /* ========================================================================== */
1836 
1845 typedef struct HWA_InterruptCtx_t {
1846  HWA_ParamDone_IntHandlerFuncPTR callbackFn;
1847  void *callbackArg;
1848 } HWA_InterruptCtx;
1849 
1858 typedef struct HWA_DoneInterruptCtx_t {
1859  bool bIsEnabled;
1860  HWA_Done_IntHandlerFuncPTR callbackFn;
1861  void *callbackArg;
1862 } HWA_DoneInterruptCtx;
1863 
1867 typedef struct HWA_Driver_t {
1871  uint32_t instanceNum;
1875  uint32_t refCnt;
1880  uint8_t configInProgress;
1886  uint16_t paramSetMapInProgress;
1890  HWA_Attrs const *hwAttrs;
1891 
1895  HwiP_Object hwiHandleParamSet;
1896 
1900  HwiP_Object hwiHandleDone;
1901 
1905  HwiP_Object hwiHandleParamSetALT;
1906 
1910  HwiP_Object hwiHandleDoneALT;
1911 
1912 
1916  HWA_InterruptCtx *interruptCtxParamSet; /*[NUM_HWA_PARAMSETS_PER_INSTANCE];*/
1917 
1921  uint64_t interrupt1ParamSetMask;
1922 
1926  uint64_t interrupt2ParamSetMask;
1927 
1928 
1932  HWA_DoneInterruptCtx interruptCtxDone;
1933 
1937  HWA_DoneInterruptCtx interruptCtxDoneALT;
1938 } HWA_Object;
1939 
1941 extern HWA_Attrs gHwaAttrs[];
1943 extern HWA_RAMAttrs gHwaRamCfg[HWA_NUM_RAMS];
1945 extern HWA_Object gHwaObject[];
1947 extern HWA_Object *gHwaObjectPtr[];
1949 extern uint32_t gHwaConfigNum;
1950 
1951 /* ========================================================================== */
1952 /* Global Variables Declarations */
1953 /* ========================================================================== */
1954 
1955 /* None */
1956 
1957 /* ========================================================================== */
1958 /* Function Declarations */
1959 /* ========================================================================== */
1960 
1971 extern void HWA_init(void);
1972 
1976 extern void HWA_deinit(void);
1977 
1995 extern HWA_Handle HWA_open(uint32_t index, HWA_OpenConfig * hwaCfg, int32_t* errCode);
1996 
2008 extern int32_t HWA_close(HWA_Handle handle);
2009 
2021 extern int32_t HWA_reset(HWA_Handle handle);
2022 
2034 extern int32_t HWA_clearHistogramRAM(HWA_Handle handle);
2035 
2048 extern DSSHWACCRegs *HWA_getCommonCtrlAddr(HWA_Handle handle);
2049 
2064 extern DSSHWACCPARAMRegs *HWA_getParamSetAddr(HWA_Handle handle, uint8_t paramsetIdx);
2065 
2080 extern int32_t HWA_configCommon(HWA_Handle handle, HWA_CommonConfig *commonConfig);
2081 
2101 extern int32_t HWA_configParamSet(HWA_Handle handle, uint8_t paramsetIdx, HWA_ParamConfig *paramConfig, HWA_SrcDMAConfig *dmaConfig);
2102 
2125 extern int32_t HWA_getDMAconfig(HWA_Handle handle, uint8_t dmaTriggerSrc, HWA_SrcDMAConfig *dmaConfig);
2126 
2146 extern int32_t HWA_configRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx);
2147 
2157 extern uint32_t HWA_getRamAddress(uint8_t ramType);
2158 
2179 extern int32_t HWA_readRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx);
2180 
2199 extern int32_t HWA_readHistThresholdRam(HWA_Handle handle, HWA_CdfThreshold *cdfThresholdResult, uint8_t numSampleIndices, uint8_t startSampleIdx);
2200 
2218 extern int32_t HWA_enableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, HWA_InterruptConfig *intrConfig);
2219 
2236 extern int32_t HWA_paramSetDonePolling(HWA_Handle handle, uint8_t numParamSets, uint8_t *paramsetsArray);
2237 
2252 extern int32_t HWA_singleParamSetDonePolling(HWA_Handle handle, uint8_t paramsetIndex);
2253 
2271 extern int32_t HWA_enableDoneInterrupt(HWA_Handle handle, uint8_t threadIdx, HWA_Done_IntHandlerFuncPTR callbackFn, void * callbackArg);
2272 
2288 extern int32_t HWA_disableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, uint8_t interruptTypeFlag);
2289 
2303 extern int32_t HWA_disableDoneInterrupt(HWA_Handle handle, uint8_t threadIdx);
2304 
2319 extern int32_t HWA_enable(HWA_Handle handle, uint8_t flagEnDis);
2320 
2334 extern int32_t HWA_enableContextSwitch(HWA_Handle handle, uint8_t flagEnDis);
2335 
2350 extern int32_t HWA_setSoftwareTrigger(HWA_Handle handle);
2351 
2364 extern int32_t HWA_setContextswitchSoftwareTrigger(HWA_Handle handle);
2365 
2379 extern int32_t HWA_setContextswitchDMAManualTrigger(HWA_Handle handle,uint8_t idx);
2380 
2394 extern int32_t HWA_softwareResetAccumulators(HWA_Handle handle, uint8_t accumulatortype);
2395 
2407 extern int32_t HWA_softwareResetRecursiveWinKvalue(HWA_Handle handle);
2408 
2420 extern int32_t HWA_softwareResetTwidIncrDeltaFrac(HWA_Handle handle);
2421 
2435 extern int32_t HWA_setDMA2ACCManualTrig(HWA_Handle handle, uint8_t idx);
2436 
2452 extern int32_t HWA_setSourceAddress(HWA_Handle handle, uint16_t paramIdx, uint32_t sourceAddress);
2453 
2479 extern int32_t HWA_readClipStatus(HWA_Handle handle, uint16_t *clipStatusResult, uint8_t type);
2480 
2493 extern int32_t HWA_clearClipStatus(HWA_Handle handle, uint8_t type);
2494 
2513 extern int32_t HWA_readStatsReg(HWA_Handle handle, HWA_Stats *pStats, uint8_t numIter);
2514 
2532 extern int32_t HWA_readCFARPeakCountReg(HWA_Handle handle, uint8_t *pbuf, uint8_t size);
2533 
2548 extern int32_t HWA_readDebugReg(HWA_Handle handle, HWA_DebugStats *pStats);
2549 
2561 extern int32_t HWA_clearDebugReg(HWA_Handle handle);
2562 
2577 extern int32_t HWA_getHWAMemInfo(HWA_Handle handle, HWA_MemInfo *memInfo);
2578 
2596 extern int32_t HWA_getDMAChanIndex(HWA_Handle handle, uint8_t edmaChanId, uint8_t *hwaDestChan);
2597 
2613 extern int32_t HWA_getEDMAChanId(HWA_Handle handle, uint8_t hwaDMAdestChan);
2614 
2634 extern int32_t HWA_readDCEstimateReg(HWA_Handle handle, cmplx32ImRe_t *pbuf, uint8_t startIdx, uint8_t size);
2635 
2656 extern int32_t HWA_readIntfAccReg(HWA_Handle handle, uint64_t *accBuf, uint8_t type, uint8_t startIdx, uint8_t size);
2657 
2676 extern int32_t HWA_readDCAccReg(HWA_Handle handle, cmplx64ImRe_t *accbuf, uint8_t startIdx, uint8_t size);
2677 
2691 extern int32_t HWA_readInterfChirpCountReg(HWA_Handle handle, uint16_t *numInterfSamplesChirp);
2692 
2706 extern int32_t HWA_readInterfFrameCountReg(HWA_Handle handle, uint32_t *numInterfSamplesFrame);
2707 
2727 extern int32_t HWA_readInterfThreshReg(HWA_Handle handle, uint32_t *pbuf, uint8_t startIdx, uint8_t size, uint8_t type);
2728 
2741 extern int32_t HWA_controlPeripheralSuspendMode(HWA_Handle handle, uint8_t flagEnDis);
2742  /* end of addgroup HWA_DRIVER_EXTERNAL_FUNCTION*/
2744 
2745 #ifdef __cplusplus
2746 }
2747 #endif
2748 
2749 #endif /* HWA_H_ */
2750 
2751 
HWA_CHANCOMB_LENGTH_INWORDS
#define HWA_CHANCOMB_LENGTH_INWORDS
The length of channel combining vector in words.
Definition: hwa/v0/hwa.h:179
HWA_SourceConfig
HWA Paramset Config for Input Formatter/Source block.
Definition: hwa/v0/hwa.h:1073
HWA_AccmulatorVal
HWA Accumulator register value data structure.
Definition: hwa/v0/hwa.h:1742
HWA_readInterfThreshReg
int32_t HWA_readInterfThreshReg(HWA_Handle handle, uint32_t *pbuf, uint8_t startIdx, uint8_t size, uint8_t type)
Function to read the interference statistics INTF_LOC_THRESH_MAG_VAL or INTF_LOC_THRESH_MAG_VAL regis...
HWA_enable
int32_t HWA_enable(HWA_Handle handle, uint8_t flagEnDis)
Function to enable the state machine of the HWA. This should be called after paramset and RAM have be...
HWA_disableDoneInterrupt
int32_t HWA_disableDoneInterrupt(HWA_Handle handle, uint8_t threadIdx)
Function to disable the CPU interrupt after all programmed paramSets have been completed.
HWA_reset
int32_t HWA_reset(HWA_Handle handle)
Function to reset the internal state machine of the HWA.
HWA_clearHistogramRAM
int32_t HWA_clearHistogramRAM(HWA_Handle handle)
Function to clear the Histogram RAM in HWA.
HWA_AccelModeFFT
HWA Paramset Config for FFT block.
Definition: hwa/v0/hwa.h:1477
HWA_setDMA2ACCManualTrig
int32_t HWA_setDMA2ACCManualTrig(HWA_Handle handle, uint8_t idx)
Function to manually trigger the execution of the state machine waiting on DMA via software.
HWA_clearDebugReg
int32_t HWA_clearDebugReg(HWA_Handle handle)
Function to clear the debug registers (acc_trig_in_clr)
HWA_MemInfo
HWA Local memory Information.
Definition: hwa/v0/hwa.h:1773
gHwaConfigNum
uint32_t gHwaConfigNum
Externally defined driver configuration array size.
HWA_paramSetDonePolling
int32_t HWA_paramSetDonePolling(HWA_Handle handle, uint8_t numParamSets, uint8_t *paramsetsArray)
Function to poll the PARAM_DONE_SET_STATUS_0 and PARAM_DONE_SET_STATUS_1 registers to check if the sp...
HWA_open
HWA_Handle HWA_open(uint32_t index, HWA_OpenConfig *hwaCfg, int32_t *errCode)
Function to initialize HWA specified by the particular index value.
HWA_getDMAChanIndex
int32_t HWA_getDMAChanIndex(HWA_Handle handle, uint8_t edmaChanId, uint8_t *hwaDestChan)
Function to get the dma destination index with a given EDMA channel number This function assumes the ...
HWA_enableParamSetInterrupt
int32_t HWA_enableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, HWA_InterruptConfig *intrConfig)
Function to enable the CPU and/or DMA interrupt after a paramSet completion. The CPU interrupt for ev...
HWA_ComplexMultiply
HWA Paramset Config for ComplexMultiply block.
Definition: hwa/v0/hwa.h:1289
HWA_ParamDone_IntHandlerFuncPTR
void(* HWA_ParamDone_IntHandlerFuncPTR)(uint32_t intrIdx, uint32_t paramSet, void *arg)
HWA Interrupt callback function after every paramset completion.
Definition: hwa/v0/hwa.h:740
HWA_AccelModeCFAR
HWA Paramset Config for CFAR block.
Definition: hwa/v0/hwa.h:1549
HWA_init
void HWA_init(void)
Function to initialize the HWA module.
gHwaAttrs
HWA_Attrs gHwaAttrs[]
Externally defined driver configuration array.
HWA_CMP_K_ARR_LEN
#define HWA_CMP_K_ARR_LEN
The length of EGE compression/decompression K-paramseters array.
Definition: hwa/v0/hwa.h:187
HWA_OpenConfig
HWA configuration structure, which describes the configuration information, needed for hwa handle ope...
Definition: hwa/v0/hwa.h:1811
HWA_softwareResetTwidIncrDeltaFrac
int32_t HWA_softwareResetTwidIncrDeltaFrac(HWA_Handle handle)
Function resets the execution counter if complex multiply is configured as frequency shifter mode wit...
HWA_setContextswitchDMAManualTrigger
int32_t HWA_setContextswitchDMAManualTrigger(HWA_Handle handle, uint8_t idx)
Function to manually trigger the execution of the state machine via DMA trigger in context switch.
HWA_ZEROINSERT_LENGTH_INWORDS
#define HWA_ZEROINSERT_LENGTH_INWORDS
The length of zero insert mask in words.
Definition: hwa/v0/hwa.h:181
HWA_getDMAconfig
int32_t HWA_getDMAconfig(HWA_Handle handle, uint8_t dmaTriggerSrc, HWA_SrcDMAConfig *dmaConfig)
Function to get the config to program the DMA for a given DMA Trigger channel. Application should use...
HWA_DebugStats
HWA Debug statistics.
Definition: hwa/v0/hwa.h:1753
HWA_readInterfFrameCountReg
int32_t HWA_readInterfFrameCountReg(HWA_Handle handle, uint32_t *numInterfSamplesFrame)
Function to read the number of samples that exceeded the threshold in a frame.
HWA_close
int32_t HWA_close(HWA_Handle handle)
Function to close a HWA peripheral specified by the HWA handle.
HWA_readHistThresholdRam
int32_t HWA_readHistThresholdRam(HWA_Handle handle, HWA_CdfThreshold *cdfThresholdResult, uint8_t numSampleIndices, uint8_t startSampleIdx)
Function to read the HWA HWA_RAM_TYPE_HIST_THRESH_RAM RAM.
HWA_enableContextSwitch
int32_t HWA_enableContextSwitch(HWA_Handle handle, uint8_t flagEnDis)
Function to enable or disable the context switching in hwa.
HWA_readCFARPeakCountReg
int32_t HWA_readCFARPeakCountReg(HWA_Handle handle, uint8_t *pbuf, uint8_t size)
Function to read the PEAKCNT register.
HWA_getParamSetAddr
DSSHWACCPARAMRegs * HWA_getParamSetAddr(HWA_Handle handle, uint8_t paramsetIdx)
Function to returns the HWA paramSet base address.
HWA_readDCAccReg
int32_t HWA_readDCAccReg(HWA_Handle handle, cmplx64ImRe_t *accbuf, uint8_t startIdx, uint8_t size)
Function to read the DC estimation accumulator register,.
HWA_BPMPATTERN_LENGTH_INWORDS
#define HWA_BPMPATTERN_LENGTH_INWORDS
The length of BPM Pattern sequence in words.
Definition: hwa/v0/hwa.h:177
HWA_getEDMAChanId
int32_t HWA_getEDMAChanId(HWA_Handle handle, uint8_t hwaDMAdestChan)
Function to get the edma EDMA channel number from a given HWA paramset destination channel....
HWA_enableDoneInterrupt
int32_t HWA_enableDoneInterrupt(HWA_Handle handle, uint8_t threadIdx, HWA_Done_IntHandlerFuncPTR callbackFn, void *callbackArg)
Function to enable the CPU interrupt after all programmed paramSets have been completed in the backgr...
HWA_setContextswitchSoftwareTrigger
int32_t HWA_setContextswitchSoftwareTrigger(HWA_Handle handle)
Function to manually trigger the execution of the state machine via software in context switch,...
HWA_getCommonCtrlAddr
DSSHWACCRegs * HWA_getCommonCtrlAddr(HWA_Handle handle)
Function to returns the HWA common control base address.
gHwaRamCfg
HWA_RAMAttrs gHwaRamCfg[HWA_NUM_RAMS]
Externally defined driver RAM configuration array.
HWA_Done_IntHandlerFuncPTR
void(* HWA_Done_IntHandlerFuncPTR)(uint32_t threadIdx, void *arg)
HWA Interrupt callback function after all paramsets completion.
Definition: hwa/v0/hwa.h:748
HWA_PreProcessing
HWA Paramset Config for pre-processing block.
Definition: hwa/v0/hwa.h:1394
HWA_getRamAddress
uint32_t HWA_getRamAddress(uint8_t ramType)
Function to get the RAM starting address for one specified RAM type.
HWA_configCommon
int32_t HWA_configCommon(HWA_Handle handle, HWA_CommonConfig *commonConfig)
Function to set the common HWA configuration parameters needed for the next operations/iterations/par...
HwiP.h
HWA_NUM_RXCHANNELS
#define HWA_NUM_RXCHANNELS
Number of RX channels in pre-processing block.
Definition: hwa/v0/hwa.h:173
HWA_getHWAMemInfo
int32_t HWA_getHWAMemInfo(HWA_Handle handle, HWA_MemInfo *memInfo)
Function to get HWA processing Memory information including address, size and number of banks.
gHwaObject
HWA_Object gHwaObject[]
Externally defined driver object.
HWA_configRam
int32_t HWA_configRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx)
Function to set the HWA RAM : HWA_RAM_TYPE_WINDOW_RAM, HWA_RAM_TYPE_VECTORMULTIPLY_RAM,...
HWA_AccelModeLocalMax
HWA Paramset Config for Local maxima block.
Definition: hwa/v0/hwa.h:1614
HWA_InterruptPriority
HWA interrupt priority for HWA background thread done, ALT thread done, paramset done interrupt 1 and...
Definition: hwa/v0/hwa.h:1798
HWA_readClipStatus
int32_t HWA_readClipStatus(HWA_Handle handle, uint16_t *clipStatusResult, uint8_t type)
Function to read the Clip Status registers.
HWA_configParamSet
int32_t HWA_configParamSet(HWA_Handle handle, uint8_t paramsetIdx, HWA_ParamConfig *paramConfig, HWA_SrcDMAConfig *dmaConfig)
Function to set the HWA configuration parameters for a given paramSet.
HWA_InterruptConfig
HWA Interrupt Config.
Definition: hwa/v0/hwa.h:1706
HWA_SrcDMAConfig
Source trigger DMA parameters.
Definition: hwa/v0/hwa.h:797
HWA_DoneInterruptCtx
HWA Interrupt context structure for done interrupt.
Definition: hwa/v0/hwa.h:1855
HWA_CommonConfig
HWA Common Config.
Definition: hwa/v0/hwa.h:811
HWA_disableParamSetInterrupt
int32_t HWA_disableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, uint8_t interruptTypeFlag)
Function to disable the CPU and/or DMA interrupt after a paramSet completion.
HwiP_Object
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
HWA_ParamConfig
HWA Paramset Config.
Definition: hwa/v0/hwa.h:1672
HWA_readDCEstimateReg
int32_t HWA_readDCEstimateReg(HWA_Handle handle, cmplx32ImRe_t *pbuf, uint8_t startIdx, uint8_t size)
Function to read the DC_EST_I/Q register.
HWA_AccelModeCompress
HWA Paramset Config for compression and decompression.
Definition: hwa/v0/hwa.h:1639
HWA_singleParamSetDonePolling
int32_t HWA_singleParamSetDonePolling(HWA_Handle handle, uint8_t paramsetIndex)
Function to poll the PARAM_DONE_SET_STATUS_0 or PARAM_DONE_SET_STATUS_1 registers to check if one sin...
HWA_NUM_RAMS
#define HWA_NUM_RAMS
The number of RAM types in HWA.
Definition: hwa/v0/hwa.h:183
HWA_CdfThreshold
HWA Histogram Threshold RAM data structure.
Definition: hwa/v0/hwa.h:1785
HWA_softwareResetRecursiveWinKvalue
int32_t HWA_softwareResetRecursiveWinKvalue(HWA_Handle handle)
Function resets the paramset counter used in recurise windowing mode with REC_WIN_MODE_SEL is set to ...
HWA_NUM_INTERFMITG_WINARRAY
#define HWA_NUM_INTERFMITG_WINARRAY
Number of programmable array of window parameters in interference mitigation block.
Definition: hwa/v0/hwa.h:175
HWA_InterruptCtx
HWA Interrupt context structure for paramset done interrupt.
Definition: hwa/v0/hwa.h:1842
HWA_clearClipStatus
int32_t HWA_clearClipStatus(HWA_Handle handle, uint8_t type)
Function to clear the Clip Status registers.
HWA_setSoftwareTrigger
int32_t HWA_setSoftwareTrigger(HWA_Handle handle)
Function to manually trigger the execution of the state machine via software, the software trigger th...
HWA_RAMAttrs
HWA RAM Parameters.
Definition: hwa/v0/hwa.h:781
HWA_readDebugReg
int32_t HWA_readDebugReg(HWA_Handle handle, HWA_DebugStats *pStats)
Function to read the debug registers (paramcurr, loopcou, acc_trig_in_stat)
HWA_PostProcStat
HWA Paramset Config for post-processing and the statistics control registers.
Definition: hwa/v0/hwa.h:1248
HWA_DestConfig
HWA Paramset Config for Output Formatter/Destination block.
Definition: hwa/v0/hwa.h:1184
HWA_readRam
int32_t HWA_readRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx)
Function to read the HWA 2D statistics output RAM, including HWA_RAM_TYPE_2DSTAT_ITER_VAL,...
HWA_controlPeripheralSuspendMode
int32_t HWA_controlPeripheralSuspendMode(HWA_Handle handle, uint8_t flagEnDis)
Function to control the suspend mode of the peripheral when the controlling processor (where this dri...
HWA_readInterfChirpCountReg
int32_t HWA_readInterfChirpCountReg(HWA_Handle handle, uint16_t *numInterfSamplesChirp)
Function to read the number of samples that exceeded the threshold in a chirp.
HWA_Handle
void * HWA_Handle
A handle that is returned from a HWA_open() call.
Definition: hwa/v0/hwa.h:732
HWA_Stats
HWA Statistics from the STATISTICS block.
Definition: hwa/v0/hwa.h:1729
HWA_setSourceAddress
int32_t HWA_setSourceAddress(HWA_Handle handle, uint16_t paramIdx, uint32_t sourceAddress)
Function to set the source address for one paramset.
HWA_deinit
void HWA_deinit(void)
Function to deinitialize the HWA module.
HWA_readStatsReg
int32_t HWA_readStatsReg(HWA_Handle handle, HWA_Stats *pStats, uint8_t numIter)
Function to read the 4 sets of 'MAX' statistics register.
HWA_Object
HWA driver internal Config.
Definition: hwa/v0/hwa.h:1864
HWA_Attrs
HWA H/W Parameters.
Definition: hwa/v0/hwa.h:756
HWA_readIntfAccReg
int32_t HWA_readIntfAccReg(HWA_Handle handle, uint64_t *accBuf, uint8_t type, uint8_t startIdx, uint8_t size)
Function to read the interference threshold MAG or MAGDIFF Accumulator register.
gHwaObjectPtr
HWA_Object * gHwaObjectPtr[]
Externally defined driver object pointer.
HWA_softwareResetAccumulators
int32_t HWA_softwareResetAccumulators(HWA_Handle handle, uint8_t accumulatortype)
Function for sofware to reset the DC accumulators or interference statistics accumulators.