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AM263Px MCU+ SDK
09.01.00
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42 #ifndef RESOLVER_V1_H_
43 #define RESOLVER_V1_H_
63 #include <drivers/hw_include/hw_types.h>
64 #include <drivers/hw_include/cslr_soc.h>
66 #include <drivers/hw_include/cslr_resolver.h>
78 #define RDC_CORE_OFFSET (CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_1 - CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_0)
82 #define RDC_EXCITATION_FREQUENCY_MIN_PHASE (0U)
85 #define RDC_EXCITATION_FREQUENCY_MAX_PHASE (7999U)
89 #define RDC_MAX_EXCITATION_AMPLITUDE (249U)
93 #define RDC_RESOLVER_CORE0 (0U)
96 #define RDC_RESOLVER_CORE1 (1U)
99 #define RDC_ADC_CAL_CHANNEL0 (0U)
100 #define RDC_ADC_CAL_CHANNEL1 (1U)
101 #define RDC_ADC_CAL_CHANNEL2 (2U)
102 #define RDC_ADC_CAL_CHANNEL3 (3U)
105 #define RDC_DC_OFFSET_SIN_ESTIMATION (0U)
106 #define RDC_DC_OFFSET_COS_ESTIMATION (1U)
109 #define RDC_MIN_IDEAL_SAMPLE_PEAK_AVG_LIMIT (0U)
110 #define RDC_MAX_IDEAL_SAMPLE_PEAK_AVG_LIMIT (7U)
112 #define RDC_MAX_IDEAL_SAMPLE_BPF_ADJUST (0x0000001FU)
114 #define RDC_SINGALMODE_SINGLE_ENDED (0U)
115 #define RDC_SINGALMODE_DIFFERENTIAL_ENDED (1U)
127 #define RDC_ADC_BURST_COUNT_DISABLE (1U)
130 #define RDC_ADC_BURST_COUNT_2 (2U)
133 #define RDC_ADC_BURST_COUNT_4 (4U)
136 #define RDC_ADC_BURST_COUNT_8 (8U)
139 #define RDC_ADC_BURST_COUNT_16 (16U)
142 #define RDC_ADC_BURST_COUNT_32 (32U)
157 #define RDC_SEQUENCER_MODE_0 (0U)
161 #define RDC_SEQUENCER_MODE_1 (1U)
166 #define RDC_SEQUENCER_MODE_2 (2U)
174 #define RDC_SEQUENCER_MODE_3 (3U)
182 #define RDC_SEQUENCER_MODE_4 (4U)
189 #define RDC_SEQUENCER_MODE_5 (5U)
203 #define RDC_EXCITATION_FREQUENCY_5K (50)
206 #define RDC_EXCITATION_FREQUENCY_10K (100)
209 #define RDC_EXCITATION_FREQUENCY_20K (200)
225 #define OVERSAMPLING_RATIO_16 (8)
230 #define OVERSAMPLING_RATIO_20 (10)
247 #define RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR (0x00000001U)
248 #define RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR (0x00000002U)
249 #define RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR (0x00000004U)
250 #define RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR (0x00000008U)
251 #define RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR (0x00000010U)
252 #define RDC_INTERRUPT_SOURCE_COS_MULTI_ZC_ERROR_ERR (0x00000020U)
253 #define RDC_INTERRUPT_SOURCE_SIN_MULTI_ZC_ERROR_ERR (0x00000040U)
254 #define RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR (0x00000080U)
255 #define RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR (0x00000100U)
256 #define RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR (0x00000200U)
257 #define RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR (0x00000400U)
258 #define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR (0x00000800U)
259 #define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR (0x00001000U)
260 #define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR (0x00002000U)
261 #define RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR (0x00004000U)
262 #define RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR (0x00008000U)
263 #define RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR (0x00010000U)
264 #define RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR (0x00020000U)
265 #define RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR (0x00040000U)
266 #define RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR (0x00080000U)
267 #define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR (0x00100000U)
268 #define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR (0x00200000U)
269 #define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR (0x00400000U)
270 #define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR (0x00800000U)
271 #define RDC_INTERRUPT_SOURCE_TRACK_LOCK_ERR (0x01000000U)
273 #define RDC_INTERRUPT_SOURCE_ALL (RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR | \
274 RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR | \
275 RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR | \
276 RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR | \
277 RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR | \
278 RDC_INTERRUPT_SOURCE_COS_MULTI_ZC_ERROR_ERR | \
279 RDC_INTERRUPT_SOURCE_SIN_MULTI_ZC_ERROR_ERR | \
280 RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR | \
281 RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR | \
282 RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR | \
283 RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR | \
284 RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR | \
285 RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR | \
286 RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR | \
287 RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR | \
288 RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR | \
289 RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR | \
290 RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR | \
291 RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR | \
292 RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR | \
293 RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR | \
294 RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR | \
295 RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR | \
296 RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR | \
297 RDC_INTERRUPT_SOURCE_TRACK_LOCK_ERR)
308 #define RDC_CAL_ADC0 (0U)
311 #define RDC_CAL_ADC1 (1U)
323 #define RDC_IDEAL_SAMPLE_TIME_MODE_0_AUTO_DETECT (0U)
327 #define RDC_IDEAL_SAMPLE_TIME_MODE_1_AUTO_DETECT_ON_SIN (1U)
331 #define RDC_IDEAL_SAMPLE_TIME_MODE_2_AUTO_DETECT_ON_COS (2U)
335 #define RDC_IDEAL_SAMPLE_TIME_MODE_3_AUTO_DETECT_OFF (3U)
671 uint8_t peakHistgoramBucket[20];
687 base + CSL_RESOLVER_REGS_GLOBAL_CFG,
689 base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
690 ~CSL_RESOLVER_REGS_GLOBAL_CFG_SOC_WIDTH_MASK) |
691 (((uint8_t)socWidth) << CSL_RESOLVER_REGS_GLOBAL_CFG_SOC_WIDTH_SHIFT));
710 base + CSL_RESOLVER_REGS_GLOBAL_CFG,
712 base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
713 ~CSL_RESOLVER_REGS_GLOBAL_CFG_BURST_CNT_MASK) |
714 ((uint32_t)(((uint8_t)burstCount) << CSL_RESOLVER_REGS_GLOBAL_CFG_BURST_CNT_SHIFT)));
727 base + CSL_RESOLVER_REGS_GLOBAL_CFG,
729 base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
730 ~CSL_RESOLVER_REGS_GLOBAL_CFG_SINGLE_EN_MASK) |
731 ((uint32_t)((1U) << CSL_RESOLVER_REGS_GLOBAL_CFG_SINGLE_EN_SHIFT)));
744 base + CSL_RESOLVER_REGS_GLOBAL_CFG,
746 base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
747 ~CSL_RESOLVER_REGS_GLOBAL_CFG_SINGLE_EN_MASK));
769 static inline uint32_t
772 return ((HW_RD_REG32(
773 base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
774 CSL_RESOLVER_REGS_GLOBAL_CFG_MODE_MASK) >>
775 CSL_RESOLVER_REGS_GLOBAL_CFG_MODE_SHIFT);
805 base + CSL_RESOLVER_REGS_GLOBAL_CFG,
807 base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
808 ~CSL_RESOLVER_REGS_GLOBAL_CFG_MODE_MASK) |
809 ((uint32_t)((operationalMode) << CSL_RESOLVER_REGS_GLOBAL_CFG_MODE_SHIFT)));
821 base + CSL_RESOLVER_REGS_GLOBAL_CFG,
823 base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
824 ~CSL_RESOLVER_REGS_GLOBAL_CFG_MASTER_EN_MASK) |
825 ((uint32_t)((1U) << CSL_RESOLVER_REGS_GLOBAL_CFG_MASTER_EN_SHIFT)));
837 base + CSL_RESOLVER_REGS_GLOBAL_CFG,
839 base + CSL_RESOLVER_REGS_GLOBAL_CFG) |
840 CSL_RESOLVER_REGS_GLOBAL_CFG_MASTER_EN_MASK) &
841 ~((uint32_t)((1U) << CSL_RESOLVER_REGS_GLOBAL_CFG_MASTER_EN_SHIFT)));
861 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1,
863 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
864 ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_PHASE_CFG_MASK) |
865 ((uint32_t)(phase << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_PHASE_CFG_SHIFT)));
875 static inline uint32_t
880 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
881 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_PHASE_CFG_MASK) >>
882 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_PHASE_CFG_SHIFT);
902 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1,
904 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
905 ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_SEL_MASK) |
906 ((uint32_t)(FrequencySel << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_SEL_SHIFT)));
918 static inline uint32_t
923 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
924 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_SEL_MASK) >>
925 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_SEL_SHIFT);
934 static inline uint32_t
939 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
940 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_ADC_SAMPLE_RATE_MASK) >>
941 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_ADC_SAMPLE_RATE_SHIFT);
953 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2,
955 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
956 ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EN_MASK) |
957 ((uint32_t)((1U) << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EN_SHIFT)));
969 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2,
971 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) |
972 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EN_MASK) &
973 ~((uint32_t)((1U) << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EN_SHIFT)));
986 static inline uint32_t
991 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
992 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EVENT_MASK) >>
993 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EVENT_SHIFT);
1005 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2,
1007 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
1008 ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EVENT_MASK) |
1009 ((uint32_t)((1U) << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EVENT_SHIFT)));
1019 static inline uint32_t
1024 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
1025 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_PHASE_INFO_MASK) >>
1026 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_PHASE_INFO_SHIFT);
1039 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2,
1041 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
1042 ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_TO_SOC_DLY_START_MASK) |
1043 ((uint32_t)(socDelay << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_TO_SOC_DLY_START_SHIFT)));
1059 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3,
1061 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3) &
1062 ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3_EXC_AMP_CTRL_MASK) |
1063 ((uint32_t)(amplitude << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3_EXC_AMP_CTRL_SHIFT)));
1072 static inline uint32_t
1077 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3) &
1078 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3_EXC_AMP_CTRL_MASK) >>
1079 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3_EXC_AMP_CTRL_SHIFT);
1095 base + CSL_RESOLVER_REGS_IRQSTATUS_SYS,
1097 base + CSL_RESOLVER_REGS_IRQSTATUS_SYS) &
1098 ~CSL_RESOLVER_REGS_IRQSTATUS_SYS_SEQ_ERR_MASK) |
1099 ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQSTATUS_SYS_SEQ_ERR_SHIFT)));
1111 base + CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS,
1113 base + CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS) &
1114 ~CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS_SEQ_ERR_MASK) |
1115 ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS_SEQ_ERR_SHIFT)));
1127 base + CSL_RESOLVER_REGS_IRQSTATUS_SYS,
1129 base + CSL_RESOLVER_REGS_IRQSTATUS_SYS) &
1130 ~CSL_RESOLVER_REGS_IRQSTATUS_SYS_SEQ_ERR_MASK) |
1131 ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQSTATUS_SYS_SEQ_ERR_SHIFT)));
1143 base + CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS,
1145 base + CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS) &
1146 ~CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_SEQ_ERR_MASK) |
1147 ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_SEQ_ERR_SHIFT)));
1155 static inline uint32_t
1160 base + CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS) &
1161 ~CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_SEQ_ERR_MASK) |
1162 ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_SEQ_ERR_SHIFT)));
1179 uint32_t regOffset = CSL_RESOLVER_REGS_IRQENABLE_SET_SYS_0 + (ResolverCore *
RDC_CORE_OFFSET);
1185 ((uint32_t)interruptSource));
1195 static inline uint32_t
1198 uint32_t regOffset = CSL_RESOLVER_REGS_IRQENABLE_SET_SYS_0 + (ResolverCore *
RDC_CORE_OFFSET);
1217 uint32_t regOffset = CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS_0 + (ResolverCore *
RDC_CORE_OFFSET);
1223 ((uint32_t)interruptSource));
1239 uint32_t regOffset = CSL_RESOLVER_REGS_IRQSTATUS_SYS_0 + (ResolverCore *
RDC_CORE_OFFSET);
1262 uint32_t regOffset = CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_0 + (ResolverCore *
RDC_CORE_OFFSET);
1278 static inline uint32_t
1283 uint32_t regOffset = CSL_RESOLVER_REGS_IRQSTATUS_SYS_0 + (ResolverCore *
RDC_CORE_OFFSET);
1306 base + CSL_RESOLVER_REGS_CAL_CFG) &
1307 CSL_RESOLVER_REGS_CAL_CFG_CAL_DONE_MASK) >>
1308 CSL_RESOLVER_REGS_CAL_CFG_CAL_DONE_SHIFT) &
1321 base + CSL_RESOLVER_REGS_CAL_CFG,
1323 base + CSL_RESOLVER_REGS_CAL_CFG) &
1324 ~CSL_RESOLVER_REGS_CAL_CFG_CAL_DONE_MASK) |
1325 ((uint32_t)((1U) << CSL_RESOLVER_REGS_CAL_CFG_CAL_DONE_SHIFT)));
1338 base + CSL_RESOLVER_REGS_CAL_CFG,
1340 base + CSL_RESOLVER_REGS_CAL_CFG) &
1341 ~CSL_RESOLVER_REGS_CAL_CFG_CAL_CHSEL_MASK) |
1342 ((uint32_t)(calChannel << CSL_RESOLVER_REGS_CAL_CFG_CAL_CHSEL_SHIFT)));
1354 base + CSL_RESOLVER_REGS_CAL_CFG,
1356 base + CSL_RESOLVER_REGS_CAL_CFG) &
1357 ~CSL_RESOLVER_REGS_CAL_CFG_CAL_EN_MASK) |
1358 ((uint32_t)((1U) << CSL_RESOLVER_REGS_CAL_CFG_CAL_EN_SHIFT)));
1368 static inline uint32_t
1371 uint32_t regData = HW_RD_REG32(
1372 base + CSL_RESOLVER_REGS_CAL_OBS) &
1373 (CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC0_DATA_MASK |
1374 CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC1_DATA_MASK);
1377 return ((regData & CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC0_DATA_MASK) >>
1378 CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC0_DATA_SHIFT);
1380 return ((regData & CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC1_DATA_MASK) >>
1381 CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC1_DATA_SHIFT);
1401 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core *
RDC_CORE_OFFSET);
1402 uint32_t mask = (CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF1_MASK |
1403 CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF2_MASK);
1405 uint32_t value = (coef1 << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF1_SHIFT) |
1406 (coef2 << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF2_SHIFT);
1431 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core *
RDC_CORE_OFFSET);
1437 ~CSL_RESOLVER_REGS_DC_OFF_CFG1_0_BANDPASSFILTER_ON_MASK) |
1438 ((uint32_t)((1U) << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_BANDPASSFILTER_ON_SHIFT)));
1451 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core *
RDC_CORE_OFFSET);
1457 CSL_RESOLVER_REGS_DC_OFF_CFG1_0_BANDPASSFILTER_ON_MASK) &
1458 ~((uint32_t)((1U) << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_BANDPASSFILTER_ON_SHIFT)));
1473 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core *
RDC_CORE_OFFSET);
1479 ~CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFFSET_CORR_ON_MASK) |
1480 ((uint32_t)((1U) << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFFSET_CORR_ON_SHIFT)));
1495 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core *
RDC_CORE_OFFSET);
1501 CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFFSET_CORR_ON_MASK) &
1502 ~((uint32_t)((1U) << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFFSET_CORR_ON_SHIFT)));
1519 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG2_0 + (core *
RDC_CORE_OFFSET);
1520 uint32_t mask = (CSL_RESOLVER_REGS_DC_OFF_CFG2_0_SIN_MAN_OFF_ADJ_MASK |
1521 CSL_RESOLVER_REGS_DC_OFF_CFG2_0_COS_MAN_OFF_ADJ_MASK);
1523 uint32_t value = (((uint32_t)((uint16_t)sin)) << CSL_RESOLVER_REGS_DC_OFF_CFG2_0_SIN_MAN_OFF_ADJ_SHIFT) |
1524 (((uint32_t)((uint16_t)cos)) << CSL_RESOLVER_REGS_DC_OFF_CFG2_0_COS_MAN_OFF_ADJ_SHIFT);
1546 static inline int16_t
1549 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF0 + (core *
RDC_CORE_OFFSET);
1550 uint32_t mask = CSL_RESOLVER_REGS_DC_OFF0_SIN_OFFSET_MASK | CSL_RESOLVER_REGS_DC_OFF0_COS_OFFSET_MASK;
1552 return ((int16_t)(HW_RD_REG32(
1555 (sinCosValue * CSL_RESOLVER_REGS_DC_OFF0_COS_OFFSET_SHIFT));
1573 uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG1_0 + (core *
RDC_CORE_OFFSET);
1578 ~CSL_RESOLVER_REGS_SAMPLE_CFG1_0_IDEAL_SAMPLE_TIME_OVR_MASK) |
1579 ((uint32_t)(overrideValue << CSL_RESOLVER_REGS_SAMPLE_CFG1_0_IDEAL_SAMPLE_TIME_OVR_SHIFT)));
1590 static inline uint8_t
1593 uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG1_0 + (core *
RDC_CORE_OFFSET);
1597 CSL_RESOLVER_REGS_SAMPLE_CFG1_0_IDEAL_SAMPLE_TIME_MASK) >>
1598 CSL_RESOLVER_REGS_SAMPLE_CFG1_0_IDEAL_SAMPLE_TIME_SHIFT);
1615 uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG2_0 + (core *
RDC_CORE_OFFSET);
1620 ~CSL_RESOLVER_REGS_SAMPLE_CFG2_0_SAMPLE_DET_THRESHOLD_MASK) |
1621 ((uint32_t)(absThresholdValue << CSL_RESOLVER_REGS_SAMPLE_CFG2_0_SAMPLE_DET_THRESHOLD_SHIFT)));
1636 uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG2_0 + (core *
RDC_CORE_OFFSET);
1642 ~CSL_RESOLVER_REGS_SAMPLE_CFG2_0_BANDPASSFILTERSAMPLEADJUST_MASK) |
1643 ((uint32_t)(sampleAdjustCount << CSL_RESOLVER_REGS_SAMPLE_CFG2_0_BANDPASSFILTERSAMPLEADJUST_SHIFT)));
1658 uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG2_0 + (core *
RDC_CORE_OFFSET);
1662 CSL_RESOLVER_REGS_SAMPLE_CFG2_0_PEAK_AVG_LIMIT_DONE_MASK) &
1663 ((uint32_t)((1U) << CSL_RESOLVER_REGS_SAMPLE_CFG2_0_PEAK_AVG_LIMIT_DONE_SHIFT))) != 0U);
1681 uint32_t regOffset = CSL_RESOLVER_REGS_DEC_GF_CFG0 + (core *
RDC_CORE_OFFSET);
1683 (mode & ~(CSL_RESOLVER_REGS_DEC_GF_CFG0_IDEAL_SAMPLE_MODE_MAX)) == 0U);
1688 ~CSL_RESOLVER_REGS_DEC_GF_CFG0_IDEAL_SAMPLE_MODE_MASK) |
1689 ((uint32_t)(mode << CSL_RESOLVER_REGS_DEC_GF_CFG0_IDEAL_SAMPLE_MODE_SHIFT)));
1704 uint32_t regOffset = CSL_RESOLVER_REGS_DEC_GF_CFG0 + (core *
RDC_CORE_OFFSET);
1709 ~CSL_RESOLVER_REGS_DEC_GF_CFG0_ENABLE_BOTTOM_MASK) |
1710 ((uint32_t)((1U) << CSL_RESOLVER_REGS_DEC_GF_CFG0_ENABLE_BOTTOM_SHIFT)));
1723 uint32_t regOffset = CSL_RESOLVER_REGS_DEC_GF_CFG0 + (core *
RDC_CORE_OFFSET);
1728 CSL_RESOLVER_REGS_DEC_GF_CFG0_ENABLE_BOTTOM_MASK) &
1729 ~((uint32_t)((1U) << CSL_RESOLVER_REGS_DEC_GF_CFG0_ENABLE_BOTTOM_SHIFT)));
1748 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG1_0 + (core *
RDC_CORE_OFFSET);
1752 CSL_RESOLVER_REGS_PG_EST_CFG1_0_AUTOPHASEGAINREADYDONE_MASK) &
1753 ((uint32_t)((1U) << CSL_RESOLVER_REGS_PG_EST_CFG1_0_AUTOPHASEGAINREADYDONE_SHIFT))) != 0U);
1768 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG1_0 + (core *
RDC_CORE_OFFSET);
1769 DebugP_assert(pgEstimationLimit <= CSL_RESOLVER_REGS_PG_EST_CFG1_0_PG_TRAIN_LIMIT_MAX);
1774 ~CSL_RESOLVER_REGS_PG_EST_CFG1_0_PG_TRAIN_LIMIT_MASK) |
1775 ((uint32_t)(pgEstimationLimit << CSL_RESOLVER_REGS_PG_EST_CFG1_0_PG_TRAIN_LIMIT_SHIFT)));
1789 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core *
RDC_CORE_OFFSET);
1790 DebugP_assert((cosPhaseBypass & (~CSL_RESOLVER_REGS_PG_EST_CFG2_0_PHASECOSBYP0_MAX)) == 0U);
1795 ~CSL_RESOLVER_REGS_PG_EST_CFG2_0_PHASECOSBYP0_MASK) |
1796 ((uint32_t)(cosPhaseBypass << CSL_RESOLVER_REGS_PG_EST_CFG2_0_PHASECOSBYP0_SHIFT)));
1809 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core *
RDC_CORE_OFFSET);
1814 CSL_RESOLVER_REGS_PG_EST_CFG2_0_BYPASSPHASEGAINCORR0_MASK) &
1815 ~((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_BYPASSPHASEGAINCORR0_SHIFT));
1829 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core *
RDC_CORE_OFFSET);
1834 ~CSL_RESOLVER_REGS_PG_EST_CFG2_0_BYPASSPHASEGAINCORR0_MASK) |
1835 ((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_BYPASSPHASEGAINCORR0_SHIFT));
1848 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core *
RDC_CORE_OFFSET);
1853 ~CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOPHASECONTROL0_MASK) |
1854 ((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOPHASECONTROL0_SHIFT));
1867 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core *
RDC_CORE_OFFSET);
1872 CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOPHASECONTROL0_MASK) &
1873 ~((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOPHASECONTROL0_SHIFT));
1886 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core *
RDC_CORE_OFFSET);
1891 ~CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOGAINCONTROL0_MASK) |
1892 ((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOGAINCONTROL0_SHIFT));
1905 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core *
RDC_CORE_OFFSET);
1910 CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOGAINCONTROL0_MASK) &
1911 ~((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOGAINCONTROL0_SHIFT));
1926 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG3_0 + (core *
RDC_CORE_OFFSET);
1928 uint32_t value = ((uint32_t)(((uint16_t)cosGainBypass) << 16)) | ((uint32_t)((uint16_t)sinGainBypass));
1931 base + regOffset, value);
1943 static inline int16_t
1946 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG4_0 + (core *
RDC_CORE_OFFSET);
1950 CSL_RESOLVER_REGS_PG_EST_CFG4_0_PHASEESTIMATEFINAL_MASK) >>
1951 CSL_RESOLVER_REGS_PG_EST_CFG4_0_PHASEESTIMATEFINAL_SHIFT);
1966 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG5_0 + (core *
RDC_CORE_OFFSET);
1967 uint32_t value = HW_RD_REG32(base + regOffset);
1969 *cosGainEstimate = (int16_t)(value >> 16);
1970 *sinGainEstimate = (int16_t)value;
1991 uint8_t kvelfilt = track2Constants->
kvelfilt;
1992 uint32_t cfg1 = (kvelfilt << CSL_RESOLVER_REGS_TRACK2_CFG1_0_KVELFILT_SHIFT);
1994 uint32_t mask_cfg1 = (CSL_RESOLVER_REGS_TRACK2_CFG1_0_KVELFILT_MASK);
1996 uint32_t regOffset_cfg1 = CSL_RESOLVER_REGS_TRACK2_CFG1_0 + (core *
RDC_CORE_OFFSET);
1998 base + regOffset_cfg1,
2000 base + regOffset_cfg1) &
2015 uint32_t regOffset = CSL_RESOLVER_REGS_TRACK2_CFG2_0 + (core *
RDC_CORE_OFFSET);
2021 ~CSL_RESOLVER_REGS_TRACK2_CFG2_0_BOOST_MASK) |
2022 ((uint32_t)((1U) << CSL_RESOLVER_REGS_TRACK2_CFG2_0_BOOST_SHIFT)));
2034 uint32_t regOffset = CSL_RESOLVER_REGS_TRACK2_CFG2_0 + (core *
RDC_CORE_OFFSET);
2040 CSL_RESOLVER_REGS_TRACK2_CFG2_0_BOOST_MASK) &
2041 ~((uint32_t)((1U) << CSL_RESOLVER_REGS_TRACK2_CFG2_0_BOOST_SHIFT)));
2054 static inline int16_t
2057 uint32_t regOffset = CSL_RESOLVER_REGS_ANGLE_ARCTAN_0 + (core *
RDC_CORE_OFFSET);
2059 (int16_t)HW_RD_REG16(
2072 static inline int16_t
2075 uint32_t regOffset = CSL_RESOLVER_REGS_ANGLE_TRACK2_0 + (core *
RDC_CORE_OFFSET);
2077 (int16_t)HW_RD_REG16(
2091 static inline int32_t
2094 uint32_t regOffset = CSL_RESOLVER_REGS_VELOCITY_TRACK2_0 + (core *
RDC_CORE_OFFSET);
2096 (int32_t)HW_RD_REG32(
2120 uint8_t resolverCore,
2123 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG1_0 + (
RDC_CORE_OFFSET * resolverCore);
2124 uint32_t value = HW_RD_REG32(base + regOffset);
2129 CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_HI_MASK) >>
2130 CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_HI_SHIFT));
2132 CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_LO_MASK) >>
2133 CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_LO_SHIFT));
2162 uint8_t resolverCore,
2165 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG1_0 + (
RDC_CORE_OFFSET * resolverCore);
2166 uint32_t value = (((uint32_t)((uint16_t)(monitorData->
offset_drift_threshold_hi))) << CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_HI_SHIFT) |
2167 (((uint32_t)((uint16_t)(monitorData->
offset_drift_threshold_lo))) << CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_LO_SHIFT);
2168 uint32_t interruptSource = 0;
2178 base + regOffset, value);
2225 uint8_t resolverCore,
2228 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG14_0 + (
RDC_CORE_OFFSET * resolverCore);
2230 uint32_t value = HW_RD_REG32(base + regOffset);
2236 CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_HI_MASK) >>
2237 CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_HI_SHIFT));
2239 CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_LO_MASK) >>
2240 CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_LO_SHIFT));
2248 regOffset = CSL_RESOLVER_REGS_DIAG15_0 + (
RDC_CORE_OFFSET * resolverCore);
2251 monitorData->
gaindrift_en = ((enabledInterruptSources &
2275 uint8_t resolverCore,
2278 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG14_0 + (
RDC_CORE_OFFSET * resolverCore);
2279 uint32_t value = (((uint32_t)((uint16_t)(monitorData->
gain_drift_threshold_hi))) << CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_HI_SHIFT) |
2280 (((uint32_t)((uint16_t)(monitorData->
gain_drift_threshold_lo))) << CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_LO_SHIFT);
2282 uint32_t interruptSource = 0;
2292 regOffset = CSL_RESOLVER_REGS_DIAG15_0 + (
RDC_CORE_OFFSET * resolverCore);
2298 base + regOffset, value);
2344 uint8_t resolverCore,
2347 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG16_0 + (
RDC_CORE_OFFSET * resolverCore);
2349 uint32_t value = HW_RD_REG32(base + regOffset);
2355 CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_HI_MASK) >>
2356 CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_HI_SHIFT));
2358 CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_LO_MASK) >>
2359 CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_LO_SHIFT));
2365 regOffset = CSL_RESOLVER_REGS_DIAG17_0 + (
RDC_CORE_OFFSET * resolverCore);
2388 uint8_t resolverCore,
2391 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG16_0 + (
RDC_CORE_OFFSET * resolverCore);
2392 uint32_t value = (((uint32_t)((uint16_t)(monitorData->
phase_drift_threshold_hi))) << CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_HI_SHIFT) |
2393 (((uint32_t)((uint16_t)(monitorData->
phase_drift_threshold_lo))) << CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_LO_SHIFT);
2395 uint32_t interruptSource = 0;
2401 regOffset = CSL_RESOLVER_REGS_DIAG17_0 + (
RDC_CORE_OFFSET * resolverCore);
2407 base + regOffset, value);
2448 uint8_t resolverCore,
2451 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG2_0 + (
RDC_CORE_OFFSET * resolverCore);
2453 uint32_t value = HW_RD_REG32(base + regOffset);
2459 CSL_RESOLVER_REGS_DIAG2_0_EXCFREQDETECTED_SIN_MASK) >>
2460 CSL_RESOLVER_REGS_DIAG2_0_EXCFREQDETECTED_SIN_SHIFT));
2462 CSL_RESOLVER_REGS_DIAG2_0_EXCFREQDETECTED_COS_MASK) >>
2463 CSL_RESOLVER_REGS_DIAG2_0_EXCFREQDETECTED_COS_SHIFT));
2465 regOffset = CSL_RESOLVER_REGS_DIAG3_0 + (
RDC_CORE_OFFSET * resolverCore);
2466 value = HW_RD_REG32(base + regOffset);
2469 CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_HI_MASK) >>
2470 CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_HI_SHIFT));
2472 CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_LO_MASK) >>
2473 CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_LO_SHIFT));
2475 regOffset = CSL_RESOLVER_REGS_DIAG4_0 + (
RDC_CORE_OFFSET * resolverCore);
2476 value = HW_RD_REG32(base + regOffset);
2479 CSL_RESOLVER_REGS_DIAG4_0_EXCFREQ_LEVEL_MASK) >>
2480 CSL_RESOLVER_REGS_DIAG4_0_EXCFREQ_LEVEL_SHIFT));
2482 CSL_RESOLVER_REGS_DIAG4_0_EXCFREQDRIFT_GLITCHCOUNT_MASK) >>
2483 CSL_RESOLVER_REGS_DIAG4_0_EXCFREQDRIFT_GLITCHCOUNT_SHIFT));
2514 uint8_t resolverCore,
2517 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG2_0 + (
RDC_CORE_OFFSET * resolverCore);
2518 uint32_t value = (((uint32_t)((uint16_t)(monitorData->
excfreqdrift_threshold_hi))) << CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_HI_SHIFT) |
2519 (((uint32_t)((uint16_t)(monitorData->
excfreqdrift_threshold_lo))) << CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_LO_SHIFT);
2520 uint32_t interruptSource = 0;
2530 base + regOffset, value);
2532 regOffset = CSL_RESOLVER_REGS_DIAG3_0 + (
RDC_CORE_OFFSET * resolverCore);
2533 value = (((uint32_t)((uint16_t)(monitorData->
excfreq_level))) << CSL_RESOLVER_REGS_DIAG4_0_EXCFREQ_LEVEL_SHIFT) |
2534 (((uint32_t)((uint16_t)(monitorData->
excfreqdrift_glitchcount))) << CSL_RESOLVER_REGS_DIAG4_0_EXCFREQDRIFT_GLITCHCOUNT_SHIFT);
2537 base + regOffset, value);
2578 uint8_t resolverCore,
2581 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG13_0 + (
RDC_CORE_OFFSET * resolverCore);
2582 uint32_t value = HW_RD_REG32(
2585 monitorData->
sin_multi_zc_error_count = (uint8_t)((value & CSL_RESOLVER_REGS_DIAG13_0_SIN_MULTI_ZC_ERROR_COUNT_MASK) >> CSL_RESOLVER_REGS_DIAG13_0_SIN_MULTI_ZC_ERROR_COUNT_SHIFT);
2587 monitorData->
cos_multi_zc_error_count = (uint8_t)((value & CSL_RESOLVER_REGS_DIAG13_0_COS_MULTI_ZC_ERROR_COUNT_MASK) >> CSL_RESOLVER_REGS_DIAG13_0_COS_MULTI_ZC_ERROR_COUNT_SHIFT);
2589 regOffset = CSL_RESOLVER_REGS_DIAG12_0 + (
RDC_CORE_OFFSET * resolverCore);
2590 value = HW_RD_REG32(
2592 monitorData->
rotpeak_level = (value & CSL_RESOLVER_REGS_DIAG12_0_ROTPEAK_LEVEL_MASK) >> CSL_RESOLVER_REGS_DIAG12_0_ROTPEAK_LEVEL_SHIFT;
2593 monitorData->
rotpeak_level = (value & CSL_RESOLVER_REGS_DIAG12_0_ROTFREQ_LEVEL_MASK) >> CSL_RESOLVER_REGS_DIAG12_0_ROTFREQ_LEVEL_SHIFT;
2628 uint8_t resolverCore,
2631 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG12_0 + (
RDC_CORE_OFFSET * resolverCore);
2632 uint32_t value = (((uint32_t)((uint16_t)(monitorData->
rotpeak_level))) << CSL_RESOLVER_REGS_DIAG12_0_ROTPEAK_LEVEL_SHIFT) |
2633 (((uint32_t)((uint16_t)(monitorData->
rotfreq_level))) << CSL_RESOLVER_REGS_DIAG12_0_ROTFREQ_LEVEL_SHIFT);
2639 uint32_t interruptSources = 0;
2683 uint32_t resolverCore,
2686 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG9_0 + (resolverCore *
RDC_CORE_OFFSET);
2687 uint32_t value = HW_RD_REG32(
2691 CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_HI_SHIFT;
2693 CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_LO_SHIFT;
2695 regOffset = CSL_RESOLVER_REGS_DIAG10_0 + (resolverCore *
RDC_CORE_OFFSET);
2696 value = HW_RD_REG32(
2699 monitorData->
sinsqcossq_cossq = (value & CSL_RESOLVER_REGS_DIAG10_0_SINSQCOSSQ_COSSQ_MASK) >>
2700 CSL_RESOLVER_REGS_DIAG10_0_SINSQCOSSQ_COSSQ_SHIFT;
2701 monitorData->
sinsqcossq_sinsq = (value & CSL_RESOLVER_REGS_DIAG10_0_SINSQCOSSQ_SINSQ_MASK) >>
2702 CSL_RESOLVER_REGS_DIAG10_0_SINSQCOSSQ_SINSQ_SHIFT;
2706 regOffset = CSL_RESOLVER_REGS_DIAG11_0 + (resolverCore *
RDC_CORE_OFFSET);
2709 CSL_RESOLVER_REGS_DIAG11_0_SINSQCOSSQ_GLITCHCOUNT_MASK) >>
2710 CSL_RESOLVER_REGS_DIAG11_0_SINSQCOSSQ_GLITCHCOUNT_SHIFT);
2732 uint32_t resolverCore,
2735 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG9_0 + (resolverCore *
RDC_CORE_OFFSET);
2736 uint32_t value = (((uint32_t)((uint16_t)(monitorData->
sinsqcossq_threshold_hi))) << CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_HI_SHIFT) |
2737 (((uint32_t)((uint16_t)(monitorData->
sinsqcossq_threshold_lo))) << CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_LO_SHIFT);
2739 base + regOffset, value);
2741 regOffset = CSL_RESOLVER_REGS_DIAG11_0 + (resolverCore *
RDC_CORE_OFFSET);
2748 uint32_t interruptSources = 0;
2778 uint8_t resolverCore,
2781 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG7_0 + (resolverCore *
RDC_CORE_OFFSET);
2782 uint32_t value = HW_RD_REG32(
2787 CSL_RESOLVER_REGS_DIAG7_1_HIGHAMPLITUDE_GLITCHCOUNT_SHIFT;
2790 CSL_RESOLVER_REGS_DIAG7_1_HIGHAMPLITUDE_THRESHOLD_SHIFT;
2791 regOffset = CSL_RESOLVER_REGS_DIAG8_0 + (resolverCore *
RDC_CORE_OFFSET);
2792 value = HW_RD_REG32(
2795 monitorData->
highAmplitude_sin_value = (int16_t) ((value & CSL_RESOLVER_REGS_DIAG8_1_HIGHAMPLITUDE_SIN_MASK) >> \
2796 CSL_RESOLVER_REGS_DIAG8_1_HIGHAMPLITUDE_SIN_SHIFT);
2798 monitorData->
highAmplitude_cos_value = (int16_t) ((value & CSL_RESOLVER_REGS_DIAG8_1_HIGHAMPLITUDE_COS_MASK) >> \
2799 CSL_RESOLVER_REGS_DIAG8_1_HIGHAMPLITUDE_COS_SHIFT);
2819 uint8_t resolverCore,
2822 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG7_0 + (resolverCore *
RDC_CORE_OFFSET);
2823 uint32_t value = (((uint32_t)((uint16_t)(monitorData->
highAmplitude_glitchcount))) << CSL_RESOLVER_REGS_DIAG7_1_HIGHAMPLITUDE_GLITCHCOUNT_SHIFT) |
2824 (((uint32_t)((uint16_t)(monitorData->
highAmplitude_threshold))) << CSL_RESOLVER_REGS_DIAG7_1_HIGHAMPLITUDE_THRESHOLD_SHIFT);
2825 uint32_t enabledInterruptSources = 0;
2826 uint32_t interruptSources = 0;
2858 uint8_t resolverCore,
2862 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG5_0 + (resolverCore *
RDC_CORE_OFFSET);
2864 uint32_t value = HW_RD_REG32(
2867 CSL_RESOLVER_REGS_DIAG5_1_LOWAMPLITUDE_THRESHOLD_SHIFT;
2869 CSL_RESOLVER_REGS_DIAG5_1_LOWAMPLITUDE_GLITCHCOUNT_SHIFT;
2873 regOffset = CSL_RESOLVER_REGS_DIAG6_0 + (resolverCore *
RDC_CORE_OFFSET);
2874 value = HW_RD_REG32(
2876 monitorData->
lowAmplitude_cos_value = (int16_t)((value & CSL_RESOLVER_REGS_DIAG6_1_LOWAMPLITUDE_COS_MASK) >>\
2877 CSL_RESOLVER_REGS_DIAG6_1_LOWAMPLITUDE_COS_SHIFT);
2879 monitorData->
lowAmplitude_sin_value = (int16_t)((value & CSL_RESOLVER_REGS_DIAG6_1_LOWAMPLITUDE_SIN_MASK) >>\
2880 CSL_RESOLVER_REGS_DIAG6_1_LOWAMPLITUDE_SIN_SHIFT);
2897 uint8_t resolverCore,
2901 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG5_0 + (resolverCore *
RDC_CORE_OFFSET);
2902 uint32_t value = ((uint32_t)(monitorData->
lowAmplitude_glitchcount << CSL_RESOLVER_REGS_DIAG5_1_LOWAMPLITUDE_GLITCHCOUNT_SHIFT)) |
2903 ((uint32_t) (monitorData->
lowAmplitude_threshold << CSL_RESOLVER_REGS_DIAG5_1_LOWAMPLITUDE_GLITCHCOUNT_SHIFT));
2907 base + regOffset, value);
2940 uint8_t resolverCore,
2943 uint32_t regOffset = CSL_RESOLVER_REGS_OBS_ADC_0 + (resolverCore *
RDC_CORE_OFFSET);
2944 uint32_t value = HW_RD_REG32(
2946 AdcData->
cos_adc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_1_COS_ADC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_1_COS_ADC_SHIFT);
2947 AdcData->
sin_adc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_1_SIN_ADC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_1_SIN_ADC_SHIFT);
2949 regOffset = CSL_RESOLVER_REGS_OBS_ADC_REC_0 + (resolverCore *
RDC_CORE_OFFSET);
2950 value = HW_RD_REG32(
2952 AdcData->
cos_rec = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_REC_1_COS_REC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_REC_1_COS_REC_SHIFT);
2953 AdcData->
sin_rec = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_REC_1_SIN_REC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_REC_1_SIN_REC_SHIFT);
2955 regOffset = CSL_RESOLVER_REGS_OBS_ADC_DC_0 + (resolverCore *
RDC_CORE_OFFSET);
2956 value = HW_RD_REG32(
2958 AdcData->
cos_dc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_DC_1_COS_DC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_DC_1_COS_DC_SHIFT);
2959 AdcData->
sin_dc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_DC_1_SIN_DC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_DC_1_SIN_DC_SHIFT);
2961 regOffset = CSL_RESOLVER_REGS_OBS_ADC_PGC_0 + (resolverCore *
RDC_CORE_OFFSET);
2962 value = HW_RD_REG32(
2964 AdcData->
cos_pgc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_PGC_1_COS_PGC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_PGC_1_COS_PGC_SHIFT);
2965 AdcData->
sin_pgc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_PGC_1_SIN_PGC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_PGC_1_SIN_PGC_SHIFT);
2978 uint32_t regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0 + (resolverCore *
RDC_CORE_OFFSET);
2979 uint32_t value = HW_RD_REG32(
2981 histogram->
peakHistgoramBucket[0] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM0_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM0_0_SHIFT);
2982 histogram->
peakHistgoramBucket[1] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM1_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM1_0_SHIFT);
2983 histogram->
peakHistgoramBucket[2] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM2_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM2_0_SHIFT);
2984 histogram->
peakHistgoramBucket[3] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM3_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM3_0_SHIFT);
2986 regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0 + (resolverCore *
RDC_CORE_OFFSET);
2987 value = HW_RD_REG32(
2989 histogram->
peakHistgoramBucket[4] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM4_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM4_0_SHIFT);
2990 histogram->
peakHistgoramBucket[5] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM5_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM5_0_SHIFT);
2991 histogram->
peakHistgoramBucket[6] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM6_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM6_0_SHIFT);
2992 histogram->
peakHistgoramBucket[7] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM7_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM7_0_SHIFT);
2994 regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0 + (resolverCore *
RDC_CORE_OFFSET);
2995 value = HW_RD_REG32(
2997 histogram->
peakHistgoramBucket[8] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM8_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM8_0_SHIFT);
2998 histogram->
peakHistgoramBucket[9] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM9_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM9_0_SHIFT);
2999 histogram->
peakHistgoramBucket[10] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM10_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM10_0_SHIFT);
3000 histogram->
peakHistgoramBucket[11] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM11_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM11_0_SHIFT);
3002 regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0 + (resolverCore *
RDC_CORE_OFFSET);
3003 value = HW_RD_REG32(
3005 histogram->
peakHistgoramBucket[12] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM12_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM12_0_SHIFT);
3006 histogram->
peakHistgoramBucket[13] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM13_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM13_0_SHIFT);
3007 histogram->
peakHistgoramBucket[14] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM14_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM14_0_SHIFT);
3008 histogram->
peakHistgoramBucket[15] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM15_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM15_0_SHIFT);
3010 regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0 + (resolverCore *
RDC_CORE_OFFSET);
3011 value = HW_RD_REG32(
3013 histogram->
peakHistgoramBucket[16] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM16_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM16_0_SHIFT);
3014 histogram->
peakHistgoramBucket[17] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM17_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM17_0_SHIFT);
3015 histogram->
peakHistgoramBucket[18] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM18_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM18_0_SHIFT);
3016 histogram->
peakHistgoramBucket[19] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM19_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM19_0_SHIFT);
3064 #endif // RESOLVER_V1_H_
int16_t gain_drift_threshold_lo
Definition: resolver/v0/resolver.h:392
bool Pg_correctionEnable
Definition: resolver/v0/resolver.h:599
#define RDC_CAL_ADC0
Macro used to specify Calibration data for ADC 0.
Definition: resolver/v0/resolver.h:308
static int16_t RDC_getArcTanAngle(uint32_t base, uint8_t core)
Returns signed 16bit angle data from ArcTan. the data corresponds to -180 to +180 degrees angle in de...
Definition: resolver/v0/resolver.h:2055
bool lowAmplitude_error
Definition: resolver/v0/resolver.h:538
uint8_t Input_signalMode
Definition: resolver/v0/resolver.h:618
static int16_t RDC_getDcOffsetEstimatedValues(uint32_t base, uint8_t core, uint8_t sinCosValue)
returns DC OFFSET estimation values
Definition: resolver/v0/resolver.h:1547
Structure to hold the control/status data for Diagnostics mentioned under Monitor excitation frequenc...
Definition: resolver/v0/resolver.h:436
#define RDC_DC_OFFSET_COS_ESTIMATION
Definition: resolver/v0/resolver.h:106
bool phase_drift_en
Definition: resolver/v0/resolver.h:420
#define RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR
Definition: resolver/v0/resolver.h:261
uint16_t sinsqcossq_cossq
Definition: resolver/v0/resolver.h:494
void RDC_coreParamsInit(Core_config_t *coreParams)
Inits the Core Parameters for the resolver core.
uint16_t excfreqdetected_sin
Definition: resolver/v0/resolver.h:437
bool sinsqcossq_lo
Definition: resolver/v0/resolver.h:497
#define RDC_EXCITATION_FREQUENCY_MIN_PHASE
Minimum Phase value that can be programmed for the Excitation signal.
Definition: resolver/v0/resolver.h:82
static void RDC_setDiagnosticsSinCosOffsetDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_SinCos_Offset_drift_data *monitorData)
Sets the Monitor Sin or Cos Offset Drift (DOS) diagnostics controls int16_t offset_drift_threshold_hi...
Definition: resolver/v0/resolver.h:2161
Structure to hold the control/status data for Diagnostics mentioned under Monitor Cos Phase drift (DO...
Definition: resolver/v0/resolver.h:414
bool gain_drift_sin_hi
Definition: resolver/v0/resolver.h:396
uint16_t excfreq_level
Definition: resolver/v0/resolver.h:441
static void RDC_clearSequencerInterrupt(uint32_t base)
Clear the Sequencer Error Interrupt status.
Definition: resolver/v0/resolver.h:1124
int16_t cos_adc
Definition: resolver/v0/resolver.h:565
#define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR
Definition: resolver/v0/resolver.h:268
static void RDC_disablePhaseGainEstimation(uint32_t base, uint8_t core)
Disbales Phase Gain Estimation in the background.
Definition: resolver/v0/resolver.h:1827
static void RDC_setDcOffsetCalCoef(uint32_t base, uint8_t core, uint8_t coef1, uint8_t coef2)
Sets the DC Offset Coefficients coef1, coef2.
Definition: resolver/v0/resolver.h:1398
uint8_t DcParam3
Definition: resolver/v0/resolver.h:647
bool BpfDc_offsetCorrectionEnable
Definition: resolver/v0/resolver.h:584
Core_config_t core1
Definition: resolver/v0/resolver.h:630
int16_t sin_adc
Definition: resolver/v0/resolver.h:566
#define RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR
Definition: resolver/v0/resolver.h:251
bool offset_drift_cos_lo
Definition: resolver/v0/resolver.h:371
static void RDC_getDiagnosticsRotationalSignalIntegrityData(uint32_t base, uint8_t resolverCore, Diag_Mon_Rotational_Signal_Integrity_data *monitorData)
Returns the Monitor rotational signal integrity (DOS) diagnostics data bool cos_neg_zc_peak_mismatch_...
Definition: resolver/v0/resolver.h:2577
int16_t Pg_sinGainBypassValue
Definition: resolver/v0/resolver.h:601
static uint32_t RDC_getCoreInterruptStatus(uint32_t base, uint32_t ResolverCore)
Returns Core interrupt Status.
Definition: resolver/v0/resolver.h:1279
static uint32_t RDC_getCoreEnabledInterruptSources(uint32_t base, uint8_t ResolverCore)
returns enabled Interrupt Sources
Definition: resolver/v0/resolver.h:1196
static void RDC_setTrack2Constants(uint32_t base, uint8_t core, Track2Constants_t *track2Constants)
sets up the Track2 loop constants the following are the constants that can be setup using this API
Definition: resolver/v0/resolver.h:1989
static void RDC_getDiagnosticsWeakAmplitudeData(uint32_t base, uint8_t resolverCore, Diag_Mon_Sin_Cos_Weak_Amplitude *monitorData)
Returns the Monitor weak Sin or Cos signal below a threshold (LOS) diagnostics data uint16_t lowAmpli...
Definition: resolver/v0/resolver.h:2856
uint16_t excfreqdrift_threshold_lo
Definition: resolver/v0/resolver.h:440
int16_t offset_drift_threshold_lo
Definition: resolver/v0/resolver.h:369
bool excfreqdrift_en
Definition: resolver/v0/resolver.h:446
bool sin_pos_zc_peak_mismatch_err
Definition: resolver/v0/resolver.h:466
#define RDC_MAX_IDEAL_SAMPLE_BPF_ADJUST
Definition: resolver/v0/resolver.h:112
int16_t BpfDc_manualCos
Definition: resolver/v0/resolver.h:588
bool phase_drift_cos_hi
Definition: resolver/v0/resolver.h:418
static uint32_t RDC_getAdcSampleRate(uint32_t base)
Gets the ADC Sampling Ratio.
Definition: resolver/v0/resolver.h:935
static void RDC_enableGainAutoCorrection(uint32_t base, uint8_t core)
Enable Gain Auto correction.
Definition: resolver/v0/resolver.h:1884
#define RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR
Definition: resolver/v0/resolver.h:254
#define RDC_EXCITATION_FREQUENCY_MAX_PHASE
Maximum Phase value that can be programmed for the Excitation signal.
Definition: resolver/v0/resolver.h:85
int16_t highAmplitude_cos_value
Definition: resolver/v0/resolver.h:517
uint8_t phase_drift_glitch_count
Definition: resolver/v0/resolver.h:417
static void RDC_disableCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
Disable Core Interrupt.
Definition: resolver/v0/resolver.h:1212
uint16_t highAmplitude_threshold
Definition: resolver/v0/resolver.h:514
void RDC_init(uint32_t base, RDC_configParams *params)
Configures the RDC based on the parameter values.
Struct holds the Resolver Core Configurations Can be passed to RDC_coreParamsInit(Core_config_t* core...
Definition: resolver/v0/resolver.h:582
static void RDC_enableTrack2Boost(uint32_t base, uint8_t core)
enables the track2 Boost
Definition: resolver/v0/resolver.h:2013
static void RDC_getGainEstimation(uint32_t base, uint8_t core, int16_t *sinGainEstimate, int16_t *cosGainEstimate)
returns the Gain estimates for sin and cosine gain values
Definition: resolver/v0/resolver.h:1964
static bool RDC_getIdealSamplePeakAvgLimitStatus(uint32_t base, uint8_t core)
Gets the status if the Peak Averaging Limit is reached.
Definition: resolver/v0/resolver.h:1656
#define RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR
Definition: resolver/v0/resolver.h:262
static void RDC_setIdealSampleBpfAdjust(uint32_t base, uint8_t core, uint8_t sampleAdjustCount)
the BPF sample adjust when the BPF is turned on. This configuration takes effect only on the auto mod...
Definition: resolver/v0/resolver.h:1634
bool excfreqdrift_cos_lo
Definition: resolver/v0/resolver.h:444
bool cos_pos_zc_peak_mismatch_err
Definition: resolver/v0/resolver.h:464
#define RDC_SEQUENCER_MODE_5
ADC0/1 Parallelly Sample Sin0, Cos0, Cos1, Sin1 Samples Sequentially For Core0/1. Both Sin(Cos) Sampl...
Definition: resolver/v0/resolver.h:189
static uint32_t RDC_getSequencerInterruptStatus(uint32_t base)
Returns Sequencer interrupt Status.
Definition: resolver/v0/resolver.h:1156
static uint32_t RDC_getCalibrationData(uint32_t base, uint8_t CalAdc)
Returns the CAL ADC data for given ADC, if the mode permits.
Definition: resolver/v0/resolver.h:1369
Track2Constants_t track2Constants
Definition: resolver/v0/resolver.h:605
static void RDC_setGainBypassValue(uint32_t base, uint8_t core, int16_t sinGainBypass, int16_t cosGainBypass)
Sets the Manual Gain Correction values for Sin and Cos.
Definition: resolver/v0/resolver.h:1924
#define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR
Definition: resolver/v0/resolver.h:260
static void RDC_overrideIdealSampleTime(uint32_t base, uint8_t core, uint8_t overrideValue)
sets the Override value for the Ideal Sample Time selection.
Definition: resolver/v0/resolver.h:1571
#define RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR
Definition: resolver/v0/resolver.h:249
bool IdealSample_bottomSampleEnable
Definition: resolver/v0/resolver.h:594
#define RDC_RESOLVER_CORE0
Macro used to specify resolver core 0.
Definition: resolver/v0/resolver.h:93
uint8_t t2Param8
Definition: resolver/v0/resolver.h:652
static void RDC_setIdealSampleMode(uint32_t base, uint8_t core, uint8_t mode)
Ideal Sample Time Computation Mode selection.
Definition: resolver/v0/resolver.h:1679
void RDC_BaselineParametersInit(uint32_t base)
Inits Baseline Parameter configurations.
uint16_t lowAmplitude_threshold
Definition: resolver/v0/resolver.h:536
bool cos_multi_zc_error_err
Definition: resolver/v0/resolver.h:468
bool BpfDc_bpfEnable
Definition: resolver/v0/resolver.h:583
static uint32_t RDC_getExcitationSignalAmplitudeControl(uint32_t base)
returns the Amplitude control for the excitation signal
Definition: resolver/v0/resolver.h:1073
bool highAmplitude_sin_error
Definition: resolver/v0/resolver.h:518
static void RDC_disableAdcSingleEndedMode(uint32_t base)
Disable Single Ended Mode of operation.
Definition: resolver/v0/resolver.h:741
uint32_t Int_core1Interrupts
Definition: resolver/v0/resolver.h:634
bool adv_config
Definition: resolver/v0/resolver.h:617
bool gaindrift_en
Definition: resolver/v0/resolver.h:398
#define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR
Definition: resolver/v0/resolver.h:269
bool gain_drift_sin_lo
Definition: resolver/v0/resolver.h:397
static void RDC_enableExcitationSignalSyncIn(uint32_t base)
Enables the Excitation Signal Sync In.
Definition: resolver/v0/resolver.h:950
uint8_t lowAmplitude_glitchcount
Definition: resolver/v0/resolver.h:537
struct to hold the track2 constant data
Definition: resolver/v0/resolver.h:350
static void RDC_clearCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
Clear the Core Interrupt status.
Definition: resolver/v0/resolver.h:1234
#define RDC_CORE_OFFSET
Header Files.
Definition: resolver/v0/resolver.h:78
uint8_t Input_adcBurstCount
Definition: resolver/v0/resolver.h:620
static void RDC_setDiagnosticsRotationalSignalIntegrityData(uint32_t base, uint8_t resolverCore, Diag_Mon_Rotational_Signal_Integrity_data *monitorData)
Sets the Monitor rotational signal integrity (DOS) diagnostics Controls bool cos_neg_zc_peak_mismatch...
Definition: resolver/v0/resolver.h:2627
Structure to hold the control/status data for Diagnostics mentioned under Monitor Sin or Cos saturati...
Definition: resolver/v0/resolver.h:513
static void RDC_selectCalibrationChannel(uint32_t base, uint8_t calChannel)
Selects Calibration Channel for Cal sequence.
Definition: resolver/v0/resolver.h:1335
int16_t cos_pgc
Definition: resolver/v0/resolver.h:571
bool sinsqcossq_hi
Definition: resolver/v0/resolver.h:496
uint8_t IdealSample_overrideValue
Definition: resolver/v0/resolver.h:590
uint8_t excfreqdrift_glitchcount
Definition: resolver/v0/resolver.h:442
bool phase_drift_cos_lo
Definition: resolver/v0/resolver.h:419
Structure to hold the control/status data for Diagnostics mentioned under Monitor weak Sin or Cos sig...
Definition: resolver/v0/resolver.h:535
#define RDC_RESOLVER_CORE1
Macro used to specify resolver core 1.
Definition: resolver/v0/resolver.h:96
uint8_t Input_resolverSequencerMode
Definition: resolver/v0/resolver.h:621
int16_t highAmplitude_sin_value
Definition: resolver/v0/resolver.h:516
static void RDC_disableGainAutoCorrection(uint32_t base, uint8_t core)
Disable Gain Auto Correction.
Definition: resolver/v0/resolver.h:1903
int16_t sin_rec
Definition: resolver/v0/resolver.h:568
bool cos_neg_zc_peak_mismatch_err
Definition: resolver/v0/resolver.h:463
int16_t cos_dc
Definition: resolver/v0/resolver.h:569
static uint32_t RDC_getExcitationSignalFrequencySelect(uint32_t base)
Returns the selected Excitation Signal Frequency select.
Definition: resolver/v0/resolver.h:919
#define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR
Definition: resolver/v0/resolver.h:270
Core_config_t core0
Definition: resolver/v0/resolver.h:629
static void RDC_setExcitationSignalPhase(uint32_t base, uint16_t phase)
Sets the Phase value for the Excitation Signal. Phase values in the range [RDC_EXCITATION_FREQUENCY_M...
Definition: resolver/v0/resolver.h:856
int16_t Pg_cosGainBypassValue
Definition: resolver/v0/resolver.h:602
Struct to hold the peakHistogram Buckets for Ideal Sample Calculation by SW. once the auto ideal samp...
Definition: resolver/v0/resolver.h:670
static void RDC_enableBPF(uint32_t base, uint8_t core)
enables Band Pass Filter before DC Offset logic.
Definition: resolver/v0/resolver.h:1428
uint8_t t2Param6
Definition: resolver/v0/resolver.h:650
#define RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR
Interrupt Sources Macros.
Definition: resolver/v0/resolver.h:247
static void RDC_setDiagnosticsHighAmplitudeData(uint32_t base, uint8_t resolverCore, Diag_Mon_Sin_Cos_High_Amplitude *monitorData)
Sets the Monitor Sin or Cos saturation or very high amplitude (DOS) diagnostics Controls uint16_t hig...
Definition: resolver/v0/resolver.h:2817
uint16_t rotpeak_level
Definition: resolver/v0/resolver.h:471
bool sin_neg_zc_peak_mismatch_err
Definition: resolver/v0/resolver.h:465
static void RDC_disableSequencerInterrupt(uint32_t base)
Disable Sequencer Error Interrupt.
Definition: resolver/v0/resolver.h:1108
static void RDC_enableDcOffsetAutoCorrection(uint32_t base, uint8_t core)
Enables Auto DC Offset Correction from the estimated values Disables DC Offset Manual Correction logi...
Definition: resolver/v0/resolver.h:1492
static void RDC_setDiagnosticsSinCosGainDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_SinCos_Gain_drift_data *monitorData)
Sets the Monitor Sin or Cos Gain drift (DOS) diagnostics Controls int16_t gain_drift_threshold_hi - t...
Definition: resolver/v0/resolver.h:2274
static void RDC_getPeakHistogramObservationalData(uint32_t base, uint8_t resolverCore, PeakHistogram_observationalData *histogram)
Returns the Peak Histogram Bucket data.
Definition: resolver/v0/resolver.h:2976
int16_t Pg_cosPhaseBypassValue
Definition: resolver/v0/resolver.h:603
#define RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR
Definition: resolver/v0/resolver.h:264
uint8_t sin_multi_zc_error_count
Definition: resolver/v0/resolver.h:470
static void RDC_forceSequencerInterrupt(uint32_t base)
Force the Sequencer Error Interrupt.
Definition: resolver/v0/resolver.h:1140
uint16_t ExcFrq_socDelay
Definition: resolver/v0/resolver.h:627
bool Int_seqEnable
Definition: resolver/v0/resolver.h:632
Structure to hold the control/status data for Diagnostics mentioned under Monitor Sin or Cos offset d...
Definition: resolver/v0/resolver.h:367
uint8_t adcParam1
Definition: resolver/v0/resolver.h:645
static void RDC_disableIdealSampleBottomSampling(uint32_t base, uint8_t core)
Disables Bottom Sampling.
Definition: resolver/v0/resolver.h:1721
static void RDC_setIdealSampleDetectionThreshold(uint32_t base, uint8_t core, uint16_t absThresholdValue)
sets Ideal Sample Detetction Threshold. validates the sample for the Ideal Sample time detection comp...
Definition: resolver/v0/resolver.h:1613
uint8_t gain_drift_glitch_count
Definition: resolver/v0/resolver.h:393
#define RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR
Definition: resolver/v0/resolver.h:250
static void RDC_getDiagnosticsHighAmplitudeData(uint32_t base, uint8_t resolverCore, Diag_Mon_Sin_Cos_High_Amplitude *monitorData)
Returns the Monitor Sin or Cos saturation or very high amplitude (DOS) diagnostics data uint16_t high...
Definition: resolver/v0/resolver.h:2776
static int16_t RDC_getPhaseEstimation(uint32_t base, uint8_t core)
returns the Cos Phase Offset Estimation this can be used only if the RDC_getPhaseGainEstimationStatus...
Definition: resolver/v0/resolver.h:1944
static void RDC_enableCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
enable Core Interrupt
Definition: resolver/v0/resolver.h:1174
static void RDC_enablePhaseAutoCorrection(uint32_t base, uint8_t core)
Enables Phase Auto Correction.
Definition: resolver/v0/resolver.h:1846
Structure to hold the control/status data for Diagnostics mentioned under Monitor signal integrity by...
Definition: resolver/v0/resolver.h:490
#define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR
Definition: resolver/v0/resolver.h:259
static bool RDC_getPhaseGainEstimationStatus(uint32_t base, uint8_t core)
Gets status if the Phase Gain Estimation is complete.
Definition: resolver/v0/resolver.h:1746
uint8_t highAmplitude_glitchcount
Definition: resolver/v0/resolver.h:515
bool offset_drift_sin_hi
Definition: resolver/v0/resolver.h:372
int16_t gain_drift_threshold_hi
Definition: resolver/v0/resolver.h:391
int16_t BpfDc_manualSin
Definition: resolver/v0/resolver.h:587
uint8_t BpfDc_dcOffCal2
Definition: resolver/v0/resolver.h:586
#define RDC_SEQUENCER_MODE_0
or returned by RDC_getAdcSequencerOperationalMode()
Definition: resolver/v0/resolver.h:157
static int16_t RDC_getTrack2Angle(uint32_t base, uint8_t core)
Returns Signed 16 bit angle data from Track2 Loop. the data corresponds to -180 to 180 degrees angle ...
Definition: resolver/v0/resolver.h:2073
uint8_t Pg_estimationLimit
Definition: resolver/v0/resolver.h:597
bool t2Param9
Definition: resolver/v0/resolver.h:653
void RDC_paramsInit(RDC_configParams *params)
Inits the resolver Configuration parameters.
uint16_t rotfreq_level
Definition: resolver/v0/resolver.h:472
#define RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR
Definition: resolver/v0/resolver.h:265
uint8_t kvelfilt
Definition: resolver/v0/resolver.h:351
uint16_t excfreqdetected_cos
Definition: resolver/v0/resolver.h:438
#define RDC_INTERRUPT_SOURCE_ALL
Definition: resolver/v0/resolver.h:273
uint16_t PgParam4
Definition: resolver/v0/resolver.h:648
static void RDC_setDcOffsetManualCorrectionValue(uint32_t base, uint8_t core, int16_t sin, int16_t cos)
Sets the Sin, Cosine Manual Correction values for the Dc Offset block in the given resolver core.
Definition: resolver/v0/resolver.h:1516
uint8_t t2Param5
Definition: resolver/v0/resolver.h:649
int16_t sin_dc
Definition: resolver/v0/resolver.h:570
bool highAmplitude_cos_error
Definition: resolver/v0/resolver.h:519
uint16_t sinsqcossq_threshold_hi
Definition: resolver/v0/resolver.h:491
static void RDC_disableResolver(uint32_t base)
Disables the Resolver Operation.
Definition: resolver/v0/resolver.h:834
static void RDC_setExcitationSignalFrequencySelect(uint32_t base, uint8_t FrequencySel)
Sets the Excitation frequency value from the selected values.
Definition: resolver/v0/resolver.h:895
#define RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR
Definition: resolver/v0/resolver.h:266
static void RDC_setDiagnosticsSignalIntegritySquareSumData(uint32_t base, uint32_t resolverCore, Diag_Mon_Signal_Integrity_SinSq_CosSq *monitorData)
Sets the Monitor signal integrity by checking Sin2+Cos2=Constant (DOS) diagnostics Controls uint16_t ...
Definition: resolver/v0/resolver.h:2730
uint8_t ExcFrq_freqSel
Definition: resolver/v0/resolver.h:623
static void RDC_disableTrack2Boost(uint32_t base, uint8_t core)
disables the track2 Boost
Definition: resolver/v0/resolver.h:2032
static void RDC_clearCalibrationStatus(uint32_t base)
Clears Calibration Status for re-enabling Calibration Sequence.
Definition: resolver/v0/resolver.h:1318
int16_t phase_drift_threshold_hi
Definition: resolver/v0/resolver.h:415
uint16_t sinsqcossq_sinsq
Definition: resolver/v0/resolver.h:495
static void RDC_disablePhaseAutoCorrection(uint32_t base, uint8_t core)
Disables Phase Auto Correction.
Definition: resolver/v0/resolver.h:1865
static uint32_t RDC_getExcitationSignalPhase(uint32_t base)
Returns the Phase Value programmed for Excitation signal.
Definition: resolver/v0/resolver.h:876
static void RDC_setDiagnosticsCosPhaseDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_Cos_Phase_drift_data *monitorData)
Sets the Monitor Cos Phase drift (DOS) diagnostics Controls int16_t phase_drift_threshold_hi - the ph...
Definition: resolver/v0/resolver.h:2387
uint16_t ExcFrq_phase
Definition: resolver/v0/resolver.h:624
static void RDC_getAdcObservationalData(uint32_t base, uint8_t resolverCore, ADC_observationalData *AdcData)
Returns the Observational ADC data to struct type ADC_observationalData int16_t cos_adc - SW Observat...
Definition: resolver/v0/resolver.h:2938
static void RDC_enableAdcSingleEndedMode(uint32_t base)
Enable Single Ended Mode of operation.
Definition: resolver/v0/resolver.h:724
uint8_t t2Param7
Definition: resolver/v0/resolver.h:651
uint32_t Int_core0Interrupts
Definition: resolver/v0/resolver.h:633
static void RDC_enableIdealSampleBottomSampling(uint32_t base, uint8_t core)
Enables bottom Sampling. twice the sampling rate than disabled. the track2 loop runs twice the speed ...
Definition: resolver/v0/resolver.h:1702
int16_t phase_drift_threshold_lo
Definition: resolver/v0/resolver.h:416
bool excfreqdrift_sin_lo
Definition: resolver/v0/resolver.h:445
uint8_t sinsqcossq_glitchcount
Definition: resolver/v0/resolver.h:493
static bool RDC_getCalibrationStatus(uint32_t base)
Returns the Calibration Status.
Definition: resolver/v0/resolver.h:1302
bool gain_drift_cos_lo
Definition: resolver/v0/resolver.h:395
static void RDC_getDiagnosticsSinCosOffsetDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_SinCos_Offset_drift_data *monitorData)
Returns the Monitor Sin or Cos Offset Drift (DOS) diagnostics data int16_t offset_drift_threshold_hi ...
Definition: resolver/v0/resolver.h:2119
static void RDC_setCosPhaseBypass(uint32_t base, uint8_t core, uint16_t cosPhaseBypass)
sets the Cos Phase Manual Bypass Value
Definition: resolver/v0/resolver.h:1787
static void RDC_enableCalibration(uint32_t base)
Enables ADC Calibration.
Definition: resolver/v0/resolver.h:1351
Structure to hold the control/status data for Diagnostics mentioned under Monitor Sin or Cos Gain dri...
Definition: resolver/v0/resolver.h:390
uint16_t IdealSample_absThresholdValue
Definition: resolver/v0/resolver.h:591
static void RDC_disableExcitationSignalSyncIn(uint32_t base)
Disables the Excitation Signal Sync In.
Definition: resolver/v0/resolver.h:966
int16_t sin_pgc
Definition: resolver/v0/resolver.h:572
bool zero_cross_rot_en
Definition: resolver/v0/resolver.h:473
static void RDC_getDiagnosticsSinCosGainDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_SinCos_Gain_drift_data *monitorData)
Returns the Monitor Sin or Cos Gain drift (DOS) diagnostics data int16_t gain_drift_threshold_hi - th...
Definition: resolver/v0/resolver.h:2224
static void RDC_setAdcSequencerOperationalMode(uint32_t base, uint8_t operationalMode)
sets Sequencer Operational Mode Valid values are RDC_SEQUENCER_MODE_0 - ADC0 SAMPLES SIN AND ADC1 SAM...
Definition: resolver/v0/resolver.h:798
#define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR
Definition: resolver/v0/resolver.h:258
static void RDC_enableResolver(uint32_t base)
Enables the Resolver Operation.
Definition: resolver/v0/resolver.h:818
static void RDC_setAdcBurstCount(uint32_t base, uint8_t burstCount)
sets the ADC Burst count, samples to be averaged.
Definition: resolver/v0/resolver.h:707
static void RDC_enableSequencerInterrupt(uint32_t base)
Enable Sequencer Error Interrupt.
Definition: resolver/v0/resolver.h:1092
static uint8_t RDC_getIdealSampleTime(uint32_t base, uint8_t core)
Returns the Ideal Sample Time esitimated by the resolver core.
Definition: resolver/v0/resolver.h:1591
uint8_t Input_socWidth
Definition: resolver/v0/resolver.h:619
static void RDC_setDiagnosticsExcFreqDegradationData(uint32_t base, uint8_t resolverCore, Diag_Mon_ExcFreq_Degradataion_data *monitorData)
Sets the Monitor excitation frequency degradation or loss (DOS) diagnostics Controls uint16_t excfreq...
Definition: resolver/v0/resolver.h:2513
bool offset_drift_sin_lo
Definition: resolver/v0/resolver.h:373
uint16_t excfreqdrift_threshold_hi
Definition: resolver/v0/resolver.h:439
#define RDC_EXCITATION_FREQUENCY_20K
select 20KHz Excitation Sine Frequency
Definition: resolver/v0/resolver.h:209
static void RDC_getDiagnosticsSignalIntegritySquareSumData(uint32_t base, uint32_t resolverCore, Diag_Mon_Signal_Integrity_SinSq_CosSq *monitorData)
Returns the Monitor signal integrity by checking Sin2+Cos2=Constant (DOS) diagnostics data uint16_t s...
Definition: resolver/v0/resolver.h:2681
#define RDC_DC_OFFSET_SIN_ESTIMATION
Definition: resolver/v0/resolver.h:105
static void RDC_enablePhaseGainEstimation(uint32_t base, uint8_t core)
Enables Phase Gain Estimation in the background.
Definition: resolver/v0/resolver.h:1807
#define RDC_MAX_EXCITATION_AMPLITUDE
Maximum Excitation Signal Amplitude.
Definition: resolver/v0/resolver.h:89
Structure to hold the control/status data for Diagnostics mentioned under Monitor rotational signal i...
Definition: resolver/v0/resolver.h:462
static void RDC_clearExcitationSignalEventStatus(uint32_t base)
Clears SyncIn event status.
Definition: resolver/v0/resolver.h:1002
static void RDC_disableDcOffsetAutoCorrection(uint32_t base, uint8_t core)
Disbales Auto Offset correction from the estimated values Enables DC Offset Manual Correction logic.
Definition: resolver/v0/resolver.h:1470
uint8_t IdealParam2
Definition: resolver/v0/resolver.h:646
static void RDC_setPhaseGainEstimationTrainLimit(uint32_t base, uint8_t core, uint8_t pgEstimationLimit)
Sets the Phase Gain Estimation train limit. if the programmed value is x, 2^x rotations are considere...
Definition: resolver/v0/resolver.h:1766
#define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR
Definition: resolver/v0/resolver.h:267
uint8_t BpfDc_dcOffCal1
Definition: resolver/v0/resolver.h:585
static void RDC_forceCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
Force the Core Interrupt.
Definition: resolver/v0/resolver.h:1257
static void RDC_setExcitationSignalSocDelay(uint32_t base, uint16_t socDelay)
Sets the SOC Delay from the PWM Exciation Signal.
Definition: resolver/v0/resolver.h:1036
uint8_t IdealSample_sampleAdjustCount
Definition: resolver/v0/resolver.h:592
#define RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR
Definition: resolver/v0/resolver.h:256
#define RDC_EXCITATION_FREQUENCY_5K
or returned by RDC_getExcitationSignalFrequencySelect()
Definition: resolver/v0/resolver.h:203
int16_t offset_drift_threshold_hi
Definition: resolver/v0/resolver.h:368
static uint32_t RDC_getExcitationSignalPhaseInfo(uint32_t base)
Returns the latched value of the last pwm_sync_in rise event of the pwm phase. this is updated on eve...
Definition: resolver/v0/resolver.h:1020
Struct holds the Baseline Parameter values Can be passed to RDC_BaselineParametersInit(uint32_t base)...
Definition: resolver/v0/resolver.h:644
uint8_t cos_multi_zc_error_count
Definition: resolver/v0/resolver.h:469
uint8_t IdealSample_mode
Definition: resolver/v0/resolver.h:593
bool sin_multi_zc_error_err
Definition: resolver/v0/resolver.h:467
uint16_t sinsqcossq_threshold_lo
Definition: resolver/v0/resolver.h:492
int16_t cos_rec
Definition: resolver/v0/resolver.h:567
#define RDC_EXCITATION_FREQUENCY_10K
select 10KHz Excitation Sine Frequency
Definition: resolver/v0/resolver.h:206
static uint32_t RDC_getAdcSequencerOperationalMode(uint32_t base)
returns Sequencer Operational Mode Valid values are RDC_SEQUENCER_MODE_0 - ADC0 SAMPLES SIN AND ADC1 ...
Definition: resolver/v0/resolver.h:770
int16_t lowAmplitude_cos_value
Definition: resolver/v0/resolver.h:540
#define DebugP_assert(expression)
Function to call for assert check.
Definition: DebugP.h:177
bool excfreqdrift_hi
Definition: resolver/v0/resolver.h:443
bool Pg_estimationEnable
Definition: resolver/v0/resolver.h:596
static int32_t RDC_getTrack2Velocity(uint32_t base, uint8_t core)
Returns Signed 32 bit Velocity data from Track2 Loop.
Definition: resolver/v0/resolver.h:2092
uint8_t peakHistgoramBucket[20]
Definition: resolver/v0/resolver.h:671
static void RDC_disableBPF(uint32_t base, uint8_t core)
Disables Band Pass Filter Logic before DC Offset logic.
Definition: resolver/v0/resolver.h:1448
bool ExcFrq_enableSyncIn
Definition: resolver/v0/resolver.h:626
#define RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR
Definition: resolver/v0/resolver.h:255
static void RDC_setDiagnosticsWeakAmplitudeData(uint32_t base, uint8_t resolverCore, Diag_Mon_Sin_Cos_Weak_Amplitude *monitorData)
Sets the Monitor weak Sin or Cos signal below a threshold (LOS) diagnostics Controls uint16_t lowAmpl...
Definition: resolver/v0/resolver.h:2895
static void RDC_setExcitationSignalAmplitudeControl(uint32_t base, uint8_t amplitude)
set the Amplitude control for the excitation signal
Definition: resolver/v0/resolver.h:1055
static void RDC_setAdcSocWidth(uint32_t base, uint8_t socWidth)
sets the Start of Conversion Width for the ADC conversion
Definition: resolver/v0/resolver.h:684
static void RDC_getDiagnosticsExcFreqDegradationData(uint32_t base, uint8_t resolverCore, Diag_Mon_ExcFreq_Degradataion_data *monitorData)
Returns the Monitor excitation frequency degradation or loss (DOS) diagnostics data uint16_t excfreqd...
Definition: resolver/v0/resolver.h:2447
int16_t lowAmplitude_sin_value
Definition: resolver/v0/resolver.h:539
#define RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR
Definition: resolver/v0/resolver.h:263
uint8_t ExcFrq_amplitude
Definition: resolver/v0/resolver.h:625
static void RDC_getDiagnosticsCosPhaseDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_Cos_Phase_drift_data *monitorData)
Returns the Monitor Cos Phase drift (DOS) diagnostics data int16_t phase_drift_threshold_hi - the con...
Definition: resolver/v0/resolver.h:2343
#define RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR
Definition: resolver/v0/resolver.h:248
bool offset_drift_cos_hi
Definition: resolver/v0/resolver.h:370
static uint32_t RDC_getExcitationSignalEventStatus(uint32_t base)
returns if there is a sync in event after the RDC_enableResolver() has been called once this returns ...
Definition: resolver/v0/resolver.h:987
#define RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR
Definition: resolver/v0/resolver.h:257
bool Pg_autoCorrectionEnable
Definition: resolver/v0/resolver.h:600
Structure to hold the Observational Data reads int16_t cos_adc - SW Observational ADC data post latch...
Definition: resolver/v0/resolver.h:564
bool offset_drift_en
Definition: resolver/v0/resolver.h:374
Struct holds the RDC configurations Can be passed to RDC_paramsInit(RDC_configParams* params); RDC_in...
Definition: resolver/v0/resolver.h:616
bool gain_drift_cos_hi
Definition: resolver/v0/resolver.h:394