C2000™ Multicore Development User Guide

This guide describes various cores available in C2000™ devices and how other resources such as peripherals, memories, GPIOs are shared among these. It also talks about how to communicate and share data among different cores. This guide is written for F2838x family of devices, but this can also apply for other devices with some exceptions.

• 1. Introduction
• 2. Memory blocks available
• 3. Ownership assignment of shared resources
  • 3.1. LSxRAM
  • 3.2. GSx RAM
  • 3.3. Peripherals
  • 3.4. GPIOs
• 4. Communication between CPU1, CPU2 and CM cores
  • 4.1. Message RAMs
  • 4.2. IPC Flags and Command registers
  • 4.3. Trigger an interrupt (with no data) from one core to another
  • 4.4. Send a command from one core to another with interrupt
  • 4.5. Sending a large amount of data from one core to another
  • 4.6. Synchronize 2 cores
  • 4.7. IPC Message queues
• 5. Communication between C28x and CLA
• 6. Debugging multiple cores
  • 6.1. Loading program in multiple cores
  • 6.2. Loading program in CLA
  • 6.3. Exercise 1 - Multi-core Debug Example
  • 6.4. Viewing Memories/Registers/Expressions
  • 6.5. Exercise 1 - Multi-core Debug Example (continued)
• 7. Examples from C2000ware
  • 7.1. Exercise 2 - IPC example
  • 7.2. Exercise 3 - IPC example with message queues
  • 7.3. Exercise 4 - CLA example
  • 7.4. Exercise 5 - Dual core GPIO example
  • 7.5. Exercise 6 - CM example with shared peripheral
• 8. Frequently Asked Questions
• 9. Important Notice

For offline use, a PDF version of the guide is available here: C2000 Multicore Development User Guide