5. Communication between C28x and CLA

Each CPU subsystem contains a C28x core and a CLA core. C28x core can only communicate to the CLA core in its own subsystem. The IPC module is not available to CPU-CLA communication

For sharing data between C28x and CLA, CPU-CLA MSG RAMs can be used. The device includes dedicated MSG RAMs for CPU to CLA and CLA to CPU communication.

The following table lists out various CPU-CLA Message RAMs available in the device and its accessibility across different cores. This also includes the name of the driverlib macro which holds the base address of the Message RAM.

  • RW : Read and Write access

  • R : Read access

Table 5.1 CLA Message RAMs

Memory

C28x

CLA

Driverlib macro

CPU_TO_CLA MSG RAM
RW
R
CPUTOCLA_RAM_BASE
CLA_TO_CPU MSG RAM
R
RW
CLATOCPU_RAM_BASE

To send data from CPU to CLA, CPU needs to write the data in the CPUTOCLA_RAM which can be read by CLA and vice versa.

CLA tasks can be triggered by either C28x software or by peripheral events. C28x software can trigger CLA tasks by setting the corresponding bit in the MIFRC register. The driverlib function CLA_forceTasks does the same.

Note that the global variables defined in the .cla file are global to the cla source file, which means they are shared across CLA tasks, but not with the C28x core. All of the data shared between C28x and CLA must be defined in .c or .cpp file, and not in the .cla file.

Please refer to the c2000ware driverlib example which showcases how CPU triggers CLA tasks with CPU sending a data to CLA and CLA sending back the processed data. These examples are covered in Examples from C2000ware section.