3. Ownership assignment of shared resources¶
3.1. LSxRAM¶
The dual-core C2000 device includes dedicated LS RAMs for CPU1 and CPU2 subsystems. LSxRAM can be owned by the C28x core or by the CLA core. The ownership of LS RAM should be assigned by the C28x core in the respective subsystem.
By default, all the LS RAMs are configured as C28x only memory.
Configuration |
Register to be set |
Driverlib function |
|---|---|---|
C28x only memory
|
LSxMSEL.MSEL_LSx = 0
|
MemCfg_setLSRAMMasterSel (MEMCFG_SECT_LSx, MEMCFG_LSRAMMASTER_CPU_ONLY)
|
CLA program memory
|
LSxMSEL.MSEL_LSx = 1
LSxCLAPGM.CLAPGM_LSx = 1
|
MemCfg_setLSRAMMasterSel (MEMCFG_SECT_LSx, MEMCFG_LSRAMMASTER_CPU_CLA1)
MemCfg_setCLAMemType (MEMCFG_SECT_LSx, MEMCFG_CLA_MEM_PROGRAM)
|
Data memory shared
between C28x and CLA
|
LSxMSEL.MSEL_LSx = 1
LSxCLAPGM.CLAPGM_LSx = 0
|
MemCfg_setLSRAMMasterSel (MEMCFG_SECT_LSx, MEMCFG_LSRAMMASTER_CPU_CLA1)
MemCfg_setCLAMemType (MEMCFG_SECT_LSx, MEMCFG_CLA_MEM_DATA)
|
3.2. GSx RAM¶
GS RAMs are shared between CPU1 and CPU2 subsystems. The ownership of GS RAM should be assigned by CPU1.
By default, all the GS RAMs are owned by CPU1 subsystem.
Configuration |
Register to be set |
Driverlib function |
|---|---|---|
Owned by CPU1 subsystem
|
GSxMSEL.MSEL_GSx = 0
|
MemCfg_setGSRAMMasterSel (MEMCFG_SECT_GSx, MEMCFG_GSRAMMASTER_CPU1)
|
Owned by CPU2 subsystem
|
GSxMSEL.MSEL_GSx = 1
|
MemCfg_setGSRAMMasterSel (MEMCFG_SECT_GSx, MEMCFG_GSRAMMASTER_CPU2)
|
3.3. Peripherals¶
Most of the C28x peripherals are shared between CPU1 and CPU2. Please refer to the device datasheet for available peripherals.The ownership of the peripherals should be assigned by CPU1.
By default, all the peripherals are owned by CPU1.
Configuration |
Register to be set |
Driverlib function |
|---|---|---|
Owned by CPU1
|
CPUSELx.module = 0
|
SysCtl_selectCPUForPeripheral (peripheral, instance, SYSCTL_CPUSEL_CPU1)
|
Owned by CPU2
|
CPUSELx.module = 1
|
SysCtl_selectCPUForPeripheral (peripheral, instance, SYSCTL_CPUSEL_CPU2)
|
There are few peripherals such as CAN, MCAN, Ethernet and USB which are shared across CPU1, CPU2 and CM cores. The ownership of shared peripheral should be assigned by CPU1.
Configuration |
Register to be set |
Driverlib function |
|---|---|---|
Owned by CPU1
|
CPUSELx.bit.module = 0
PALLOCATE0.bit.module = 0
|
SysCtl_selectCPUForPeripheral (peripheral, instance, SYSCTL_CPUSEL_CPU1)
SysCtl_allocateSharedPeripheral (peripheral, 0)
|
Owned by CPU2
|
CPUSELx.bit.module = 1
PALLOCATE0.bit.module = 0
|
SysCtl_selectCPUForPeripheral (peripheral, instance, SYSCTL_CPUSEL_CPU2)
SysCtl_allocateSharedPeripheral (peripheral, 0)
|
Owned by CM
|
PALLOCATE0.bit.module = 1
|
SysCtl_allocateSharedPeripheral (peripheral, 1)
|
Note
The peripheral clock must be enabled by the owner core.
3.4. GPIOs¶
The GPIOs on the devices are shared across all the cores and the ownership should be assigned by the CPU1 core before using them.
By default, all the GPIOs are owned by CPU1.
Configuration |
Register to be set |
Driverlib function |
|---|---|---|
Owned by CPU1
|
GPxCSELy.bit.GPIOz = 0
|
GPIO_setMasterCore (pin, GPIO_CORE_CPU1)
|
Owned by CPU1.CLA
|
GPxCSELy.bit.GPIOz = 1
|
GPIO_setMasterCore (pin, GPIO_CORE_CPU1_CLA1)
|
Owned by CPU2
|
GPxCSELy.bit.GPIOz = 2
|
GPIO_setMasterCore (pin, GPIO_CORE_CPU2)
|
Owned by CPU2.CLA
|
GPxCSELy.bit.GPIOz = 3
|
GPIO_setMasterCore (pin, GPIO_CORE_CPU2_CLA1)
|
Owned by CM
|
GPxCSELy.bit.GPIOz = 4
|
GPIO_setMasterCore (pin, GPIO_CORE_CM)
|