AUX_EVCTL

Instance: AUX_EVCTL
Component: AUX_EVCTL
Base address: 0x400C5000


AUX Event Controller

TOP:AUX_EVCTL Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

VECCFG0

RW

32

0x0000 0000

0x0000 0000

0x400C 5000

VECCFG1

RW

32

0x0000 0000

0x0000 0004

0x400C 5004

SCEWEVSEL

RW

32

0x0000 0000

0x0000 0008

0x400C 5008

EVTOAONFLAGS

RW

32

0x0000 0000

0x0000 000C

0x400C 500C

EVTOAONPOL

RW

32

0x0000 0000

0x0000 0010

0x400C 5010

DMACTL

RW

32

0x0000 0000

0x0000 0014

0x400C 5014

SWEVSET

RW

32

0x0000 0000

0x0000 0018

0x400C 5018

EVSTAT0

RO

32

0x0000 0000

0x0000 001C

0x400C 501C

EVSTAT1

RO

32

0x0000 0000

0x0000 0020

0x400C 5020

EVTOMCUPOL

RW

32

0x0000 0000

0x0000 0024

0x400C 5024

EVTOMCUFLAGS

RW

32

0x0000 0000

0x0000 0028

0x400C 5028

COMBEVTOMCUMASK

RW

32

0x0000 0000

0x0000 002C

0x400C 502C

VECFLAGS

RW

32

0x0000 0000

0x0000 0034

0x400C 5034

EVTOMCUFLAGSCLR

RW

32

0x0000 0000

0x0000 0038

0x400C 5038

EVTOAONFLAGSCLR

RW

32

0x0000 0000

0x0000 003C

0x400C 503C

VECFLAGSCLR

RW

32

0x0000 0000

0x0000 0040

0x400C 5040

TOP:AUX_EVCTL Register Descriptions

TOP:AUX_EVCTL:VECCFG0

Address Offset 0x0000 0000
Physical Address 0x400C 5000 Instance 0x400C 5000
Description Vector Configuration 0

AUX_SCE wakeup vector 0 and 1 configuration
Type RW
Bits Field Name Description Type Reset
31:15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000
14 VEC1_POL Vector 1 trigger event polarity.

To manually trigger vector 1 execution:
- AUX_SCE must sleep.
- Set VEC1_EV to a known static value.
- Toggle VEC1_POL twice.
Value ENUM Name Description
0x0 RISE Rising edge triggers vector 1 execution.
0x1 FALL Falling edge triggers vector 1 execution.
RW 0
13 VEC1_EN Vector 1 trigger enable.

When enabled, VEC1_EV event with VEC1_POL polarity triggers a jump to vector # 1 when AUX_SCE sleeps.

Lower vectors (0) have priority.
Value ENUM Name Description
0x0 DIS Disable vector 1 trigger.
0x1 EN Enable vector 1 trigger.
RW 0
12:8 VEC1_EV Select vector 1 trigger source event.
Value ENUM Name Description
0x0 AON_RTC_CH2 EVSTAT0.AON_RTC_CH2
0x1 AUX_COMPA EVSTAT0.AUX_COMPA
0x2 AUX_COMPB EVSTAT0.AUX_COMPB
0x3 TDC_DONE EVSTAT0.TDC_DONE
0x4 TIMER0_EV EVSTAT0.TIMER0_EV
0x5 TIMER1_EV EVSTAT0.TIMER1_EV
0x6 SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE
0x7 ADC_DONE EVSTAT0.ADC_DONE
0x8 ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL
0x9 OBSMUX0 EVSTAT0.OBSMUX0
0xA OBSMUX1 EVSTAT0.OBSMUX1
0xB AON_SW EVSTAT0.AON_SW
0xC AON_PROG_WU EVSTAT0.AON_PROG_WU
0xD AUXIO0 EVSTAT0.AUXIO0
0xE AUXIO1 EVSTAT0.AUXIO1
0xF AUXIO2 EVSTAT0.AUXIO2
0x10 AUXIO3 EVSTAT1.AUXIO3
0x11 AUXIO4 EVSTAT1.AUXIO4
0x12 AUXIO5 EVSTAT1.AUXIO5
0x13 AUXIO6 EVSTAT1.AUXIO6
0x14 AUXIO7 EVSTAT1.AUXIO7
0x15 AUXIO8 EVSTAT1.AUXIO8
0x16 AUXIO9 EVSTAT1.AUXIO9
0x17 AUXIO10 EVSTAT1.AUXIO10
0x18 AUXIO11 EVSTAT1.AUXIO11
0x19 AUXIO12 EVSTAT1.AUXIO12
0x1A AUXIO13 EVSTAT1.AUXIO13
0x1B AUXIO14 EVSTAT1.AUXIO14
0x1C AUXIO15 EVSTAT1.AUXIO15
0x1D ACLK_REF EVSTAT1.ACLK_REF
0x1E MCU_EV EVSTAT1.MCU_EV
0x1F ADC_IRQ EVSTAT1.ADC_IRQ
RW 0b0 0000
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 VEC0_POL Vector 0 trigger event polarity.

To manually trigger vector 0 execution:
- AUX_SCE must sleep.
- Set VEC0_EV to a known static value.
- Toggle VEC0_POL twice.
Value ENUM Name Description
0x0 RISE Rising edge triggers vector 0 execution.
0x1 FALL Falling edge triggers vector 0 execution.
RW 0
5 VEC0_EN Vector 0 trigger enable.

When enabled, VEC0_EV event with VEC0_POL polarity triggers a jump to vector # 0 when AUX_SCE sleeps.
Value ENUM Name Description
0x0 DIS Disable vector 0 trigger.
0x1 EN Enable vector 0 trigger.
RW 0
4:0 VEC0_EV Select vector 0 trigger source event.
Value ENUM Name Description
0x0 AON_RTC_CH2 EVSTAT0.AON_RTC_CH2
0x1 AUX_COMPA EVSTAT0.AUX_COMPA
0x2 AUX_COMPB EVSTAT0.AUX_COMPB
0x3 TDC_DONE EVSTAT0.TDC_DONE
0x4 TIMER0_EV EVSTAT0.TIMER0_EV
0x5 TIMER1_EV EVSTAT0.TIMER1_EV
0x6 SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE
0x7 ADC_DONE EVSTAT0.ADC_DONE
0x8 ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL
0x9 OBSMUX0 EVSTAT0.OBSMUX0
0xA OBSMUX1 EVSTAT0.OBSMUX1
0xB AON_SW EVSTAT0.AON_SW
0xC AON_PROG_WU EVSTAT0.AON_PROG_WU
0xD AUXIO0 EVSTAT0.AUXIO0
0xE AUXIO1 EVSTAT0.AUXIO1
0xF AUXIO2 EVSTAT0.AUXIO2
0x10 AUXIO3 EVSTAT1.AUXIO3
0x11 AUXIO4 EVSTAT1.AUXIO4
0x12 AUXIO5 EVSTAT1.AUXIO5
0x13 AUXIO6 EVSTAT1.AUXIO6
0x14 AUXIO7 EVSTAT1.AUXIO7
0x15 AUXIO8 EVSTAT1.AUXIO8
0x16 AUXIO9 EVSTAT1.AUXIO9
0x17 AUXIO10 EVSTAT1.AUXIO10
0x18 AUXIO11 EVSTAT1.AUXIO11
0x19 AUXIO12 EVSTAT1.AUXIO12
0x1A AUXIO13 EVSTAT1.AUXIO13
0x1B AUXIO14 EVSTAT1.AUXIO14
0x1C AUXIO15 EVSTAT1.AUXIO15
0x1D ACLK_REF EVSTAT1.ACLK_REF
0x1E MCU_EV EVSTAT1.MCU_EV
0x1F ADC_IRQ EVSTAT1.ADC_IRQ
RW 0b0 0000

TOP:AUX_EVCTL:VECCFG1

Address Offset 0x0000 0004
Physical Address 0x400C 5004 Instance 0x400C 5004
Description Vector Configuration 1

AUX_SCE event vectors 2 and 3 configuration
Type RW
Bits Field Name Description Type Reset
31:15 RESERVED15 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000
14 VEC3_POL Vector 3 trigger event polarity.

To manually trigger vector 3 execution:
- AUX_SCE must sleep.
- Set VEC3_EV to a known static value.
- Toggle VEC3_POL twice.
Value ENUM Name Description
0x0 RISE Rising edge triggers vector 3 execution.
0x1 FALL Falling edge triggers vector 3 execution.
RW 0
13 VEC3_EN Vector 3 trigger enable.

When enabled, VEC3_EV event with VEC3_POL polarity triggers a jump to vector # 3 when AUX_SCE sleeps.

Lower vectors (0, 1, and 2) have priority.
Value ENUM Name Description
0x0 DIS Disable vector 3 trigger.
0x1 EN Enable vector 3 trigger.
RW 0
12:8 VEC3_EV Select vector 3 trigger source event.
Value ENUM Name Description
0x0 AON_RTC_CH2 EVSTAT0.AON_RTC_CH2
0x1 AUX_COMPA EVSTAT0.AUX_COMPA
0x2 AUX_COMPB EVSTAT0.AUX_COMPB
0x3 TDC_DONE EVSTAT0.TDC_DONE
0x4 TIMER0_EV EVSTAT0.TIMER0_EV
0x5 TIMER1_EV EVSTAT0.TIMER1_EV
0x6 SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE
0x7 ADC_DONE EVSTAT0.ADC_DONE
0x8 ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL
0x9 OBSMUX0 EVSTAT0.OBSMUX0
0xA OBSMUX1 EVSTAT0.OBSMUX1
0xB AON_SW EVSTAT0.AON_SW
0xC AON_PROG_WU EVSTAT0.AON_PROG_WU
0xD AUXIO0 EVSTAT0.AUXIO0
0xE AUXIO1 EVSTAT0.AUXIO1
0xF AUXIO2 EVSTAT0.AUXIO2
0x10 AUXIO3 EVSTAT1.AUXIO3
0x11 AUXIO4 EVSTAT1.AUXIO4
0x12 AUXIO5 EVSTAT1.AUXIO5
0x13 AUXIO6 EVSTAT1.AUXIO6
0x14 AUXIO7 EVSTAT1.AUXIO7
0x15 AUXIO8 EVSTAT1.AUXIO8
0x16 AUXIO9 EVSTAT1.AUXIO9
0x17 AUXIO10 EVSTAT1.AUXIO10
0x18 AUXIO11 EVSTAT1.AUXIO11
0x19 AUXIO12 EVSTAT1.AUXIO12
0x1A AUXIO13 EVSTAT1.AUXIO13
0x1B AUXIO14 EVSTAT1.AUXIO14
0x1C AUXIO15 EVSTAT1.AUXIO15
0x1D ACLK_REF EVSTAT1.ACLK_REF
0x1E MCU_EV EVSTAT1.MCU_EV
0x1F ADC_IRQ EVSTAT1.ADC_IRQ
RW 0b0 0000
7 RESERVED7 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
6 VEC2_POL Vector 2 trigger event polarity.

To manually trigger vector 2 execution:
- AUX_SCE must sleep.
- Set VEC2_EV to a known static value.
- Toggle VEC2_POL twice.
Value ENUM Name Description
0x0 RISE Rising edge triggers vector 2 execution.
0x1 FALL Falling edge triggers vector 2 execution.
RW 0
5 VEC2_EN Vector 2 trigger enable.

When enabled, VEC2_EV event with VEC2_POL polarity triggers a jump to vector # 2 when AUX_SCE sleeps.

Lower vectors (0 and 1) have priority.
Value ENUM Name Description
0x0 DIS Disable vector 2 trigger.
0x1 EN Enable vector 2 trigger.
RW 0
4:0 VEC2_EV Select vector 2 trigger source event.
Value ENUM Name Description
0x0 AON_RTC_CH2 EVSTAT0.AON_RTC_CH2
0x1 AUX_COMPA EVSTAT0.AUX_COMPA
0x2 AUX_COMPB EVSTAT0.AUX_COMPB
0x3 TDC_DONE EVSTAT0.TDC_DONE
0x4 TIMER0_EV EVSTAT0.TIMER0_EV
0x5 TIMER1_EV EVSTAT0.TIMER1_EV
0x6 SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE
0x7 ADC_DONE EVSTAT0.ADC_DONE
0x8 ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL
0x9 OBSMUX0 EVSTAT0.OBSMUX0
0xA OBSMUX1 EVSTAT0.OBSMUX1
0xB AON_SW EVSTAT0.AON_SW
0xC AON_PROG_WU EVSTAT0.AON_PROG_WU
0xD AUXIO0 EVSTAT0.AUXIO0
0xE AUXIO1 EVSTAT0.AUXIO1
0xF AUXIO2 EVSTAT0.AUXIO2
0x10 AUXIO3 EVSTAT1.AUXIO3
0x11 AUXIO4 EVSTAT1.AUXIO4
0x12 AUXIO5 EVSTAT1.AUXIO5
0x13 AUXIO6 EVSTAT1.AUXIO6
0x14 AUXIO7 EVSTAT1.AUXIO7
0x15 AUXIO8 EVSTAT1.AUXIO8
0x16 AUXIO9 EVSTAT1.AUXIO9
0x17 AUXIO10 EVSTAT1.AUXIO10
0x18 AUXIO11 EVSTAT1.AUXIO11
0x19 AUXIO12 EVSTAT1.AUXIO12
0x1A AUXIO13 EVSTAT1.AUXIO13
0x1B AUXIO14 EVSTAT1.AUXIO14
0x1C AUXIO15 EVSTAT1.AUXIO15
0x1D ACLK_REF EVSTAT1.ACLK_REF
0x1E MCU_EV EVSTAT1.MCU_EV
0x1F ADC_IRQ EVSTAT1.ADC_IRQ
RW 0b0 0000

TOP:AUX_EVCTL:SCEWEVSEL

Address Offset 0x0000 0008
Physical Address 0x400C 5008 Instance 0x400C 5008
Description Sensor Controller Engine Wait Event Selection

Configuration of this register controls bit index 7 in AUX_SCE:WUSTAT.EV_SIGNALS. This bit can be used by AUX_SCE WEV0, WEV1, BEV0 and BEV1 instructions
Type RW
Bits Field Name Description Type Reset
31:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
4:0 WEV7_EV Select event source to connect to AUX_SCE:WUSTAT.EV_SIGNALS bit 7.
Value ENUM Name Description
0x0 AON_RTC_CH2 EVSTAT0.AON_RTC_CH2
0x1 AUX_COMPA EVSTAT0.AUX_COMPA
0x2 AUX_COMPB EVSTAT0.AUX_COMPB
0x3 TDC_DONE EVSTAT0.TDC_DONE
0x4 TIMER0_EV EVSTAT0.TIMER0_EV
0x5 TIMER1_EV EVSTAT0.TIMER1_EV
0x6 SMPH_AUTOTAKE_DONE EVSTAT0.SMPH_AUTOTAKE_DONE
0x7 ADC_DONE EVSTAT0.ADC_DONE
0x8 ADC_FIFO_ALMOST_FULL EVSTAT0.ADC_FIFO_ALMOST_FULL
0x9 OBSMUX0 EVSTAT0.OBSMUX0
0xA OBSMUX1 EVSTAT0.OBSMUX1
0xB AON_SW EVSTAT0.AON_SW
0xC AON_PROG_WU EVSTAT0.AON_PROG_WU
0xD AUXIO0 EVSTAT0.AUXIO0
0xE AUXIO1 EVSTAT0.AUXIO1
0xF AUXIO2 EVSTAT0.AUXIO2
0x10 AUXIO3 EVSTAT1.AUXIO3
0x11 AUXIO4 EVSTAT1.AUXIO4
0x12 AUXIO5 EVSTAT1.AUXIO5
0x13 AUXIO6 EVSTAT1.AUXIO6
0x14 AUXIO7 EVSTAT1.AUXIO7
0x15 AUXIO8 EVSTAT1.AUXIO8
0x16 AUXIO9 EVSTAT1.AUXIO9
0x17 AUXIO10 EVSTAT1.AUXIO10
0x18 AUXIO11 EVSTAT1.AUXIO11
0x19 AUXIO12 EVSTAT1.AUXIO12
0x1A AUXIO13 EVSTAT1.AUXIO13
0x1B AUXIO14 EVSTAT1.AUXIO14
0x1C AUXIO15 EVSTAT1.AUXIO15
0x1D ACLK_REF EVSTAT1.ACLK_REF
0x1E MCU_EV EVSTAT1.MCU_EV
0x1F ADC_IRQ EVSTAT1.ADC_IRQ
RW 0b0 0000

TOP:AUX_EVCTL:EVTOAONFLAGS

Address Offset 0x0000 000C
Physical Address 0x400C 500C Instance 0x400C 500C
Description Events To AON Flags

This register contains a collection of event flags routed to AON_EVENT.

To clear an event flag, write to EVTOAONFLAGSCLR or write 0 to event flag in this register.
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 TIMER1_EV This event flag is set when level selected by EVTOAONPOL.TIMER1_EV occurs on EVSTAT0.TIMER1_EV. RW 0
7 TIMER0_EV This event flag is set when level selected by EVTOAONPOL.TIMER0_EV occurs on EVSTAT0.TIMER0_EV. RW 0
6 TDC_DONE This event flag is set when level selected by EVTOAONPOL.TDC_DONE occurs on EVSTAT0.TDC_DONE. RW 0
5 ADC_DONE This event flag is set when level selected by EVTOAONPOL.ADC_DONE occurs on EVSTAT0.ADC_DONE. RW 0
4 AUX_COMPB This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on EVSTAT0.AUX_COMPB. RW 0
3 AUX_COMPA This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on EVSTAT0.AUX_COMPA. RW 0
2 SWEV2 This event flag is set when software writes a 1 to SWEVSET.SWEV2. RW 0
1 SWEV1 This event flag is set when software writes a 1 to SWEVSET.SWEV1. RW 0
0 SWEV0 This event flag is set when software writes a 1 to SWEVSET.SWEV0. RW 0

TOP:AUX_EVCTL:EVTOAONPOL

Address Offset 0x0000 0010
Physical Address 0x400C 5010 Instance 0x400C 5010
Description Events To AON Polarity

Event source polarity configuration for EVTOAONFLAGS.
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 TIMER1_EV Select the level of EVSTAT0.TIMER1_EV that sets EVTOAONFLAGS.TIMER1_EV.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
7 TIMER0_EV Select the level of EVSTAT0.TIMER0_EV that sets EVTOAONFLAGS.TIMER0_EV.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
6 TDC_DONE Select level of EVSTAT0.TDC_DONE that sets EVTOAONFLAGS.TDC_DONE.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
5 ADC_DONE Select the level of EVSTAT0.ADC_DONE that sets EVTOAONFLAGS.ADC_DONE.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
4 AUX_COMPB Select the edge of EVSTAT0.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB.
Value ENUM Name Description
0x0 HIGH Rising edge
0x1 LOW Falling edge
RW 0
3 AUX_COMPA Select the edge of EVSTAT0.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA.
Value ENUM Name Description
0x0 HIGH Rising edge
0x1 LOW Falling edge
RW 0
2:0 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000

TOP:AUX_EVCTL:DMACTL

Address Offset 0x0000 0014
Physical Address 0x400C 5014 Instance 0x400C 5014
Description Direct Memory Access Control
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 REQ_MODE UDMA0 Request mode
Value ENUM Name Description
0x0 BURST Burst requests are generated on UDMA0 channel 7 when the condition configured in SEL is met.
0x1 SINGLE Single requests are generated on UDMA0 channel 7 when the condition configured in SEL is met.
RW 0
1 EN uDMA ADC interface enable.

0: Disable UDMA0 interface to ADC.
1: Enable UDMA0 interface to ADC.		 RW 0
0 SEL Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO data.
Value ENUM Name Description
0x0 FIFO_NOT_EMPTY UDMA0 trigger event will be generated when there are samples in the ADC FIFO.
0x1 FIFO_ALMOST_FULL UDMA0 trigger event will be generated when the ADC FIFO is almost full (3/4 full).
RW 0

TOP:AUX_EVCTL:SWEVSET

Address Offset 0x0000 0018
Physical Address 0x400C 5018 Instance 0x400C 5018
Description Software Event Set

Set software event flags from AUX domain to AON and MCU domains. CPUs in MCU domain can read the event flags from EVTOAONFLAGS and clear them in EVTOAONFLAGSCLR.

Use of these event flags is software-defined.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 SWEV2 Software event flag 2.

0: No effect.
1: Set software event flag 2.		 WO 0
1 SWEV1 Software event flag 1.

0: No effect.
1: Set software event flag 1.		 WO 0
0 SWEV0 Software event flag 0.

0: No effect.
1: Set software event flag 0.		 WO 0

TOP:AUX_EVCTL:EVSTAT0

Address Offset 0x0000 001C
Physical Address 0x400C 501C Instance 0x400C 501C
Description Event Status 0

Register holds events 0 thru 15 of the 32-bit event bus that is synchronous to AUX clock. The following subscribers use the asynchronous version of events in this register.
- AUX_ANAIF.
- AUX_TDC.
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 AUXIO2 AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2. RO 0
14 AUXIO1 AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1. RO 0
13 AUXIO0 AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0. RO 0
12 AON_PROG_WU AON_EVENT:AUXWUSEL.WU2_EV OR AON_EVENT:AUXWUSEL.WU1_EV OR AON_EVENT:AUXWUSEL.WU0_EV RO 0
11 AON_SW AON_WUC:AUXCTL.SWEV RO 0
10 OBSMUX1 Observation input 1 from IOC.
This event is configured by IOC:OBSAUXOUTPUT.SEL1.		 RO 0
9 OBSMUX0 Observation input 0 from IOC.
This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by IOC:OBSAUXOUTPUT.SEL_MISC.		 RO 0
8 ADC_FIFO_ALMOST_FULL AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL RO 0
7 ADC_DONE AUX_ANAIF ADC conversion done event. RO 0
6 SMPH_AUTOTAKE_DONE See AUX_SMPH:AUTOTAKE.SMPH_ID for description. RO 0
5 TIMER1_EV AUX_TIMER1_EV event, see AUX_TIMER:T1TARGET for description. RO 0
4 TIMER0_EV AUX_TIMER0_EV event, see AUX_TIMER:T0TARGET for description. RO 0
3 TDC_DONE AUX_TDC:STAT.DONE RO 0
2 AUX_COMPB Comparator B output RO 0
1 AUX_COMPA Comparator A output RO 0
0 AON_RTC_CH2 AON_RTC:EVFLAGS.CH2 RO 0

TOP:AUX_EVCTL:EVSTAT1

Address Offset 0x0000 0020
Physical Address 0x400C 5020 Instance 0x400C 5020
Description Event Status 1

Current event source levels, 31:16
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15 ADC_IRQ The logical function for this event is configurable.

When DMACTL.EN = 1 :
Event = UDMA0 Channel 7 done event OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW

When DMACTL.EN = 0 :
Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW

Bit 7 in UDMA0:DONEMASK must be 0.		 RO 0
14 MCU_EV Event from EVENT configured by EVENT:AUXSEL0. RO 0
13 ACLK_REF TDC reference clock.
It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by AUX_WUC:REFCLKCTL.REQ.		 RO 0
12 AUXIO15 AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7. RO 0
11 AUXIO14 AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6. RO 0
10 AUXIO13 AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5. RO 0
9 AUXIO12 AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4. RO 0
8 AUXIO11 AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3. RO 0
7 AUXIO10 AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2. RO 0
6 AUXIO9 AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1. RO 0
5 AUXIO8 AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0. RO 0
4 AUXIO7 AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7. RO 0
3 AUXIO6 AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6. RO 0
2 AUXIO5 AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5. RO 0
1 AUXIO4 AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4. RO 0
0 AUXIO3 AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3. RO 0

TOP:AUX_EVCTL:EVTOMCUPOL

Address Offset 0x0000 0024
Physical Address 0x400C 5024 Instance 0x400C 5024
Description Event To MCU Polarity

Event source polarity configuration for EVTOMCUFLAGS.
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 ADC_IRQ Select the event source level that sets EVTOMCUFLAGS.ADC_IRQ.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
9 OBSMUX0 Select the event source level that sets EVTOMCUFLAGS.OBSMUX0.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
8 ADC_FIFO_ALMOST_FULL Select the event source level that sets EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
7 ADC_DONE Select the event source level that sets EVTOMCUFLAGS.ADC_DONE.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
6 SMPH_AUTOTAKE_DONE Select the event source level that sets EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
5 TIMER1_EV Select the event source level that sets EVTOMCUFLAGS.TIMER1_EV.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
4 TIMER0_EV Select the event source level that sets EVTOMCUFLAGS.TIMER0_EV.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
3 TDC_DONE Select the event source level that sets EVTOMCUFLAGS.TDC_DONE.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
2 AUX_COMPB Select the event source level that sets EVTOMCUFLAGS.AUX_COMPB.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
1 AUX_COMPA Select the event source level that sets EVTOMCUFLAGS.AUX_COMPA.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0
0 AON_WU_EV Select the event source level that sets EVTOMCUFLAGS.AON_WU_EV.
Value ENUM Name Description
0x0 HIGH High level
0x1 LOW Low level
RW 0

TOP:AUX_EVCTL:EVTOMCUFLAGS

Address Offset 0x0000 0028
Physical Address 0x400C 5028 Instance 0x400C 5028
Description Events to MCU Flags

This register contains a collection of event flags routed to MCU domain.

To clear an event flag, write to EVTOMCUFLAGSCLR or write 0 to event flag in this register. Follow procedure described in AUX_SYSIF:WUCLR to clear AUX_WU_EV event flag.
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 ADC_IRQ This event flag is set when level selected by EVTOMCUPOL.ADC_IRQ occurs on EVSTAT0.ADC_IRQ. RW 0
9 OBSMUX0 This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs on EVSTAT0.MCU_OBSMUX0. RW 0
8 ADC_FIFO_ALMOST_FULL This event flag is set when level selected by EVTOMCUPOL.ADC_FIFO_ALMOST_FULL occurs on EVSTAT0.ADC_FIFO_ALMOST_FULL. RW 0
7 ADC_DONE This event flag is set when level selected by EVTOMCUPOL.ADC_DONE occurs on EVSTAT0.ADC_DONE. RW 0
6 SMPH_AUTOTAKE_DONE This event flag is set when level selected by EVTOMCUPOL.SMPH_AUTOTAKE_DONE occurs on EVSTAT0.SMPH_AUTOTAKE_DONE. RW 0
5 TIMER1_EV This event flag is set when level selected by EVTOMCUPOL.TIMER1_EV occurs on EVSTAT0.TIMER1_EV. RW 0
4 TIMER0_EV This event flag is set when level selected by EVTOMCUPOL.TIMER0_EV occurs on EVSTAT0.TIMER0_EV. RW 0
3 TDC_DONE This event flag is set when level selected by EVTOMCUPOL.TDC_DONE occurs on EVSTAT0.TDC_DONE. RW 0
2 AUX_COMPB This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on EVSTAT0.AUX_COMPB. RW 0
1 AUX_COMPA This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on EVSTAT0.AUX_COMPA. RW 0
0 AON_WU_EV This event flag is set when level selected by EVTOMCUPOL.AON_WU_EV occurs on the reduction-OR of the AUX_EVCTL:EVSTAT0.RTC_CH2_EV, AUX_EVCTL:EVSTAT0.AON_SW, and AUX_EVCTL:EVSTAT0.AON_PROG_WU events. RW 0

TOP:AUX_EVCTL:COMBEVTOMCUMASK

Address Offset 0x0000 002C
Physical Address 0x400C 502C Instance 0x400C 502C
Description Combined Event To MCU Mask

Select event flags in EVTOMCUFLAGS that contribute to the AUX_COMB event to EVENT and system CPU.

The AUX_COMB event is high as long as one or more of the included event flags are set.
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 ADC_IRQ EVTOMCUFLAGS.ADC_IRQ contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
9 OBSMUX0 EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
8 ADC_FIFO_ALMOST_FULL EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
7 ADC_DONE EVTOMCUFLAGS.ADC_DONE contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
6 SMPH_AUTOTAKE_DONE EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
5 TIMER1_EV EVTOMCUFLAGS.TIMER1_EV contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
4 TIMER0_EV EVTOMCUFLAGS.TIMER0_EV contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
3 TDC_DONE EVTOMCUFLAGS.TDC_DONE contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
2 AUX_COMPB EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event.

0: Exclude
1: Include.		 RW 0
1 AUX_COMPA EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0
0 AON_WU_EV EVTOMCUFLAGS.AON_WU_EV contribution to the AUX_COMB event.

0: Exclude.
1: Include.		 RW 0

TOP:AUX_EVCTL:VECFLAGS

Address Offset 0x0000 0034
Physical Address 0x400C 5034 Instance 0x400C 5034
Description Vector Flags

If a vector flag becomes 1 and AUX_SCE sleeps, AUX_SCE will wake up and execute the corresponding vector. The vector with the lowest index will execute first if multiple vectors flags are set. AUX_SCE must return to sleep to execute the next vector.

During execution of a vector, AUX_SCE must clear the vector flag that triggered execution. Write 1 to bit index n in VECFLAGSCLR to clear vector flag n.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3 VEC3 Vector flag 3.

The vector flag is set if the edge selected VECCFG1.VEC3_POL occurs on the event selected in VECCFG1.VEC3_EV.

The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to VECFLAGSCLR.VEC3.		 RW 0
2 VEC2 Vector flag 2.

The vector flag is set if the edge selected VECCFG1.VEC2_POL occurs on the event selected in VECCFG1.VEC2_EV.

The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to VECFLAGSCLR.VEC2.		 RW 0
1 VEC1 Vector flag 1.

The vector flag is set if the edge selected VECCFG0.VEC1_POL occurs on the event selected in VECCFG0.VEC1_EV.

The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to VECFLAGSCLR.VEC1.		 RW 0
0 VEC0 Vector flag 0.

The vector flag is set if the edge selected VECCFG0.VEC0_POL occurs on the event selected in VECCFG0.VEC0_EV.

The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to VECFLAGSCLR.VEC0.		 RW 0

TOP:AUX_EVCTL:EVTOMCUFLAGSCLR

Address Offset 0x0000 0038
Physical Address 0x400C 5038 Instance 0x400C 5038
Description Events To MCU Flags Clear

Clear event flags in EVTOMCUFLAGS.

In order to clear a level sensitive event flag, the event must be deasserted.
Type RW
Bits Field Name Description Type Reset
31:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000
10 ADC_IRQ Write 1 to clear EVTOMCUFLAGS.ADC_IRQ.

Read value is 0.		 WO 0
9 OBSMUX0 Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0.

Read value is 0.		 WO 0
8 ADC_FIFO_ALMOST_FULL Write 1 to clear EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL.

Read value is 0.		 WO 0
7 ADC_DONE Write 1 to clear EVTOMCUFLAGS.ADC_DONE.

Read value is 0.		 WO 0
6 SMPH_AUTOTAKE_DONE Write 1 to clear EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE.

Read value is 0.		 WO 0
5 TIMER1_EV Write 1 to clear EVTOMCUFLAGS.TIMER1_EV.

Read value is 0.		 WO 0
4 TIMER0_EV Write 1 to clear EVTOMCUFLAGS.TIMER0_EV.

Read value is 0.		 WO 0
3 TDC_DONE Write 1 to clear EVTOMCUFLAGS.TDC_DONE.

Read value is 0.		 WO 0
2 AUX_COMPB Write 1 to clear EVTOMCUFLAGS.AUX_COMPB.

Read value is 0.		 WO 0
1 AUX_COMPA Write 1 to clear EVTOMCUFLAGS.AUX_COMPA.

Read value is 0.		 WO 0
0 AON_WU_EV Write 1 to clear EVTOMCUFLAGS.AON_WU_EV.

Read value is 0.		 WO 0

TOP:AUX_EVCTL:EVTOAONFLAGSCLR

Address Offset 0x0000 003C
Physical Address 0x400C 503C Instance 0x400C 503C
Description Events To AON Clear

Clear event flags in EVTOAONFLAGS.

In order to clear a level sensitive event flag, the event must be deasserted.
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 TIMER1_EV Write 1 to clear EVTOAONFLAGS.TIMER1_EV.

Read value is 0.		 WO 0
7 TIMER0_EV Write 1 to clear EVTOAONFLAGS.TIMER0_EV.

Read value is 0.		 WO 0
6 TDC_DONE Write 1 to clear EVTOAONFLAGS.TDC_DONE.

Read value is 0.		 WO 0
5 ADC_DONE Write 1 to clear EVTOAONFLAGS.ADC_DONE.

Read value is 0.		 WO 0
4 AUX_COMPB Write 1 to clear EVTOAONFLAGS.AUX_COMPB.

Read value is 0.		 WO 0
3 AUX_COMPA Write 1 to clear EVTOAONFLAGS.AUX_COMPA.

Read value is 0.		 WO 0
2 SWEV2 Write 1 to clear EVTOAONFLAGS.SWEV2.

Read value is 0.		 WO 0
1 SWEV1 Write 1 to clear EVTOAONFLAGS.SWEV1.

Read value is 0.		 WO 0
0 SWEV0 Write 1 to clear EVTOAONFLAGS.SWEV0.

Read value is 0.		 WO 0

TOP:AUX_EVCTL:VECFLAGSCLR

Address Offset 0x0000 0040
Physical Address 0x400C 5040 Instance 0x400C 5040
Description Vector Flags Clear

Strobes for clearing flags in VECFLAGS.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3 VEC3 Clear vector flag 3.

0: No effect.
1: Clear VECFLAGS.VEC3.

Read value is 0.		 WO 0
2 VEC2 Clear vector flag 2.

0: No effect.
1: Clear VECFLAGS.VEC2.

Read value is 0.		 WO 0
1 VEC1 Clear vector flag 1.

0: No effect.
1: Clear VECFLAGS.VEC1.

Read value is 0.		 WO 0
0 VEC0 Clear vector flag 0.

0: No effect.
1: Clear VECFLAGS.VEC0.

Read value is 0.		 WO 0


© 2015 - 2016. Texas Instruments | All Rights Reserved