AUX_AIODIO1

Instance: AUX_AIODIO1
Component: AUX_AIODIO
Base address: 0x400C2000


AUX Analog/Digital Input Output Controller

TOP:AUX_AIODIO1 Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

GPIODOUT

RW

32

0x0000 0000

0x0000 0000

0x400C 2000

IOMODE

RW

32

0x0000 0000

0x0000 0004

0x400C 2004

GPIODIN

RO

32

0x0000 0000

0x0000 0008

0x400C 2008

GPIODOUTSET

RW

32

0x0000 0000

0x0000 000C

0x400C 200C

GPIODOUTCLR

RW

32

0x0000 0000

0x0000 0010

0x400C 2010

GPIODOUTTGL

RW

32

0x0000 0000

0x0000 0014

0x400C 2014

GPIODIE

RW

32

0x0000 0000

0x0000 0018

0x400C 2018

TOP:AUX_AIODIO1 Register Descriptions

TOP:AUX_AIODIO1:GPIODOUT

Address Offset 0x0000 0000
Physical Address 0x400C 2000 Instance 0x400C 2000
Description General Purpose Input Output Data Out

The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 IO7_0 Write 1 to bit index n in this bit vector to set AUXIO[8i+n].
Write 0 to bit index n in this bit vector to clear AUXIO[8i+n].		 RW 0x00

TOP:AUX_AIODIO1:IOMODE

Address Offset 0x0000 0004
Physical Address 0x400C 2004 Instance 0x400C 2004
Description Input Output Mode

This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:14 IO7 Select mode for AUXIO[8i+7].
Value ENUM Name Description
0x0 OUT Output Mode:

GPIODOUT bit 7 drives AUXIO[8i+7].
0x1 IN Input Mode:

When GPIODIE bit 7 is 0: AUXIO[8i+7] is enabled for analog signal transfer.

When GPIODIE bit 7 is 1: AUXIO[8i+7] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When GPIODOUT bit 7 is 0: AUXIO[8i+7] is driven low.

When GPIODOUT bit 7 is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When GPIODOUT bit 7 is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When GPIODOUT bit 7 is 1: AUXIO[8i+7] is driven high.
RW 0b00
13:12 IO6 Select mode for AUXIO[8i+6].
Value ENUM Name Description
0x0 OUT Output Mode:

GPIODOUT bit 6 drives AUXIO[8i+6].
0x1 IN Input Mode:

When GPIODIE bit 6 is 0: AUXIO[8i+6] is enabled for analog signal transfer.

When GPIODIE bit 6 is 1: AUXIO[8i+6] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When GPIODOUT bit 6 is 0: AUXIO[8i+6] is driven low.

When GPIODOUT bit 6 is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When GPIODOUT bit 6 is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When GPIODOUT bit 6 is 1: AUXIO[8i+6] is driven high.
RW 0b00
11:10 IO5 Select mode for AUXIO[8i+5].
Value ENUM Name Description
0x0 OUT Output Mode:

GPIODOUT bit 5 drives AUXIO[8i+5].
0x1 IN Input Mode:

When GPIODIE bit 5 is 0: AUXIO[8i+5] is enabled for analog signal transfer.

When GPIODIE bit 5 is 1: AUXIO[8i+5] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When GPIODOUT bit 5 is 0: AUXIO[8i+5] is driven low.

When GPIODOUT bit 5 is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When GPIODOUT bit 5 is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When GPIODOUT bit 5 is 1: AUXIO[8i+5] is driven high.
RW 0b00
9:8 IO4 Select mode for AUXIO[8i+4].
Value ENUM Name Description
0x0 OUT Output Mode:

GPIODOUT bit 4 drives AUXIO[8i+4].
0x1 IN Input Mode:

When GPIODIE bit 4 is 0: AUXIO[8i+4] is enabled for analog signal transfer.

When GPIODIE bit 4 is 1: AUXIO[8i+4] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When GPIODOUT bit 4 is 0: AUXIO[8i+4] is driven low.

When GPIODOUT bit 4 is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When GPIODOUT bit 4 is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When GPIODOUT bit 4 is 1: AUXIO[8i+4] is driven high.
RW 0b00
7:6 IO3 Select mode for AUXIO[8i+3].
Value ENUM Name Description
0x0 OUT Output Mode:

GPIODOUT bit 3 drives AUXIO[8i+3].
0x1 IN Input Mode:

When GPIODIE bit 3 is 0: AUXIO[8i+3] is enabled for analog signal transfer.

When GPIODIE bit 3 is 1: AUXIO[8i+3] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When GPIODOUT bit 3 is 0: AUXIO[8i+3] is driven low.

When GPIODOUT bit 3 is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When GPIODOUT bit 3 is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When GPIODOUT bit 3 is 1: AUXIO[8i+3] is driven high.
RW 0b00
5:4 IO2 Select mode for AUXIO[8i+2].
Value ENUM Name Description
0x0 OUT Output Mode:

GPIODOUT bit 2 drives AUXIO[8i+2].
0x1 IN Input Mode:

When GPIODIE bit 2 is 0: AUXIO[8i+2] is enabled for analog signal transfer.

When GPIODIE bit 2 is 1: AUXIO[8i+2] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When GPIODOUT bit 2 is 0: AUXIO[8i+2] is driven low.

When GPIODOUT bit 2 is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When GPIODOUT bit 2 is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When GPIODOUT bit 2 is 1: AUXIO[8i+2] is driven high.
RW 0b00
3:2 IO1 Select mode for AUXIO[8i+1].
Value ENUM Name Description
0x0 OUT Output Mode:

GPIODOUT bit 1 drives AUXIO[8i+1].
0x1 IN Input Mode:

When GPIODIE bit 1 is 0: AUXIO[8i+1] is enabled for analog signal transfer.

When GPIODIE bit 1 is 1: AUXIO[8i+1] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When GPIODOUT bit 1 is 0: AUXIO[8i+1] is driven low.

When GPIODOUT bit 1 is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When GPIODOUT bit 1 is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When GPIODOUT bit 1 is 1: AUXIO[8i+1] is driven high.
RW 0b00
1:0 IO0 Select mode for AUXIO[8i+0].
Value ENUM Name Description
0x0 OUT Output Mode:

GPIODOUT bit 0 drives AUXIO[8i+0].
0x1 IN Input Mode:

When GPIODIE bit 0 is 0: AUXIO[8i+0] is enabled for analog signal transfer.

When GPIODIE bit 0 is 1: AUXIO[8i+0] is enabled for digital input.
0x2 OPEN_DRAIN Open-Drain Mode:

When GPIODOUT bit 0 is 0: AUXIO[8i+0] is driven low.

When GPIODOUT bit 0 is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
0x3 OPEN_SOURCE Open-Source Mode:

When GPIODOUT bit 0 is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When GPIODOUT bit 0 is 1: AUXIO[8i+0] is driven high.
RW 0b00

TOP:AUX_AIODIO1:GPIODIN

Address Offset 0x0000 0008
Physical Address 0x400C 2008 Instance 0x400C 2008
Description General Purpose Input Output Data In

This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and I = 1 for AUX_AIODIO1.
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 IO7_0 Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set. Otherwise, bit n value is old. RO 0x00

TOP:AUX_AIODIO1:GPIODOUTSET

Address Offset 0x0000 000C
Physical Address 0x400C 200C Instance 0x400C 200C
Description General Purpose Input Output Data Out Set

Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 IO7_0 Write 1 to bit index n in this bit vector to set GPIODOUT bit n.

Read value is 0.		 RW 0x00

TOP:AUX_AIODIO1:GPIODOUTCLR

Address Offset 0x0000 0010
Physical Address 0x400C 2010 Instance 0x400C 2010
Description General Purpose Input Output Data Out Clear

Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 IO7_0 Write 1 to bit index n in this bit vector to clear GPIODOUT bit n.

Read value is 0.		 RW 0x00

TOP:AUX_AIODIO1:GPIODOUTTGL

Address Offset 0x0000 0014
Physical Address 0x400C 2014 Instance 0x400C 2014
Description General Purpose Input Output Data Out Toggle

Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 IO7_0 Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n.

Read value is 0.		 RW 0x00

TOP:AUX_AIODIO1:GPIODIE

Address Offset 0x0000 0018
Physical Address 0x400C 2018 Instance 0x400C 2018
Description General Purpose Input Output Digital Input Enable

This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and I = 1 for AUX_AIODIO1.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7:0 IO7_0 Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n].
Write 0 to bit index n in this bit vector to disable digital input buffer for AUXIO[8i+n].

You must enable the digital input buffer for AUXIO[8i+n] to read the pin value in GPIODIN.
You must disable the digital input buffer for analog input or pins that float to avoid current leakage.		 RW 0x00


© 2015 - 2016. Texas Instruments | All Rights Reserved