AUX_TDC

Instance: AUX_TDC
Component: AUX_TDC
Base address: 0x400C4000


AUX Time To Digital Converter

TOP:AUX_TDC Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

CTL

RW

32

0x0000 0000

0x0000 0000

0x400C 4000

STAT

RO

32

0x0000 0006

0x0000 0004

0x400C 4004

RESULT

RO

32

0x0000 0002

0x0000 0008

0x400C 4008

SATCFG

RW

32

0x0000 000F

0x0000 000C

0x400C 400C

TRIGSRC

RW

32

0x0000 0000

0x0000 0010

0x400C 4010

TRIGCNT

RW

32

0x0000 0000

0x0000 0014

0x400C 4014

TRIGCNTLOAD

RW

32

0x0000 0000

0x0000 0018

0x400C 4018

TRIGCNTCFG

RW

32

0x0000 0000

0x0000 001C

0x400C 401C

PRECTL

RW

32

0x0000 001F

0x0000 0020

0x400C 4020

PRECNT

RW

32

0x0000 0000

0x0000 0024

0x400C 4024

TOP:AUX_TDC Register Descriptions

TOP:AUX_TDC:CTL

Address Offset 0x0000 0000
Physical Address 0x400C 4000 Instance 0x400C 4000
Description Control
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 CMD TDC commands.
Value ENUM Name Description
0x0 CLR_RESULT Clear STAT.SAT, STAT.DONE, and RESULT.VALUE.

This is not needed as prerequisite for a measurement. Reliable clear is only guaranteed from IDLE state.
0x1 RUN_SYNC_START Synchronous counter start.

The counter looks for the opposite edge of the selected start event before it starts to count when the selected edge occurs. This guarantees an edge-triggered start and is recommended for frequency measurements.
0x2 RUN Asynchronous counter start.

The counter starts to count when the start event is high. To achieve precise edge-to-edge measurements you must ensure that the start event is low for at least 420 ns after you write this command.
0x3 ABORT Force TDC state machine back to IDLE state.

Never write this command while AUX_TDC:STAT.STATE equals CLR_CNT or WAIT_CLR_CNT_DONE.
WO 0b00

TOP:AUX_TDC:STAT

Address Offset 0x0000 0004
Physical Address 0x400C 4004 Instance 0x400C 4004
Description Status
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 SAT TDC measurement saturation flag.

0: Conversion has not saturated.
1: Conversion stopped due to saturation.

This field is cleared when a new measurement is started or when CLR_RESULT is written to CTL.CMD.		 RO 0
6 DONE TDC measurement complete flag.

0: TDC measurement has not yet completed.
1: TDC measurement has completed.

This field clears when a new TDC measurement starts or when you write CLR_RESULT to CTL.CMD.		 RO 0
5:0 STATE TDC state machine status.
Value ENUM Name Description
0x0 WAIT_START Current state is TDC_STATE_WAIT_START.
The fast-counter circuit looks for the start condition. The state machine waits for the fast-counter to increment.
0x4 WAIT_START_STOP_CNT_EN Current state is TDC_STATE_WAIT_STARTSTOPCNTEN.
The fast-counter circuit looks for the start condition. The state machine waits for the fast-counter to increment.
0x6 IDLE Current state is TDC_STATE_IDLE.
This is the default state after reset and abortion. State will change when you write CTL.CMD to either RUN_SYNC_START or RUN.
0x7 CLR_CNT Current state is TDC_STATE_CLRCNT. The fast-counter circuit is reset.
0x8 WAIT_STOP Current state is TDC_STATE_WAIT_STOP.
The state machine waits for the fast-counter circuit to stop.
0xC WAIT_STOP_CNTDWN Current state is TDC_STATE_WAIT_STOPCNTDOWN.
The fast-counter circuit looks for the stop condition. It will ignore a number of stop events configured in TRIGCNTLOAD.CNT.
0xE GET_RESULT Current state is TDC_STATE_GETRESULTS.
The state machine copies the counter value from the fast-counter circuit.
0xF POR Current state is TDC_STATE_POR.
This is the reset state.
0x16 WAIT_CLR_CNT_DONE Current state is TDC_STATE_WAIT_CLRCNT_DONE.
The state machine waits for fast-counter circuit to finish reset.
0x1E START_FALL Current state is TDC_WAIT_STARTFALL.
The fast-counter circuit waits for a falling edge on the start event.
0x2E FORCE_STOP Current state is TDC_FORCESTOP.
You wrote ABORT to CTL.CMD to abort the TDC measurement.
RO 0b00 0110

TOP:AUX_TDC:RESULT

Address Offset 0x0000 0008
Physical Address 0x400C 4008 Instance 0x400C 4008
Description Result

Result of last TDC conversion
Type RO
Bits Field Name Description Type Reset
31:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
24:0 VALUE TDC conversion result.

The result of the TDC conversion is given in number of clock edges of the clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and falling edges are counted.

If TDC counter saturates, VALUE is slightly higher than SATCFG.LIMIT, as it takes a non-zero time to stop the measurement. Hence, the maximum value of this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT to R24.		 RO 0b0 0000 0000 0000 0000 0000 0010

TOP:AUX_TDC:SATCFG

Address Offset 0x0000 000C
Physical Address 0x400C 400C Instance 0x400C 400C
Description Saturation Configuration
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 LIMIT Saturation limit.

The flag STAT.SAT is set when the TDC counter saturates.

Values not enumerated are not supported
Value ENUM Name Description
0x3 R12 Result bit 12: TDC conversion saturates and stops when RESULT.VALUE[12] is set.
0x4 R13 Result bit 13: TDC conversion saturates and stops when RESULT.VALUE[13] is set.
0x5 R14 Result bit 14: TDC conversion saturates and stops when RESULT.VALUE[14] is set.
0x6 R15 Result bit 15: TDC conversion saturates and stops when RESULT.VALUE[15] is set.
0x7 R16 Result bit 16: TDC conversion saturates and stops when RESULT.VALUE[16] is set.
0x8 R17 Result bit 17: TDC conversion saturates and stops when RESULT.VALUE[17] is set.
0x9 R18 Result bit 18: TDC conversion saturates and stops when RESULT.VALUE[18] is set.
0xA R19 Result bit 19: TDC conversion saturates and stops when RESULT.VALUE[19] is set.
0xB R20 Result bit 20: TDC conversion saturates and stops when RESULT.VALUE[20] is set.
0xC R21 Result bit 21: TDC conversion saturates and stops when RESULT.VALUE[21] is set.
0xD R22 Result bit 22: TDC conversion saturates and stops when RESULT.VALUE[22] is set.
0xE R23 Result bit 23: TDC conversion saturates and stops when RESULT.VALUE[23] is set.
0xF R24 Result bit 24: TDC conversion saturates and stops when RESULT.VALUE[24] is set.
RW 0xF

TOP:AUX_TDC:TRIGSRC

Address Offset 0x0000 0010
Physical Address 0x400C 4010 Instance 0x400C 4010
Description Trigger Source

Select source and polarity for TDC start and stop events. See the Technical Reference Manual for event timing requirements.
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13 STOP_POL Polarity of stop source.

Change only while STAT.STATE is IDLE.
Value ENUM Name Description
0x0 HIGH TDC conversion stops when high level is detected.
0x1 LOW TDC conversion stops when low level is detected.
RW 0
12:8 STOP_SRC Select stop source from the asynchronous AUX event bus.

Change only while STAT.STATE is IDLE.
Value ENUM Name Description
0x0 AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2
0x1 AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA
0x2 AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB
0x3 ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N
0x4 TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV
0x5 TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV
0x6 SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE
0x7 ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE
0x8 ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL
0x9 OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0
0xA OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1
0xB AON_SW AUX_EVCTL:EVSTAT0.AON_SW
0xC AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU
0xD AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
0xE AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
0xF AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
0x10 AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3
0x11 AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4
0x12 AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5
0x13 AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6
0x14 AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7
0x15 AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8
0x16 AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9
0x17 AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10
0x18 AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11
0x19 AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12
0x1A AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13
0x1B AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14
0x1C AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15
0x1D ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF
0x1E MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV
0x1F TDC_PRE Select TDC Prescaler event which is generated by configuration of PRECTL.
RW 0b0 0000
7:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
5 START_POL Polarity of start source.

Change only while STAT.STATE is IDLE.
Value ENUM Name Description
0x0 HIGH TDC conversion starts when high level is detected.
0x1 LOW TDC conversion starts when low level is detected.
RW 0
4:0 START_SRC Select start source from the asynchronous AUX event bus.

Change only while STAT.STATE is IDLE.
Value ENUM Name Description
0x0 AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2
0x1 AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA
0x2 AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB
0x3 ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N
0x4 TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV
0x5 TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV
0x6 SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE
0x7 ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE
0x8 ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL
0x9 OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0
0xA OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1
0xB AON_SW AUX_EVCTL:EVSTAT0.AON_SW
0xC AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU
0xD AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
0xE AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
0xF AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
0x10 AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3
0x11 AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4
0x12 AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5
0x13 AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6
0x14 AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7
0x15 AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8
0x16 AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9
0x17 AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10
0x18 AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11
0x19 AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12
0x1A AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13
0x1B AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14
0x1C AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15
0x1D ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF
0x1E MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV
0x1F TDC_PRE Select TDC Prescaler event which is generated by configuration of PRECTL.
RW 0b0 0000

TOP:AUX_TDC:TRIGCNT

Address Offset 0x0000 0014
Physical Address 0x400C 4014 Instance 0x400C 4014
Description Trigger Counter

Stop-counter control and status.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 CNT Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1.

Read CNT to get the remaining number of stop events to ignore during a TDC measurement.

Write CNT to update the remaining number of stop events to ignore during a TDC measurement. The TDC measurement ignores updates of CNT if there are no more stop events left to ignore.

When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the start of the measurement.		 RW 0x0000

TOP:AUX_TDC:TRIGCNTLOAD

Address Offset 0x0000 0018
Physical Address 0x400C 4018 Instance 0x400C 4018
Description Trigger Counter Load

Stop-counter load.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 CNT Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1.

To measure frequency of an event source:
- Set start event equal to stop event.
- Set CNT to number of periods to measure. Both 0 and 1 values measures a single event source period.

To measure pulse width of an event source:
- Set start event source equal to stop event source.
- Select different polarity for start and stop event.
- Set CNT to 0.

To measure time from the start event to the Nth stop event when N > 1:
- Select different start and stop event source.
- Set CNT to (N-1).

See the Technical Reference Manual for event timing requirements.

When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start of the measurement.		 RW 0x0000

TOP:AUX_TDC:TRIGCNTCFG

Address Offset 0x0000 001C
Physical Address 0x400C 401C Instance 0x400C 401C
Description Trigger Counter Configuration

Stop-counter configuration.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 EN Enable stop-counter.

0: Disable stop-counter.
1: Enable stop-counter.

Change only while STAT.STATE is IDLE.		 RW 0

TOP:AUX_TDC:PRECTL

Address Offset 0x0000 0020
Physical Address 0x400C 4020 Instance 0x400C 4020
Description Prescaler Control

The prescaler can be used to count events that are faster than the AUX clock frequency.
It can be used to:
- count pulses on a specified event from the asynchronous event bus.
- prescale a specified event from the asynchronous event bus.

To use the prescaler output as an event source in TDC measurements you must set both TRIGSRC.START_SRC and TRIGSRC.STOP_SRC to AUX_TDC_PRE.

It is recommended to use the prescaler when the signal frequency to measure exceeds 1/10th of the AUX clock frequency.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00 0000
7 RESET_N Prescaler reset.

0: Reset prescaler.
1: Release reset of prescaler.

AUX_TDC_PRE event becomes 0 when you reset the prescaler.		 RW 0
6 RATIO Prescaler ratio.

This controls how often the AUX_TDC_PRE event is generated by the prescaler.
Value ENUM Name Description
0x0 DIV16 Prescaler divides input by 16.

AUX_TDC_PRE event has a rising edge for every 16 rising edges of the input. AUX_TDC_PRE event toggles on every 8th rising edge of the input.
0x1 DIV64 Prescaler divides input by 64.

AUX_TDC_PRE event has a rising edge for every 64 rising edges of the input. AUX_TDC_PRE event toggles on every 32nd rising edge of the input.
RW 0
5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
4:0 SRC Prescaler event source.

Select an event from the asynchronous AUX event bus to connect to the prescaler input.

Configure only while RESET_N is 0.
Value ENUM Name Description
0x0 AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2
0x1 AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA
0x2 AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB
0x3 ISRC_RESET AUX_ANAIF:ISRCCTL.RESET_N
0x4 TIMER0_EV AUX_EVCTL:EVSTAT0.TIMER0_EV
0x5 TIMER1_EV AUX_EVCTL:EVSTAT0.TIMER1_EV
0x6 SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT0.SMPH_AUTOTAKE_DONE
0x7 ADC_DONE AUX_EVCTL:EVSTAT0.ADC_DONE
0x8 ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT0.ADC_FIFO_ALMOST_FULL
0x9 OBSMUX0 AUX_EVCTL:EVSTAT0.OBSMUX0
0xA OBSMUX1 AUX_EVCTL:EVSTAT0.OBSMUX1
0xB AON_SW AUX_EVCTL:EVSTAT0.AON_SW
0xC AON_PROG_WU AUX_EVCTL:EVSTAT0.AON_PROG_WU
0xD AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
0xE AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
0xF AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
0x10 AUXIO3 AUX_EVCTL:EVSTAT1.AUXIO3
0x11 AUXIO4 AUX_EVCTL:EVSTAT1.AUXIO4
0x12 AUXIO5 AUX_EVCTL:EVSTAT1.AUXIO5
0x13 AUXIO6 AUX_EVCTL:EVSTAT1.AUXIO6
0x14 AUXIO7 AUX_EVCTL:EVSTAT1.AUXIO7
0x15 AUXIO8 AUX_EVCTL:EVSTAT1.AUXIO8
0x16 AUXIO9 AUX_EVCTL:EVSTAT1.AUXIO9
0x17 AUXIO10 AUX_EVCTL:EVSTAT1.AUXIO10
0x18 AUXIO11 AUX_EVCTL:EVSTAT1.AUXIO11
0x19 AUXIO12 AUX_EVCTL:EVSTAT1.AUXIO12
0x1A AUXIO13 AUX_EVCTL:EVSTAT1.AUXIO13
0x1B AUXIO14 AUX_EVCTL:EVSTAT1.AUXIO14
0x1C AUXIO15 AUX_EVCTL:EVSTAT1.AUXIO15
0x1D ACLK_REF AUX_EVCTL:EVSTAT1.ACLK_REF
0x1E MCU_EV AUX_EVCTL:EVSTAT1.MCU_EV
0x1F ADC_IRQ AUX_EVCTL:EVSTAT1.ADC_IRQ
RW 0b1 1111

TOP:AUX_TDC:PRECNT

Address Offset 0x0000 0024
Physical Address 0x400C 4024 Instance 0x400C 4024
Description Prescaler Counter
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 CNT Prescaler counter value.

Write a value to CNT to capture the value of the 16-bit prescaler counter into CNT. Read CNT to get the captured value.

The read value gets 1 LSB uncertainty if the event source level rises when you release the reset.

You must capture the prescaler counter value when the event source level is stable, either high or low:
- Disable AUX I/O input buffer to clamp AUXIO event low.
- Disable COMPA to clamp AUX_COMPA event low.
The read value can in general get 1 LSB uncertainty when you gate the event source asynchronously.

Please note the following:
- The prescaler counter is reset to 2 by PRECTL.RESET_N.
- The captured value is 2 when the number of rising edges on prescaler input is less than 3. Otherwise, captured value equals number of event pulses - 1.		 RW 0x0000


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