Instance: UDMA0
Component: UDMA
Base address: 0x40020000
ARM Micro Direct Memory Access Controller
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RO |
32 |
0x001F 0000 |
0x0000 0000 |
0x4002 0000 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0004 |
0x4002 0004 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4002 0008 |
|
|
RO |
32 |
0x0000 0200 |
0x0000 000C |
0x4002 000C |
|
|
RO |
32 |
0xFFFF 1EFF |
0x0000 0010 |
0x4002 0010 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0014 |
0x4002 0014 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4002 0018 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 001C |
0x4002 001C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x4002 0020 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0024 |
0x4002 0024 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x4002 0028 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 002C |
0x4002 002C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0x4002 0030 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0034 |
0x4002 0034 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x4002 0038 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 003C |
0x4002 003C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 004C |
0x4002 004C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0504 |
0x4002 0504 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0520 |
0x4002 0520 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x4002 0000 | Instance | 0x4002 0000 |
| Description | Status | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | TEST | 0x0: Controller does not include the integration test logic 0x1: Controller includes the integration test logic 0x2: Undefined ... 0xF: Undefined |
RO | 0x0 | ||
| 27:21 | RESERVED21 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
| 20:16 | TOTALCHANNELS | Register value returns number of available uDMA channels minus one. For example a read out value of: 0x00: Show that the controller is configured to use 1 uDMA channel 0x01: Shows that the controller is configured to use 2 uDMA channels ... 0x1F: Shows that the controller is configured to use 32 uDMA channels (32-1=31=0x1F) |
RO | 0b1 1111 | ||
| 15:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| 7:4 | STATE | Current state of the control state machine. State can be one of the following: 0x0: Idle 0x1: Reading channel controller data 0x2: Reading source data end pointer 0x3: Reading destination data end pointer 0x4: Reading source data 0x5: Writing destination data 0x6: Waiting for uDMA request to clear 0x7: Writing channel controller data 0x8: Stalled 0x9: Done 0xA: Peripheral scatter-gather transition 0xB: Undefined ... 0xF: Undefined. |
RO | 0x0 | ||
| 3:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 0 | MASTERENABLE | Shows the enable status of the controller as configured by CFG.MASTERENABLE: 0: Controller is disabled 1: Controller is enabled |
RO | 0 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0x4002 0004 | Instance | 0x4002 0004 |
| Description | Configuration | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0x00 0000 | ||
| 7:5 | PRTOCTRL | Sets the AHB-Lite bus protocol protection state by controlling the AHB signal HProt[3:1] as follows: Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring. Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring. Bit [5] Controls HProt[1] to indicate if a privileged access is occurring. When bit [n] = 1 then the corresponding HProt bit is high. When bit [n] = 0 then the corresponding HProt bit is low. This field controls HProt[3:1] signal for all transactions initiated by uDMA except two transactions below: - the read from the address indicated by source address pointer - the write to the address indicated by destination address pointer HProt[3:1] for these two exceptions can be controlled by dedicated fields in the channel configutation descriptor. |
WO | 0b000 | ||
| 4:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0x0 | ||
| 0 | MASTERENABLE | Enables the controller: 0: Disables the controller 1: Enables the controller |
WO | 0 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0x4002 0008 | Instance | 0x4002 0008 |
| Description | Channel Control Data Base Pointer | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:10 | BASEPTR | This register point to the base address for the primary data structures of each DMA channel. This is not stored in module, but in system memory, thus space must be allocated for this usage when DMA is in usage | RW | 0b00 0000 0000 0000 0000 0000 | ||
| 9:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 | ||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0x4002 000C | Instance | 0x4002 000C |
| Description | Channel Alternate Control Data Base Pointer | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | BASEPTR | This register shows the base address for the alternate data structures and is calculated by module, thus read only | RO | 0x0000 0200 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0x4002 0010 | Instance | 0x4002 0010 |
| Description | Channel Wait On Request Status | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CHNLSTATUS | Channel wait on request status: Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch, this channel may come out of active state even if request is still present. Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it keeps channel Ch in active state until the requests are deasserted. This handshake is necessary for channels where the requester is in an asynchronous domain or can run at slower clock speed than uDMA |
RO | 0xFFFF 1EFF | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0x4002 0014 | Instance | 0x4002 0014 |
| Description | Channel Software Request | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CHNLS | Set the appropriate bit to generate a software uDMA request on the corresponding uDMA channel Bit [Ch] = 0: Does not create a uDMA request for channel Ch Bit [Ch] = 1: Creates a uDMA request for channel Ch Writing to a bit where a uDMA channel is not implemented does not create a uDMA request for that channel |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0x4002 0018 | Instance | 0x4002 0018 |
| Description | Channel Set UseBurst | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CHNLS | Returns the useburst status, or disables individual channels from generating single uDMA requests. The value R is the arbitration rate and stored in the controller data structure. Read as: Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on channel C. The controller performs 2^R, or single, bus transfers. Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests. The controller only responds to burst transfer requests and performs 2^R transfers. Write as: Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0. Bit [Ch] = 1: Disables single transfer requests on channel Ch. The controller performs 2^R transfers for burst requests. Writing to a bit where a uDMA channel is not implemented has no effect |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 001C | ||
| Physical Address | 0x4002 001C | Instance | 0x4002 001C |
| Description | Channel Clear UseBurst | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CHNLS | Set the appropriate bit to enable single transfer requests. Write as: Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer requests. Bit [Ch] = 1: Enables single transfer requests on channel Ch. Writing to a bit where a DMA channel is not implemented has no effect. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0x4002 0020 | Instance | 0x4002 0020 |
| Description | Channel Set Request Mask | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CHNLS | Returns the burst and single request mask status, or disables the corresponding channel from generating uDMA requests. Read as: Bit [Ch] = 0: External requests are enabled for channel Ch. Bit [Ch] = 1: External requests are disabled for channel Ch. Write as: Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests. Bit [Ch] = 1: Disables uDMA burst request channel [C] and uDMA single request channel [C] input from generating uDMA requests. Writing to a bit where a uDMA channel is not implemented has no effect |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0x4002 0024 | Instance | 0x4002 0024 |
| Description | Clear Channel Request Mask | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CHNLS | Set the appropriate bit to enable DMA request for the channel. Write as: Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel C from generating requests. Bit [Ch] = 1: Enables channel [C] to generate DMA requests. Writing to a bit where a DMA channel is not implemented has no effect. |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0028 | ||
| Physical Address | 0x4002 0028 | Instance | 0x4002 0028 |
| Description | Set Channel Enable | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CHNLS | Returns the enable status of the channels, or enables the corresponding channels. Read as: Bit [Ch] = 0: Channel Ch is disabled. Bit [Ch] = 1: Channel Ch is enabled. Write as: Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel Bit [Ch] = 1: Enables channel Ch Writing to a bit where a DMA channel is not implemented has no effect |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 002C | ||
| Physical Address | 0x4002 002C | Instance | 0x4002 002C |
| Description | Clear Channel Enable | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CHNLS | Set the appropriate bit to disable the corresponding uDMA channel. Write as: Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels. Bit [Ch] = 1: Disables channel Ch Writing to a bit where a uDMA channel is not implemented has no effect |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0030 | ||
| Physical Address | 0x4002 0030 | Instance | 0x4002 0030 |
| Description | Channel Set Primary-Alternate | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CHNLS | Returns the channel control data structure status, or selects the alternate data structure for the corresponding uDMA channel. Read as: Bit [Ch] = 0: uDMA channel Ch is using the primary data structure. Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure. Write as: Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel Bit [Ch] = 1: Selects the alternate data structure for channel Ch Writing to a bit where a uDMA channel is not implemented has no effect |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0034 | ||
| Physical Address | 0x4002 0034 | Instance | 0x4002 0034 |
| Description | Channel Clear Primary-Alternate | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CHNLS | Clears the appropriate bit to select the primary data structure for the corresponding uDMA channel. Write as: Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate data structure. Bit [Ch] = 1: Selects the primary data structure for channel Ch. Writing to a bit where a uDMA channel is not implemented has no effect |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0038 | ||
| Physical Address | 0x4002 0038 | Instance | 0x4002 0038 |
| Description | Set Channel Priority | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CHNLS | Returns the channel priority mask status, or sets the channel priority to high. Read as: Bit [Ch] = 0: uDMA channel Ch is using the default priority level. Bit [Ch] = 1: uDMA channel Ch is using a high priority level. Write as: Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch to the default priority level. Bit [Ch] = 1: Channel Ch uses the high priority level. Writing to a bit where a uDMA channel is not implemented has no effect |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 003C | ||
| Physical Address | 0x4002 003C | Instance | 0x4002 003C |
| Description | Clear Channel Priority | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CHNLS | Clear the appropriate bit to select the default priority level for the specified uDMA channel. Write as: Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to the high priority level. Bit [Ch] = 1: Channel Ch uses the default priority level. Writing to a bit where a uDMA channel is not implemented has no effect |
WO | 0x0000 0000 | ||
| Address Offset | 0x0000 004C | ||
| Physical Address | 0x4002 004C | Instance | 0x4002 004C |
| Description | Error Status and Clear | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | STATUS | Returns the status of bus error flag in uDMA, or clears this bit Read as: 0: No bus error detected 1: Bus error detected Write as: 0: No effect, status of bus error flag is unchanged. 1: Clears the bus error flag. |
RW | 0 | ||
| Address Offset | 0x0000 0504 | ||
| Physical Address | 0x4002 0504 | Instance | 0x4002 0504 |
| Description | Channel Request Done | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CHNLS | Reflects the uDMA done status for the given channel, channel [Ch]. It's a sticky done bit. Unless cleared by writing a 1, it holds the value of 1. Read as: Bit [Ch] = 0: Request has not completed for channel Ch Bit [Ch] = 1: Request has completed for the channel Ch Writing a 1 to individual bits would clear the corresponding bit. Write as: Bit [Ch] = 0: No effect. Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 |
RW | 0x0000 0000 | ||
| Address Offset | 0x0000 0520 | ||
| Physical Address | 0x4002 0520 | Instance | 0x4002 0520 |
| Description | Channel Request Done Mask | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | CHNLS | Controls the propagation of the uDMA done and active state to the assigned peripheral. Specifically used for software channels. Read as: Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from reaching to the peripherals. Note that the uDMA done state for channel [Ch] is blocked from contributing to generation of combined uDMA done signal Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from reaching to the peripherals. Note that the uDMA done state for channel [Ch] is not blocked from contributing to generation of combined uDMA done signal Write as: Bit [Ch] = 0: Allows uDMA done and active stat to propagate to the peripherals. Note that this disables uDMA done state for channel [Ch] from contributing to generation of combined uDMA done signal Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the peripherals. Note that this enables uDMA done for channel [Ch] to contribute to generation of combined uDMA done signal. |
RW | 0x0000 0000 | ||
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