Instance: AON_WUC
Component: AON_WUC
Base address: 0x40091000
This component control the Wakeup controller residing in the AON domain.
Note: This module is only supporting 32 bit ReadWrite access from MCU
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4009 1000 |
|
|
RW |
32 |
0x0000 0001 |
0x0000 0004 |
0x4009 1004 |
|
|
RW |
32 |
0x0000 000F |
0x0000 0008 |
0x4009 1008 |
|
|
RW |
32 |
0x0000 0001 |
0x0000 000C |
0x4009 100C |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x4009 1010 |
|
|
RW |
32 |
0x0380 0000 |
0x0000 0014 |
0x4009 1014 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4009 1018 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x4009 1020 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4009 1024 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0x4009 1030 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0034 |
0x4009 1034 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x4009 1038 |
|
|
RW |
32 |
0x0000 0100 |
0x0000 0040 |
0x4009 1040 |
|
|
RW |
32 |
0x0B99 A02F |
0x0000 0044 |
0x4009 1044 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x4009 1000 | Instance | 0x4009 1000 |
| Description | MCU Clock Management This register contains bitfields related to the MCU clock. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
| 2 | RCOSC_HF_CAL_DONE | MCU bootcode will set this bit when RCOSC_HF is calibrated. The FLASH can not be used until this bit is set. 1: RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up. 0: RCOSC_HF is not yet calibrated, ie FLASH must not assume that the SCLK_HF is safe |
RW | 0 | |||||||||||
| 1:0 | PWR_DWN_SRC | Controls the clock source for the entire MCU domain while MCU is requesting powerdown. When MCU requests powerdown with SCLK_HF as source, then WUC will switch over to this clock source during powerdown, and automatically switch back to SCLK_HF when MCU is no longer requesting powerdown and system is back in active mode.
|
RW | 0b00 | |||||||||||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0x4009 1004 | Instance | 0x4009 1004 |
| Description | AUX Clock Management This register contains bitfields that are relevant for setting up the clock to the AUX domain. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
| 31:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||
| 12:11 | PWR_DWN_SRC | When AUX requests powerdown with SCLK_HF as source, then WUC will switch over to this clock source during powerdown, and automatically switch back to SCLK_HF when AUX system is back in active mode
|
RW | 0b00 | |||||||||||||||||||||||||||||
| 10:8 | SCLK_HF_DIV | Select the AUX clock divider for SCLK_HF NB: It is not supported to change the AUX clock divider while SCLK_HF is active source for AUX
|
RW | 0b000 | |||||||||||||||||||||||||||||
| 7:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 | |||||||||||||||||||||||||||||
| 2:0 | SRC | Selects the clock source for AUX: NB: Switching the clock source is guaranteed to be glitchless
|
RW | 0b001 | |||||||||||||||||||||||||||||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0x4009 1008 | Instance | 0x4009 1008 |
| Description | MCU Configuration This register contains power management related bitfields for the MCU domain. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||
| 31:18 | RESERVED18 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 | ||||||||||||||||||||
| 17 | VIRT_OFF | Internal. Only to be used through TI provided API. | RW | 0 | ||||||||||||||||||||
| 16 | FIXED_WU_EN | Internal. Only to be used through TI provided API. | RW | 0 | ||||||||||||||||||||
| 15:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | ||||||||||||||||||||
| 3:0 | SRAM_RET_EN | MCU SRAM is partitioned into 4 banks . This register controls which of the banks that has retention during MCU power off
|
RW | 0xF | ||||||||||||||||||||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0x4009 100C | Instance | 0x4009 100C |
| Description | AUX Configuration This register contains power management related signals for the AUX domain. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | RAM_RET_EN | This bit controls retention mode for the AUX_RAM:BANK0: 0: Retention is disabled 1: Retention is enabled NB: If retention is disabled, the AUX_RAM will be powered off when it would otherwise be put in retention mode |
RW | 1 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0x4009 1010 | Instance | 0x4009 1010 |
| Description | AUX Control This register contains events and control signals for the AUX domain. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | RESET_REQ | Reset request for AUX. Writing 1 to this register will assert reset to AUX. The reset will be held until the bit is cleared again. 0: AUX reset pin will be deasserted 1: AUX reset pin will be asserted |
RW | 0 | ||
| 30:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||
| 2 | SCE_RUN_EN | Enables (1) or disables (0) AUX_SCE execution. AUX_SCE execution will begin when AUX Domain is powered and either this or AUX_SCE:CTL.CLK_EN is set. Setting this bit will assure that AUX_SCE execution starts as soon as AUX power domain is woken up. ( AUX_SCE:CTL.CLK_EN will be reset to 0 if AUX power domain has been off) 0: AUX_SCE execution will be disabled if AUX_SCE:CTL.CLK_EN is 0 1: AUX_SCE execution is enabled. |
RW | 0 | ||
| 1 | SWEV | Writing 1 sets the software event to the AUX domain, which can be read through AUX_WUC:WUEVFLAGS.AON_SW. This event is normally cleared by AUX_SCE through the AUX_WUC:WUEVCLR.AON_SW. It can also be cleared by writing 0 to this register. Reading 0 means that there is no outstanding software event for AUX. Note that it can take up to 1,5 SCLK_LF clock cycles to clear the event from AUX. |
RW | 0 | ||
| 0 | AUX_FORCE_ON | Forces the AUX domain into active mode, overriding the requests from AUX_WUC:PWROFFREQ, AUX_WUC:PWRDWNREQ and AUX_WUC:MCUBUSCTL. Note that an ongoing AUX_WUC:PWROFFREQ will complete before this bit will set the AUX domain into active mode. MCU must set this bit in order to access the AUX peripherals. The AUX domain status can be read from PWRSTAT.AUX_PD_ON 0: AUX is allowed to Power Off, Power Down or Disconnect. 1: AUX Power OFF, Power Down or Disconnect requests will be overruled |
RW | 0 | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0x4009 1014 | Instance | 0x4009 1014 |
| Description | Power Status This register is used to monitor various power management related signals in AON. Most signals are for test, calibration and debug purpose only, and others can be used to detect that AUX or JTAG domains are powered up. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 0000 1110 0000 0000 0000 | ||
| 9 | AUX_PWR_DWN | Indicates the AUX powerdown state when AUX domain is powered up. 0: Active mode 1: AUX Powerdown request has been granted |
RO | 0 | ||
| 8:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 6 | JTAG_PD_ON | Indicates JTAG power state: 0: JTAG is powered off 1: JTAG is powered on |
RO | 0 | ||
| 5 | AUX_PD_ON | Indicates AUX power state: 0: AUX is not ready for use ( may be powered off or in power state transition ) 1: AUX is powered on, connected to bus and ready for use, |
RO | 0 | ||
| 4 | MCU_PD_ON | Indicates MCU power state: 0: MCU Power sequencing is not yet finalized and MCU_AONIF registers may not be reliable 1: MCU Power sequencing is finalized and all MCU_AONIF registers are reliable |
RO | 0 | ||
| 3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 2 | AUX_BUS_CONNECTED | Indicates that AUX Bus is connected: 0: AUX bus is not connected 1: AUX bus is connected ( idle_ack = 0 ) |
RO | 0 | ||
| 1 | AUX_RESET_DONE | Indicates Reset Done from AUX: 0: AUX is being reset 1: AUX reset is released |
RO | 0 | ||
| 0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| Address Offset | 0x0000 0018 | ||
| Physical Address | 0x4009 1018 | Instance | 0x4009 1018 |
| Description | Shutdown Control This register contains bitfields required for entering shutdown mode |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
| 0 | EN | Writing a 1 to this bit forces a shutdown request to be registered and all I/O values to be latched - in the PAD ring, possibly enabling I/O wakeup. Writing 0 will cancel a registered shutdown request and open th I/O latches residing in the PAD ring. A registered shutdown request takes effect the next time power down conditions exists. At this time, the will not enter Powerdown mode, but instead it will turn off all internal powersupplies, effectively putting the device into Shutdown mode. |
RW | 0 | ||
| Address Offset | 0x0000 0020 | ||
| Physical Address | 0x4009 1020 | Instance | 0x4009 1020 |
| Description | Control 0 This register contains various chip level control and debug bitfields. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | ||
| 8 | PWR_DWN_DIS | Controls whether MCU and AUX requesting to be powered off will enable a transition to powerdown: 0: Enabled 1: Disabled |
RW | 0 | ||
| 7:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x0 | ||
| 3 | AUX_SRAM_ERASE | Internal. Only to be used through TI provided API. | WO | 0 | ||
| 2 | MCU_SRAM_ERASE | Internal. Only to be used through TI provided API. | WO | 0 | ||
| 1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| Address Offset | 0x0000 0024 | ||
| Physical Address | 0x4009 1024 | Instance | 0x4009 1024 |
| Description | Control 1 This register contains various chip level control and debug bitfields. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 0000 0000 0000 0000 0000 0000 0000 | ||
| 1 | MCU_RESET_SRC | Indicates source of last MCU Voltage Domain warm reset request: 0: MCU SW reset 1: JTAG reset This bit can only be cleared by writing a 1 to it |
RW | 0 | ||
| 0 | MCU_WARM_RESET | Indicates type of last MCU Voltage Domain reset: 0: Last MCU reset was not a warm reset 1: Last MCU reset was a warm reset (requested from MCU or JTAG as indicated in MCU_RESET_SRC) This bit can only be cleared by writing a 1 to it |
RW | 0 | ||
| Address Offset | 0x0000 0030 | ||
| Physical Address | 0x4009 1030 | Instance | 0x4009 1030 |
| Description | Recharge Controller Configuration This register sets all relevant patameters for controlling the recharge algorithm. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | ADAPTIVE_EN | Enable adaptive recharge Note: Recharge can be turned completely of by setting MAX_PER_E=7 and MAX_PER_M=31 and this bitfield to 0 |
RW | 0 | ||
| 30:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
| 23:20 | C2 | Gain factor for adaptive recharge algorithm period_new=period * ( 1+/-(2^-C1+2^-C2) ) Valid values for C2 is 2 to 10 Note: Rounding may cause adaptive recharge not to start for very small values of both Gain and Initial period. Criteria for algorithm to start is MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 |
RW | 0x0 | ||
| 19:16 | C1 | Gain factor for adaptive recharge algorithm period_new=period * ( 1+/-(2^-C1+2^-C2) ) Valid values for C1 is 1 to 10 Note: Rounding may cause adaptive recharge not to start for very small values of both Gain and Initial period. Criteria for algorithm to start is MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 |
RW | 0x0 | ||
| 15:11 | MAX_PER_M | This register defines the maximum period that the recharge algorithm can take, i.e. it defines the maximum number of cycles between 2 recharges. The maximum number of cycles is specified with a 5 bit mantissa and 3 bit exponent: MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E This field sets the mantissa of MAXCYCLES |
RW | 0b0 0000 | ||
| 10:8 | MAX_PER_E | This register defines the maximum period that the recharge algorithm can take, i.e. it defines the maximum number of cycles between 2 recharges. The maximum number of cycles is specified with a 5 bit mantissa and 3 bit exponent: MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E This field sets the exponent MAXCYCLES |
RW | 0b000 | ||
| 7:3 | PER_M | Number of 32 KHz clocks between activation of recharge controller For recharge algorithm, PERIOD is the initial period when entering powerdown mode. The adaptive recharge algorithm will not change this register PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent: This field sets the Mantissa of the Period. PERIOD=(PER_M*16+15)*2^PER_E |
RW | 0b0 0000 | ||
| 2:0 | PER_E | Number of 32 KHz clocks between activation of recharge controller For recharge algorithm, PERIOD is the initial period when entering powerdown mode. The adaptive recharge algorithm will not change this register PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent: This field sets the Exponent of the Period. PERIOD=(PER_M*16+15)*2^PER_E |
RW | 0b000 | ||
| Address Offset | 0x0000 0034 | ||
| Physical Address | 0x4009 1034 | Instance | 0x4009 1034 |
| Description | Recharge Controller Status This register controls various status registers which are updated during recharge. The register is mostly intended for test and debug. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | ||
| 19:16 | VDDR_SMPLS | The last 4 VDDR samples, bit 0 being the newest. The register is being updated in every recharge period with a shift left, and bit 0 is updated with the last VDDR sample, ie a 1 is shiftet in in case VDDR > VDDR_threshold just before recharge starts. Otherwise a 0 will be shifted in. |
RO | 0x0 | ||
| 15:0 | MAX_USED_PER | The maximum value of recharge period seen with VDDR>threshold. The VDDR voltage is compared against the threshold voltage at just before each recharge. If VDDR is above threshold, MAX_USED_PER is updated with max ( current recharge peride; MAX_USED_PER ) This way MAX_USED_PER can track the recharge period where VDDR is decharged to the threshold value. We can therefore use the value as an indication of the leakage current during recharge. This bitfield is cleared to 0 when writing this register. |
RW | 0x0000 | ||
| Address Offset | 0x0000 0038 | ||
| Physical Address | 0x4009 1038 | Instance | 0x4009 1038 |
| Description | Oscillator Configuration This register sets the period for Amplitude compensation requests sent to the oscillator control system. The amplitude compensations is only applicable when XOSC_HF is running in low power mode. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7:3 | PER_M | Number of 32 KHz clocks between oscillator amplitude calibrations. When this counter expires, an oscillator amplitude compensation is triggered immediately in Active mode. When this counter expires in Powerdown mode an internal flag is set such that the amplitude compensation is postponed until the next recharge occurs. The Period will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent PERIOD=(PER_M*16+15)*2^PER_E This field sets the mantissa Note: Oscillator amplitude calibration is turned of when both this bitfield and PER_E are set to 0 |
RW | 0b0 0000 | ||
| 2:0 | PER_E | Number of 32 KHz clocks between oscillator amplitude calibrations. When this counter expires, an oscillator amplitude compensation is triggered immediately in Active mode. When this counter expires in Powerdown mode an internal flag is set such that the amplitude compensation is postponed until the next recharge occurs. The Period will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent PERIOD=(PER_M*16+15)*2^PER_E This field sets the exponent Note: Oscillator amplitude calibration is turned of when both PER_M and this bitfield are set to 0 |
RW | 0b000 | ||
| Address Offset | 0x0000 0040 | ||
| Physical Address | 0x4009 1040 | Instance | 0x4009 1040 |
| Description | JTAG Configuration This register contains control for configuration of the JTAG domain,- hereunder access permissions for each TAP. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | ||
| 8 | JTAG_PD_FORCE_ON | Controls JTAG PowerDomain power state: 0: Controlled exclusively by debug subsystem. (JTAG Powerdomain will be powered off unless a debugger is attached) 1: JTAG Power Domain is forced on, independent of debug subsystem. NB: The reset value causes JTAG Power Domain to be powered on by default. Software must clear this bit to turn off the JTAG Power Domain |
RW | 1 | ||
| 7:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0x00 | ||
| Address Offset | 0x0000 0044 | ||
| Physical Address | 0x4009 1044 | Instance | 0x4009 1044 |
| Description | JTAG USERCODE Boot code copies the JTAG USERCODE to this register from where it is forwarded to the debug subsystem. |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | USER_CODE | 32-bit JTAG USERCODE register feeding main JTAG TAP NB: This field can be locked |
RW | 0x0B99 A02F | ||
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