Digital Signal Processors Software

TI Embedded Software Products

All TI Developer Network Products

MSP430_DLL 3_04_002_007 Product Download Page

Build date: 04292014

The MSP debug stack (MSPDS) for all MSP430 devices consists of a dynamic link library as well as embedded firmware that runs on flash emulation tools (FETs) such as the MSP-FET, MSP-FET430UIF or eZ emulators. It is the bridging element between all PC software and all MSP430 microcontroller derivatives and handles tasks such as code download, stepping through code, break point handling and so forth. The MSP Debug Stack is used in IDEs such as Code Composer Studio (CCS), IAR's Embedded Workbench for MSP430 or other tools like Smart RF Studio or Elprotronic's FlashPro430.

Included in

  • CCSv6.0.1( P2 package)

New Device Support

  • MSP430FR2033 Family
  • MSP430F6736A Family
  • MSP430FG6626 Family

New Features

  • MSP-FET BSL support - I2C and UART BSL
    Can be activated via invalid baud rate commands
    9620 Tristate of all UART/ BSL pins – no current flow into target device
    9621 Configure UART communication without handshake (default start behaviour)
    9622 Configure UART communication with handshake
    9623 Voltage configuration command. Set target VCC hard to 3.3V
    9601 BSL-Entry sequence + Power up 3.3V (UART BSL)
    100000(1) BSL-Entry sequence + Power up 3.3V (I2C BSL)
    400000(1) BSL-Entry sequence + Power up 3.3V (I2C BSL)
    8001 Enable MSP-FET debugger mode - disable of MSP-FET BSL mode

  • During MSP-FET BSL mode the debugger mode is disabled
  • Over-current protection of JTAG/I2C/UART and VCC supply lines is switched of in MSP-FET BSL mode
  • In MSP-FET UART BSL mode only fixed baud rates are supported - 9600, 14400, 19200, 28800, 38400, 56000, 57600 and 115200


  • Improved EnergyTrace stability on longer runs
  • Improved stability during UIF firmware update from v2 to v3
  • SMCLK no longer listed for clock control on MSP430i2040
  • Changed voltage of 3000mV to 3300mV during UIF start-up
  • Changed MSP-FET UART lines power up state - UART lines are configured to High-Z during MSP-FET start-up
  • Changed MSP-FET UART to only support fixed baud rates - 9600, 14400, 19200, 28800, 38400, 56000, 57600 and 115200

Bug Fixes

  • Fixed clock control module definitions For MSP430FR5969/MSP430FR6989
  • Fixed potential race condition in communication with Fet (could get out of sync)
  • Fixed potential race condition between events (eg. LPMx.5) and API calls
  • Fixed memory leak when receiving asynchronous events (breakpoints, trace, ...)
  • Fixed case of hex digits when writing Intel Hex (now upper case)
  • Fixed debug access affect LPM current consumption on FR5969
  • Fixed Race conditions during LPM5/breakpoint events

Known Issues

  • On devices with FLL, clock control does not allow to keep clocks running, while the device is halted and the clock is sourced by the FLL
  • V1.3 of UIF does not work in SBW2 mode with 2.2nf cap on reset line
  • eZ-FET UART might lose bytes with 115k baud (no handshake enabled) and DMA as data loopback on target device
  • MSP-FET EEM access to F149 and L092 devices is only possible with JTAG speed slow

Older Releases

  • 2_04_007_001
  • 2_04_008_002
  • 2_04_009_001
  • 3_02_001_009
  • 3_02_003_015
  • 3_02_004_005
  • 3_02_005_004
  • 3_03_000_006
  • 3_03_001_003
  • 3_03_001_004
  • 3_04_000_020
  • 3_04_001_000

  • Legend

    Locked Fill in Form. Approved users receive download URL in 1 minute.   my.TI Login Required my.TI Login required.
    Locked Fill in Form. TI will contact you in 1-2+ business days.   No login required Immediate download (no login required).

    MSP430_DLL Product Downloads
    Title Description Size
    Unlocked MSP430 DLL 27432K
    No Login MD5 Checksums 4K

    Related Links

    Tue Apr 29 04:11:25 CDT 2014