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MSP430_DLL 3_04_001_000 Product Download Page

Build date: 04292014

The MSP debug stack (MSPDS) for all MSP430 devices consists of a dynamic link library as well as embedded firmware that runs on flash emulation tools (FETs) such as the MSP-FET, MSP-FET430UIF or eZ emulators. It is the bridging element between all PC software and all MSP430 microcontroller derivatives and handles tasks such as code download, stepping through code, break point handling and so forth. The MSP Debug Stack is used in IDEs such as Code Composer Studio (CCS), IAR's Embedded Workbench for MSP430 or other tools like Smart RF Studio or Elprotronic's FlashPro430.

Included in

  • CCSv6.0.1 + CCSv6.0 ( P2 package)
  • IAR EW430 v6.10.2

New Device Support

  • MSP430FG6626
  • MSP430FR4133 Family
  • MSP430FR6989 Family

New Features

  • User code erase via JTAG mailbox on MSP430FR4133 family
  • MSP-FET backchannel UART support


  • Reduced calibration time when setting VCC

Bug Fixes

  • Fixed: eZ-FET update fails in Ubuntu 64bit due to modemmanager blocking the port. When installing CCS, debugger ports will be blacklisted for modemmanager
  • Selecting invalid JTAG protocol on eZ-FET now returns error instead of silently using SBW
  • Prevent MSP-FET from detecting over current when connecting to a target driving the JTAG lines active low
  • Added fix to prevent unintended execution of memory content as code during debug
  • Restoring software breakpoints after external code download on MSP430L092
  • Fixed typo in device name for MSP430FR5857
  • Removed non-existent timers from clock control settings
  • Saving to Intel format did not pad CRC values lower than 0x10 with leading 0

Known Issues

  • On devices with FLL, clock control does not allow to keep clocks running, while the device is halted and the clock is sourced by the FLL
  • V1.3 of UIF does not work in SBW2 mode with 2.2nf cap on reset line
  • eZ-FET UART might lose bytes with 115k baud (no handshake enabled) and DMA as data loopback on target device
  • MSP-FET EEM access to F149 and L092 devices is only possible with JTAG speed slow
  • MSP430FR4133 might not work reliably under debug control when XT1 is used as clock source, because of overwritten XT1 drive strength register
  • MSP430FR4133 might not work reliably under debug control when BSL unlock is executed via DLL/IDE, because of overwritten DCO CSCTL1 register

Older Releases

  • 2_04_007_001
  • 2_04_008_002
  • 2_04_009_001
  • 3_02_001_009
  • 3_02_003_015
  • 3_02_004_005
  • 3_02_005_004
  • 3_03_000_006
  • 3_03_001_003
  • 3_03_001_004
  • 3_04_000_020

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    MSP430_DLL Product Downloads
    Title Description Size
    Unlocked MSP430 DLL 27432K
    No Login MD5 Checksums 4K

    Related Links

    Tue Apr 29 04:11:25 CDT 2014