Introduction

This module contains APIs to program and use the GPADC module.

Files
file	gpadc/v0/gpadc.h
	This file contains the prototypes of the APIs present in the device abstraction layer file of GPADC.

Data Structures
struct	GPADC_ChannelConfigType
	GPADC Config Type data structure for the mode, trigger source and channel configuration for all the available external sources <0-8> More...

struct	GPADC_ConfigType
	GPADC Config Type data structure for the mode, trigger source and channel configuration for all the available external sources <0-8> More...

union	GPADC_ParamInfoType
	Configuration Parameters for GPADC in IFM mode ParamValue : Value to be programmed in one hot reg CollectSamples : Number of samples to collect @625KHz SkipSamples : Number of samples to skip @10MHz Time = Mantissa[3:0] * 2^(Exponent[6:4]) / 10M. More...

union	GPADC_channelsGroupSelectType
	Available <0-8> external sources/channels could be selected by using bitmap of 9 bits in LSB. Ex: 0x01F is the bitmap for conversion of <0-4> external sources. More...

struct	GPADC_DriverChannelConfigType
	GPADC Driver Channel configuration. More...

struct	GPADC_DriverObjectType
	GPADC Driver Object configuration. More...

struct	GPADC_EfuseTempTrimType
	The Temperature sensor trim parameters structure. More...

struct	GPADC_TempSensTrimType
	The Temperature sensor trim parameters structure. More...

struct	GPADC_TempSensMuxType
	Temperature sensors mux values. More...

struct	GPADC_TempSensValueType
	The Temperature sensor values structure. More...

struct	MSS_GPADC_RST_CTRL_REG
	GPADC Reset Control register. More...

struct	MSS_GPADC_CLK_DIV_VAL_REG
	GPADC Clock Divider Value register. More...

struct	MSS_GPADC_CLK_GATE_REG
	GPADC Clock Gate register. More...

struct	MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_REG
	Analog Mux Control Registers. More...

struct	MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_REG
	Analog Refsys spare Registers. More...

struct	U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG
	RCM Analog register TW Control Registers. More...

struct	GPADCREG_REG0
	Register Offset 0x000. More...

struct	GPADCREG_REG1
	Register1 Offset 0x004. More...

struct	GPADCREG_REG2
	Register2 Offset 0x008. More...

union	U_GPADCREG_REG3
	Register3 Offset 0x00C. More...

union	U_GPADCREG_REG4
	Register4 Offset 0x010. More...

struct	GPADCREG_REG5
	Register5 Offset 0x014. More...

struct	GPADCREG_REG6
	Register6 Offset 0x018. More...

struct	GPADCREG_REG7
	Register7 Offset 0x01C. More...

struct	GPADCREG_REG8
	Register8 Offset 0x020. More...

struct	GPADCREG_REG9
	Register9 Offset 0x024. More...

struct	GPADCREG_REG10
	Register10 Offset 0x028. More...

struct	GPADCREG_REG11
	Register11 Offset 0x02C. More...

struct	GPADCREG_REG12
	Register12 Offset 0x030. More...

struct	GPADCREG_REG13
	Register13 Offset 0x034. More...

struct	GPADCREG_REG14
	Register14 Offset 0x038. More...

struct	GPADCREG_REG15
	Register15 Offset 0x03C. More...

struct	GPADCREG_REG16
	Register16 Offset 0x040. More...

struct	GPADCREG_REG17
	Register17 Offset 0x044. More...

struct	GPADCREG_REG18
	Register19 Offset 0x048. More...

struct	GPADCREG_REG19
	Register20 Offset 0x04C. More...

struct	GPADCREG_REG20
	Register21 Offset 0x050. More...

struct	GPADCREG_REG21
	Register22 Offset 0x054. More...

struct	GPADCREG_REG22
	Register22 Offset 0x058. More...

struct	T_GPADC_REGS
	MSS_GPADC_REG_REGS. More...

struct	MSS_CTRL_MSS_GPADC_MEM_INIT_REG
	GPADC Memory initialize registers. More...

struct	GPADC_CfgAndParamValuesType
	Configuration Parameters for GPADC LUT in IFM mode 32 bits: ConfigValue 32 bits: ParamInfo. More...

struct	GPADC_ResultType
	GPADC returning min, avg, max and sum. More...

Functions
void	GPADC_init (void)
	This function initializes the GPADC module. More...

void	GPADC_deinit (void)
	This function de-initializes the GPADC module. More...

int32_t	GPADC_open (GPADC_ConfigType *CfgPtr)
	Initializes the GPADC Driver with the channels configuration. More...

int32_t	GPADC_close (void)
	This function closes the GPADC module. More...

GPADC_ConvResultType	GPADC_startGroupConversion (GPADC_channelsGroupSelectType channels, uint8_t numChannels)
	Starts and triggers the multi channel ADC conversion. More...

GPADC_ConvResultType	GPADC_startSingleChannelConversion (GPADC_MeasExtSrcType channelID, uint16_t *gpadcValue)
	Starts and triggers the single channel conversion. Pass the channelID and result address to the driver and the result will be stored in the address passed. More...

int32_t	GPADC_stopConversion (void)
	Stops the GPADC conversion. More...

int32_t	GPADC_setupResultBuffer (uint16_t *ResBufferPtr)
	Initializes GPADC driver with the group specific result buffer start address where the conversion results will be stored. More...

int32_t	GPADC_readResultBuffer (uint16_t *ResBufferPtr)
	The function is used to read the result buffer from the GPADC Driver. More...

GPADC_StatusType	GPADC_getStatus (void)
	Gets the status of GPADC Driver HW unit. More...

int32_t	GPADC_readTemperature (uint8_t numAverages, uint8_t numChannels, GPADC_TempSensValueType *tempValuesPtr)
	Read the temperature sensor value. More...

void	GPADC_initTempMeasurement (void)
	Initialize GPADC efuse temperature parameters. More...

Enumerations
enum	GPADC_CtmTrigSrcType { GPADC_TRIG_SRC_GPIO_0 = 0, GPADC_TRIG_SRC_GPIO_1, GPADC_TRIG_SRC_GPIO_2, GPADC_TRIG_SRC_GPIO_3, GPADC_TRIG_SRC_RSS_CSI2A_EOL_INT, GPADC_TRIG_SRC_RSS_CSI2A_SOF_INT0, GPADC_TRIG_SRC_RSS_CSI2A_SOF_INT1, GPADC_TRIG_SRC_RSS_CSI2A_SOF_INT, GPADC_TRIG_SRC_RSS_CSI2B_SOF_INT, GPADC_TRIG_SRC_HW_Sync_FE1, GPADC_TRIG_SRC_HW_Sync_FE2, GPADC_TRIG_SRC_DSS_RTIA_1, GPADC_TRIG_SRC_DSS_RTIB_1, GPADC_TRIG_SRC_MSS_RTIA_INT1, GPADC_TRIG_SRC_MSS_RTIB_INT1, GPADC_TRIG_SRC_MMR_Based_SW_Trigger }
	Enumeration which describes the trigger sources for GPADC CTM mode conversion. More...

enum	GPADC_ChannelConvModeType { GPADC_ONESHOT_CONV_MODE = 0, GPADC_CONTINUOUS_CONV_MODE }
	Enumeration which lists the conversion modes supported for AM273x GPADC conversion. More...

enum	GPADC_TriggerSourceType { GPADC_TRIGG_SRC_SW = 0, GPADC_TRIGG_SRC_HW }
	Enumeration which describes the trigger sources for GPADC CTM mode conversion. More...

enum	GPADC_MeasExtSrcType { GPADC_MEAS_EXT_CH1 = 0, GPADC_MEAS_EXT_CH2, GPADC_MEAS_EXT_CH3, GPADC_MEAS_EXT_CH4, GPADC_MEAS_EXT_CH5, GPADC_MEAS_EXT_CH6, GPADC_MEAS_EXT_CH7, GPADC_MEAS_EXT_CH8, GPADC_MEAS_EXT_CH9, MAX_GPADC_MEAS_SOURCES }
	Enumeration which describes the external sources available for GPADC conversion. More...

enum	GPADC_ConvResultType { GPADC_CONV_ERROR = 0, GPADC_CONV_DONE, GPADC_CONV_CHANNEL_CONFIG_MISSING }
	Enumeration which describes the error types of GPADC conversion. More...

enum	GPADC_StatusType { GPADC_IDLE, GPADC_BUSY, GPADC_COMPLETED }
	Current status of the conversion of the requested GPADC HW unit. More...

enum	GPADC_TempSensorSrcType { GPADC_DIG_DSP_TEMP_SENSOR = 0, GPADC_DIG_HWA_TEMP_SENSOR, GPADC_DIG_HSM_TEMP_SENSOR, MAX_GPADC_TEMP_SENSORS }
	Enumeration which describes the temperature sensors available for GPADC measurement. More...

Macros
#define	MAX_CTM_GPADC_PARAMS (1U)
	Number of measurement parameters for GPADC in CTM mode More...

#define	GPADC_TIMEOUT_MAX (200000U)
	GPADC TIMEOUT Max Number of Sample collect : 256 Max Time for 256 samples collection : 256 * 16/10MHz = 409.6us Add 10 % margin : 450us Add 550us for skip samples Total timeout: 1ms Timout in terms of pmu count = 1ms/5ns = 200,000. More...

#define	EFUSE_TRIM_TEMPERATURE_CONST 523
	Efuse Trime Constant Temperature. More...

#define	EFUSE_TRIM_TEMPERATURE_DIV_CONST 10
	Efuse Trime Constant Temperature Divider. More...

#define	ZERO_PT_TRIM_FIXED_TRIM_TEMP 110
	Zero point TRIM Fixed Temperature. More...

#define	ZERO_PT_TRIM_FIXED_DIG_TEMP_SENSOR_TRIM_30C 305U
	Zero point TRIM Fixed Digital Temperature. More...

#define	ZERO 0
	Zero Value. More...

#define	ZERO_PT_TRIM_FIXED_SLOPE -1.05
	Zero point TRIM Fixed Slope. More...

#define	ONE_PT_TRIM_FIXED_SLOPE -1.05
	One point TRIM Fixed Slope. More...

#define	EFUSE1_ROW_14_FUSEROM_VER_START_BIT 20U
	Efuse Version Start Bit. More...

#define	EFUSE1_ROW_14_FUSEROM_VER_STOP_BIT 24U
	Efuse Version Stop Bit. More...

#define	EFUSE1_ROW_36_TRIM_TEMPERATURE_30C_START_BIT 15U
	Efuse Trim Temperature 30C Start Bit. More...

#define	EFUSE1_ROW_36_TRIM_TEMPERATURE_30C_STOP_BIT 25U
	Efuse Trim Temperature 30C Stop Bit. More...

#define	EFUSE1_ROW_33_TRIM_TEMPERATURE_125C_START_BIT 0U
	Efuse Trim Temperature 125C Start Bit. More...

#define	EFUSE1_ROW_33_TRIM_TEMPERATURE_125C_STOP_BIT 10U
	Efuse Trim Temperature 125C Stop Bit. More...

#define	EFUSE1_ROW_37_DIG_DSP_TEMP_SENSOR_TRIM0_30C_START_BIT 5U
	Efuse Digital DSP Temperature 30C Sensor Start Bit. More...

#define	EFUSE1_ROW_37_DIG_DSP_TEMP_SENSOR_TRIM0_30C_STOP_BIT 14U
	Efuse Digital DSP Temperature 30C Sensor Stop Bit. More...

#define	EFUSE1_ROW_37_DIG_HWA_TEMP_SENSOR_TRIM1_30C_START_BIT 15U
	Efuse Digital HWA Temperature 30C Sensor Start Bit. More...

#define	EFUSE1_ROW_37_DIG_HWA_TEMP_SENSOR_TRIM1_30C_STOP_BIT 24U
	Efuse Digital HWA Temperature 30C Sensor Stop Bit. More...

#define	EFUSE1_ROW_38_DIG_HSM_TEMP_SENSOR_TRIM2_30C_START_BIT 0U
	Efuse Digital HSM Temperature 30C Sensor Start Bit. More...

#define	EFUSE1_ROW_38_DIG_HSM_TEMP_SENSOR_TRIM2_30C_STOP_BIT 9U
	Efuse Digital HSM Temperature 30C Sensor Stop Bit. More...

#define	EFUSE1_ROW_34_DIG_DSP_TEMP_SENSOR_TRIM0_125C_START_BIT 5U
	Efuse Digital DSP Temperature 125C Sensor Start Bit. More...

#define	EFUSE1_ROW_34_DIG_DSP_TEMP_SENSOR_TRIM0_125C_STOP_BIT 14U
	Efuse Digital DSP Temperature 125C Sensor Stop Bit. More...

#define	EFUSE1_ROW_34_DIG_HWA_TEMP_SENSOR_TRIM1_125C_START_BIT 15U
	Efuse Digital HWA Temperature 125C Sensor Start Bit. More...

#define	EFUSE1_ROW_34_DIG_HWA_TEMP_SENSOR_TRIM1_125C_STOP_BIT 24U
	Efuse Digital HWA Temperature 125C Sensor Stop Bit. More...

#define	EFUSE1_ROW_35_DIG_HSM_TEMP_SENSOR_TRIM2_125C_START_BIT 0U
	Efuse Digital HSM Temperature 125C Sensor Start Bit. More...

#define	EFUSE1_ROW_35_DIG_HSM_TEMP_SENSOR_TRIM2_125C_STOP_BIT 9U
	Efuse Digital HSM Temperature 125C Sensor Stop Bit. More...

#define	GPADC_REGS_PTR ((T_GPADC_REGS*)CSL_MSS_GPADC_REG_U_BASE)
	GPADC Register Base Address. More...

#define	GPADCPKTRAM_REGS_PTR ((T_GPADCPKTRAM_REGS*)CSL_MSS_GPADC_PKT_RAM_U_BASE)
	GPADCPKTRAM Register Base Address. More...

#define	GPADCOUT_RAM_PTR ((T_GPADCOUT_RAM*)CSL_MSS_GPADC_DATA_RAM_U_BASE)
	GPADCPKTRAM Data RAM Base Address. More...

#define	MSS_GPADC_RST_CTRL_ADDR (CSL_MSS_RCM_U_BASE + CSL_MSS_RCM_MSS_GPADC_RST_CTRL)
	GPADC Reset Control Address. More...

#define	MSS_GPADC_RST_CTRL_PTR ((MSS_GPADC_RST_CTRL_REG*)MSS_GPADC_RST_CTRL_ADDR)
	GPADC Reset Control Pointer. More...

#define	MSS_GPADC_CLK_DIV_VAL_ADDR (CSL_MSS_RCM_U_BASE + CSL_MSS_RCM_MSS_GPADC_CLK_DIV_VAL)
	GPADC Clock Divider value Address. More...

#define	MSS_GPADC_CLK_DIV_VAL_PTR ((MSS_GPADC_CLK_DIV_VAL_REG*)MSS_GPADC_CLK_DIV_VAL_ADDR)
	GPADC Clock Divider value pointer. More...

#define	MSS_GPADC_CLK_GATE_ADDR (CSL_MSS_RCM_U_BASE + CSL_MSS_RCM_MSS_GPADC_CLK_GATE)
	GPADC Clock Gate Address. More...

#define	MSS_GPADC_CLK_GATE_PTR ((MSS_GPADC_CLK_GATE_REG*)MSS_GPADC_CLK_GATE_ADDR)
	GPADC Clock Gate Pointer. More...

#define	MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_ADDR (CSL_MSS_TOPRCM_U_BASE + CSL_MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV)
	RCM TW Analog TMUX Contol Address. More...

#define	MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_PTR ((MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_REG*)MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_ADDR)
	RCM TW Analog TMUX Contol Poniter. More...

#define	MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_ADDR (CSL_MSS_TOPRCM_U_BASE + CSL_MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV)
	RCM Analog Refsys Spare register Address. More...

#define	MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_PTR ((MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_REG*)MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_ADDR)
	RCM Analog Refsys Spare register Pointer. More...

#define	MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_ADDR (CSL_MSS_TOPRCM_U_BASE + CSL_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV)
	RCM Analog TW Control register Address. More...

#define	MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_PTR ((U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG*)MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_ADDR)
	RCM Analog TW Control register pointer. More...

#define	MSS_CTRL_MSS_GPADC_MEM_INIT_ADDR (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_MSS_GPADC_MEM_INIT)
	GPADC Memomory Init Address. More...

#define	MSS_CTRL_MSS_GPADC_MEM_INIT_PTR ((MSS_CTRL_MSS_GPADC_MEM_INIT_REG*)MSS_CTRL_MSS_GPADC_MEM_INIT_ADDR)
	GPADC Memomory Init poniter. More...

#define	REG_STRUCT_SWRITE(w_hwRegStruct, w_regVal, w_regWrSts)
	Register Structure member write and compare macro. More...

#define	REG32_SCOMPARE(w_hwVal, w_swVal, w_regWrSts)
	32 bit register compare macro More...

#define	REG_STRUCT_SCLEAR(w_hwRegStruct, w_regVal, w_regWrSts)
	Register Structure member CLEAR and compare macro. More...

GPADC Macros

#define	GPADC_DISABLE (0U)
	Disable GPADC. More...

#define	GPADC_ENABLE (1U)
	Enable GPADC. More...

#define	GPADC_ASSERT_RESET (1U)
	Reset GPADC. More...

#define	GPADC_DEASSERT_RESET (0U)
	Release GPADC Reset. More...

#define	GPADC_FSM_ASSERT_RESET (0x7U)
	Reset GPADC for digital FSM. More...

#define	GPADC_FSM_DEASSERT_RESET (0U)
	Release Reset GPADC for digital FSM. More...

GPADC Modes

#define	GPADC_MODE_DISABLE (0U)
	GPADC Disable mode. More...

#define	GPADC_MODE_IFM (1U)
	GPADC IFM Operation mode. More...

#define	GPADC_MODE_CTM (2U)
	GPADC CTM Operation mode. More...

Instruction RAM Index
MON CTM INSTRUCTION RAM Index
#define	GPADC_MON_INSTR_RAM_ST_IND (224U)
	GPADC RAM Instruction Index. More...

#define	GPADC_MAX_MON_INSTR_RAM (32U)
	GPADC MAX RAM Instruction. More...

Macro Definition Documentation

◆ GPADC_DISABLE

#define GPADC_DISABLE (0U)

Disable GPADC.

◆ GPADC_ENABLE

#define GPADC_ENABLE (1U)

Enable GPADC.

◆ GPADC_ASSERT_RESET

#define GPADC_ASSERT_RESET (1U)

Reset GPADC.

◆ GPADC_DEASSERT_RESET

#define GPADC_DEASSERT_RESET (0U)

Release GPADC Reset.

◆ GPADC_FSM_ASSERT_RESET

#define GPADC_FSM_ASSERT_RESET (0x7U)

Reset GPADC for digital FSM.

◆ GPADC_FSM_DEASSERT_RESET

#define GPADC_FSM_DEASSERT_RESET (0U)

Release Reset GPADC for digital FSM.

◆ GPADC_MODE_DISABLE

#define GPADC_MODE_DISABLE (0U)

GPADC Disable mode.

◆ GPADC_MODE_IFM

#define GPADC_MODE_IFM (1U)

GPADC IFM Operation mode.

◆ GPADC_MODE_CTM

#define GPADC_MODE_CTM (2U)

GPADC CTM Operation mode.

◆ GPADC_MON_INSTR_RAM_ST_IND

#define GPADC_MON_INSTR_RAM_ST_IND (224U)

GPADC RAM Instruction Index.

◆ GPADC_MAX_MON_INSTR_RAM

#define GPADC_MAX_MON_INSTR_RAM (32U)

GPADC MAX RAM Instruction.

◆ MAX_CTM_GPADC_PARAMS

#define MAX_CTM_GPADC_PARAMS (1U)

Number of measurement parameters for GPADC in CTM mode

◆ GPADC_TIMEOUT_MAX

#define GPADC_TIMEOUT_MAX (200000U)

GPADC TIMEOUT Max Number of Sample collect : 256 Max Time for 256 samples collection : 256 * 16/10MHz = 409.6us Add 10 % margin : 450us Add 550us for skip samples Total timeout: 1ms Timout in terms of pmu count = 1ms/5ns = 200,000.

◆ EFUSE_TRIM_TEMPERATURE_CONST

#define EFUSE_TRIM_TEMPERATURE_CONST 523

Efuse Trime Constant Temperature.

◆ EFUSE_TRIM_TEMPERATURE_DIV_CONST

#define EFUSE_TRIM_TEMPERATURE_DIV_CONST 10

Efuse Trime Constant Temperature Divider.

◆ ZERO_PT_TRIM_FIXED_TRIM_TEMP

#define ZERO_PT_TRIM_FIXED_TRIM_TEMP 110

Zero point TRIM Fixed Temperature.

◆ ZERO_PT_TRIM_FIXED_DIG_TEMP_SENSOR_TRIM_30C

#define ZERO_PT_TRIM_FIXED_DIG_TEMP_SENSOR_TRIM_30C 305U

Zero point TRIM Fixed Digital Temperature.

◆ ZERO

#define ZERO 0

Zero Value.

◆ ZERO_PT_TRIM_FIXED_SLOPE

#define ZERO_PT_TRIM_FIXED_SLOPE -1.05

Zero point TRIM Fixed Slope.

◆ ONE_PT_TRIM_FIXED_SLOPE

#define ONE_PT_TRIM_FIXED_SLOPE -1.05

One point TRIM Fixed Slope.

◆ EFUSE1_ROW_14_FUSEROM_VER_START_BIT

#define EFUSE1_ROW_14_FUSEROM_VER_START_BIT 20U

Efuse Version Start Bit.

◆ EFUSE1_ROW_14_FUSEROM_VER_STOP_BIT

#define EFUSE1_ROW_14_FUSEROM_VER_STOP_BIT 24U

Efuse Version Stop Bit.

◆ EFUSE1_ROW_36_TRIM_TEMPERATURE_30C_START_BIT

#define EFUSE1_ROW_36_TRIM_TEMPERATURE_30C_START_BIT 15U

Efuse Trim Temperature 30C Start Bit.

◆ EFUSE1_ROW_36_TRIM_TEMPERATURE_30C_STOP_BIT

#define EFUSE1_ROW_36_TRIM_TEMPERATURE_30C_STOP_BIT 25U

Efuse Trim Temperature 30C Stop Bit.

◆ EFUSE1_ROW_33_TRIM_TEMPERATURE_125C_START_BIT

#define EFUSE1_ROW_33_TRIM_TEMPERATURE_125C_START_BIT 0U

Efuse Trim Temperature 125C Start Bit.

◆ EFUSE1_ROW_33_TRIM_TEMPERATURE_125C_STOP_BIT

#define EFUSE1_ROW_33_TRIM_TEMPERATURE_125C_STOP_BIT 10U

Efuse Trim Temperature 125C Stop Bit.

◆ EFUSE1_ROW_37_DIG_DSP_TEMP_SENSOR_TRIM0_30C_START_BIT

#define EFUSE1_ROW_37_DIG_DSP_TEMP_SENSOR_TRIM0_30C_START_BIT 5U

Efuse Digital DSP Temperature 30C Sensor Start Bit.

◆ EFUSE1_ROW_37_DIG_DSP_TEMP_SENSOR_TRIM0_30C_STOP_BIT

#define EFUSE1_ROW_37_DIG_DSP_TEMP_SENSOR_TRIM0_30C_STOP_BIT 14U

Efuse Digital DSP Temperature 30C Sensor Stop Bit.

◆ EFUSE1_ROW_37_DIG_HWA_TEMP_SENSOR_TRIM1_30C_START_BIT

#define EFUSE1_ROW_37_DIG_HWA_TEMP_SENSOR_TRIM1_30C_START_BIT 15U

Efuse Digital HWA Temperature 30C Sensor Start Bit.

◆ EFUSE1_ROW_37_DIG_HWA_TEMP_SENSOR_TRIM1_30C_STOP_BIT

#define EFUSE1_ROW_37_DIG_HWA_TEMP_SENSOR_TRIM1_30C_STOP_BIT 24U

Efuse Digital HWA Temperature 30C Sensor Stop Bit.

◆ EFUSE1_ROW_38_DIG_HSM_TEMP_SENSOR_TRIM2_30C_START_BIT

#define EFUSE1_ROW_38_DIG_HSM_TEMP_SENSOR_TRIM2_30C_START_BIT 0U

Efuse Digital HSM Temperature 30C Sensor Start Bit.

◆ EFUSE1_ROW_38_DIG_HSM_TEMP_SENSOR_TRIM2_30C_STOP_BIT

#define EFUSE1_ROW_38_DIG_HSM_TEMP_SENSOR_TRIM2_30C_STOP_BIT 9U

Efuse Digital HSM Temperature 30C Sensor Stop Bit.

◆ EFUSE1_ROW_34_DIG_DSP_TEMP_SENSOR_TRIM0_125C_START_BIT

#define EFUSE1_ROW_34_DIG_DSP_TEMP_SENSOR_TRIM0_125C_START_BIT 5U

Efuse Digital DSP Temperature 125C Sensor Start Bit.

◆ EFUSE1_ROW_34_DIG_DSP_TEMP_SENSOR_TRIM0_125C_STOP_BIT

#define EFUSE1_ROW_34_DIG_DSP_TEMP_SENSOR_TRIM0_125C_STOP_BIT 14U

Efuse Digital DSP Temperature 125C Sensor Stop Bit.

◆ EFUSE1_ROW_34_DIG_HWA_TEMP_SENSOR_TRIM1_125C_START_BIT

#define EFUSE1_ROW_34_DIG_HWA_TEMP_SENSOR_TRIM1_125C_START_BIT 15U

Efuse Digital HWA Temperature 125C Sensor Start Bit.

◆ EFUSE1_ROW_34_DIG_HWA_TEMP_SENSOR_TRIM1_125C_STOP_BIT

#define EFUSE1_ROW_34_DIG_HWA_TEMP_SENSOR_TRIM1_125C_STOP_BIT 24U

Efuse Digital HWA Temperature 125C Sensor Stop Bit.

◆ EFUSE1_ROW_35_DIG_HSM_TEMP_SENSOR_TRIM2_125C_START_BIT

#define EFUSE1_ROW_35_DIG_HSM_TEMP_SENSOR_TRIM2_125C_START_BIT 0U

Efuse Digital HSM Temperature 125C Sensor Start Bit.

◆ EFUSE1_ROW_35_DIG_HSM_TEMP_SENSOR_TRIM2_125C_STOP_BIT

#define EFUSE1_ROW_35_DIG_HSM_TEMP_SENSOR_TRIM2_125C_STOP_BIT 9U

Efuse Digital HSM Temperature 125C Sensor Stop Bit.

◆ GPADC_REGS_PTR

#define GPADC_REGS_PTR ((T_GPADC_REGS*)CSL_MSS_GPADC_REG_U_BASE)

GPADC Register Base Address.

◆ GPADCPKTRAM_REGS_PTR

#define GPADCPKTRAM_REGS_PTR ((T_GPADCPKTRAM_REGS*)CSL_MSS_GPADC_PKT_RAM_U_BASE)

GPADCPKTRAM Register Base Address.

◆ GPADCOUT_RAM_PTR

#define GPADCOUT_RAM_PTR ((T_GPADCOUT_RAM*)CSL_MSS_GPADC_DATA_RAM_U_BASE)

GPADCPKTRAM Data RAM Base Address.

◆ MSS_GPADC_RST_CTRL_ADDR

#define MSS_GPADC_RST_CTRL_ADDR (CSL_MSS_RCM_U_BASE + CSL_MSS_RCM_MSS_GPADC_RST_CTRL)

GPADC Reset Control Address.

◆ MSS_GPADC_RST_CTRL_PTR

#define MSS_GPADC_RST_CTRL_PTR ((MSS_GPADC_RST_CTRL_REG*)MSS_GPADC_RST_CTRL_ADDR)

GPADC Reset Control Pointer.

◆ MSS_GPADC_CLK_DIV_VAL_ADDR

#define MSS_GPADC_CLK_DIV_VAL_ADDR (CSL_MSS_RCM_U_BASE + CSL_MSS_RCM_MSS_GPADC_CLK_DIV_VAL)

GPADC Clock Divider value Address.

◆ MSS_GPADC_CLK_DIV_VAL_PTR

#define MSS_GPADC_CLK_DIV_VAL_PTR ((MSS_GPADC_CLK_DIV_VAL_REG*)MSS_GPADC_CLK_DIV_VAL_ADDR)

GPADC Clock Divider value pointer.

◆ MSS_GPADC_CLK_GATE_ADDR

#define MSS_GPADC_CLK_GATE_ADDR (CSL_MSS_RCM_U_BASE + CSL_MSS_RCM_MSS_GPADC_CLK_GATE)

GPADC Clock Gate Address.

◆ MSS_GPADC_CLK_GATE_PTR

#define MSS_GPADC_CLK_GATE_PTR ((MSS_GPADC_CLK_GATE_REG*)MSS_GPADC_CLK_GATE_ADDR)

GPADC Clock Gate Pointer.

◆ MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_ADDR

#define MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_ADDR (CSL_MSS_TOPRCM_U_BASE + CSL_MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV)

RCM TW Analog TMUX Contol Address.

◆ MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_PTR

#define MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_PTR ((MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_REG*)MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_ADDR)

RCM TW Analog TMUX Contol Poniter.

◆ MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_ADDR

#define MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_ADDR (CSL_MSS_TOPRCM_U_BASE + CSL_MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV)

RCM Analog Refsys Spare register Address.

◆ MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_PTR

#define MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_PTR ((MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_REG*)MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_ADDR)

RCM Analog Refsys Spare register Pointer.

◆ MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_ADDR

#define MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_ADDR (CSL_MSS_TOPRCM_U_BASE + CSL_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV)

RCM Analog TW Control register Address.

◆ MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_PTR

#define MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_PTR ((U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG*)MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_ADDR)

RCM Analog TW Control register pointer.

◆ MSS_CTRL_MSS_GPADC_MEM_INIT_ADDR

#define MSS_CTRL_MSS_GPADC_MEM_INIT_ADDR (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_MSS_GPADC_MEM_INIT)

GPADC Memomory Init Address.

◆ MSS_CTRL_MSS_GPADC_MEM_INIT_PTR

#define MSS_CTRL_MSS_GPADC_MEM_INIT_PTR ((MSS_CTRL_MSS_GPADC_MEM_INIT_REG*)MSS_CTRL_MSS_GPADC_MEM_INIT_ADDR)

GPADC Memomory Init poniter.

◆ REG_STRUCT_SWRITE

#define REG_STRUCT_SWRITE	(	w_hwRegStruct,
		w_regVal,
		w_regWrSts
	)

Value:

                do { (w_hwRegStruct) = (w_regVal); \
                     REG32_SCOMPARE((w_hwRegStruct), (w_regVal), (w_regWrSts)); \
                   } while (0)

Register Structure member write and compare macro.

◆ REG32_SCOMPARE

#define REG32_SCOMPARE	(	w_hwVal,
		w_swVal,
		w_regWrSts
	)

Value:

                do { \
                     (w_regWrSts) |= (((uint32_t)(w_swVal)) ^ ((uint32_t)(w_hwVal))); \
                   } while (0)

32 bit register compare macro

◆ REG_STRUCT_SCLEAR

#define REG_STRUCT_SCLEAR	(	w_hwRegStruct,
		w_regVal,
		w_regWrSts
	)

Value:

                do { (w_hwRegStruct) = (w_regVal); \
                     (w_regWrSts) |= ((((uint32_t)(w_hwRegStruct)) & (uint32_t)(w_regVal))); \
                   } while (0)

Register Structure member CLEAR and compare macro.

Enumeration Type Documentation

◆ GPADC_CtmTrigSrcType

enum GPADC_CtmTrigSrcType

Enumeration which describes the trigger sources for GPADC CTM mode conversion.

Note: Only GPADC_TRIGG_SRC_SW is supported in the AM273x GPADC Driver. GPADC_TRIG_SRC_MMR_Based_SW_Trigger will be default trigger if CTM mode is configured

Enumerator
GPADC_TRIG_SRC_GPIO_0	0x00 - GPIO_0
GPADC_TRIG_SRC_GPIO_1	0x01 - GPIO_1
GPADC_TRIG_SRC_GPIO_2	0x02 - GPIO_2
GPADC_TRIG_SRC_GPIO_3	0x03 - GPIO_3
GPADC_TRIG_SRC_RSS_CSI2A_EOL_INT	0x04 - RSS_CSI2A_EOL_INT
GPADC_TRIG_SRC_RSS_CSI2A_SOF_INT0	0x05 - RSS_CSI2A_SOF_INT0
GPADC_TRIG_SRC_RSS_CSI2A_SOF_INT1	0x06 - RSS_CSI2A_SOF_INT1
GPADC_TRIG_SRC_RSS_CSI2A_SOF_INT	0x07 - RSS_CSI2A_SOF_INT
GPADC_TRIG_SRC_RSS_CSI2B_SOF_INT	0x08 - RSS_CSI2B_SOF_INT
GPADC_TRIG_SRC_HW_Sync_FE1	0x09 - HW_Sync_FE1
GPADC_TRIG_SRC_HW_Sync_FE2	0x0A - HW_Sync_FE2
GPADC_TRIG_SRC_DSS_RTIA_1	0x0B - DSS_RTIA_1
GPADC_TRIG_SRC_DSS_RTIB_1	0x0C - DSS_RTIB_1
GPADC_TRIG_SRC_MSS_RTIA_INT1	0x0D - MSS_RTIA_INT1
GPADC_TRIG_SRC_MSS_RTIB_INT1	0x0E - MSS_RTIB_INT1
GPADC_TRIG_SRC_MMR_Based_SW_Trigger	0x0F - MMR_Based_SW_Trigger

◆ GPADC_ChannelConvModeType

enum GPADC_ChannelConvModeType

Enumeration which lists the conversion modes supported for AM273x GPADC conversion.

Note: Only GPADC_ONESHOT_CONV_MODE is supported in the AM273x GPADC Driver.

Enumerator
GPADC_ONESHOT_CONV_MODE	0x00 - IFM - Inter Frame Monitoring/One Shot Conversion Mode
GPADC_CONTINUOUS_CONV_MODE	0x01 - CTM - Continuous Time Monitoring/ Continuous conversion Mode

◆ GPADC_TriggerSourceType

enum GPADC_TriggerSourceType

Enumeration which describes the trigger sources for GPADC CTM mode conversion.

Note: Only GPADC_TRIGG_SRC_SW is supported in the AM273x GPADC Driver.

Enumerator
GPADC_TRIGG_SRC_SW	Conversion is triggered by a software API call.
GPADC_TRIGG_SRC_HW	Conversion is triggered by a hardware event.

◆ GPADC_MeasExtSrcType

enum GPADC_MeasExtSrcType

Enumeration which describes the external sources available for GPADC conversion.

Enumerator
GPADC_MEAS_EXT_CH1	0x0 - Channel 1
GPADC_MEAS_EXT_CH2	0x1 - Channel 2
GPADC_MEAS_EXT_CH3	0x2 - Channel 3
GPADC_MEAS_EXT_CH4	0x3 - Channel 4
GPADC_MEAS_EXT_CH5	0x4 - Channel 5
GPADC_MEAS_EXT_CH6	0x5 - Channel 6
GPADC_MEAS_EXT_CH7	0x6 - Channel 7
GPADC_MEAS_EXT_CH8	0x7 - Channel 8
GPADC_MEAS_EXT_CH9	0x8 - Channel 9
MAX_GPADC_MEAS_SOURCES	0x9 - MAX_CHANNELS

◆ GPADC_ConvResultType

enum GPADC_ConvResultType

Enumeration which describes the error types of GPADC conversion.

Enumerator
GPADC_CONV_ERROR	GPADC conversion error.
GPADC_CONV_DONE	GPADC conversion done.
GPADC_CONV_CHANNEL_CONFIG_MISSING	GPADC requested channel through the channel bitmap or index is not configured during the initialization.

◆ GPADC_StatusType

enum GPADC_StatusType

Current status of the conversion of the requested GPADC HW unit.

Enumerator
GPADC_IDLE	The conversion of the specified group has not been started. No result is available.
GPADC_BUSY	The conversion of the specified group has been started and is still going on. So far no result is available.
GPADC_COMPLETED	A conversion round of the specified group has been finished. A result is available for all specified channels of the group.

◆ GPADC_TempSensorSrcType

enum GPADC_TempSensorSrcType

Enumeration which describes the temperature sensors available for GPADC measurement.

Enumerator
GPADC_DIG_DSP_TEMP_SENSOR	0x0 - DIG_DSP_TEMP_SENSOR
GPADC_DIG_HWA_TEMP_SENSOR	0x1 - DIG_HWA_TEMP_SENSOR
GPADC_DIG_HSM_TEMP_SENSOR	0x2 - DIG_HSM_TEMP_SENSOR
MAX_GPADC_TEMP_SENSORS	0x3 - MAX_TEMP_SENSORS

Function Documentation

◆ GPADC_init()

void GPADC_init ( void )

This function initializes the GPADC module.

◆ GPADC_deinit()

void GPADC_deinit ( void )

This function de-initializes the GPADC module.

◆ GPADC_open()

int32_t GPADC_open ( GPADC_ConfigType * CfgPtr )

Initializes the GPADC Driver with the channels configuration.

Parameters

[in] CfgPtr Pointer to the GPADC configuration

◆ GPADC_close()

int32_t GPADC_close ( void )

This function closes the GPADC module.

◆ GPADC_startGroupConversion()

GPADC_ConvResultType GPADC_startGroupConversion	(	GPADC_channelsGroupSelectType	channels,
		uint8_t	numChannels
	)

Starts and triggers the multi channel ADC conversion.

        Pass the channel selection bitmap for group conversion to the GPADC Driver and
        check the result buffer passed to the driver using GPADC_SetupResultBuffer()
        for conversion results of all configured channels.

        Conversion happens based on the parameters provided through GPADC_Init()
        for GPADC HW unit and each channel config like sampling parameters, buffered/ unbuffered.

        GPADC_Init() should be done before starting conversion
        Channel bitmap selected shouldn't be zero
        Result buffer should be setup before starting conversion using GPADC_SetupResultBuffer().

Parameters

[in]	channels	Channel selection bitmap to start conversion together
[in]	numChannels	number of channels

Returns: GPADC_CONV_ERROR: GPADC Conversion Error GPADC_CONV_DONE: GPADC Conversion Successfully Done GPADC_CONV_CHANNEL_CONFIG_MISSING: One or more of the bitmap selected channel group is missing configuration during initialization

◆ GPADC_startSingleChannelConversion()

GPADC_ConvResultType GPADC_startSingleChannelConversion	(	GPADC_MeasExtSrcType	channelID,
		uint16_t *	gpadcValue
	)

Starts and triggers the single channel conversion. Pass the channelID and result address to the driver and the result will be stored in the address passed.

Parameters

[in]	channelID	Channel index from <0-8> available external sources
[out]	gpadcValue	Pointer to the address where the result shall be stored.

Returns: GPADC_CONV_ERROR: GPADC Conversion Error GPADC_CONV_DONE: GPADC Conversion Successfully Done GPADC_CONV_CHANNEL_CONFIG_MISSING: The specified channel channel is not configured using GPADC_Init()

◆ GPADC_stopConversion()

int32_t GPADC_stopConversion ( void )

Stops the GPADC conversion.

        This API should not be called before initialization.\n
        This API should not be called before starting group/single channel start conversion\n
        To be used when the mode of conversion is chosen as GPADC_CONTINUOUS_CONV_MODE.

return If stop conversion is successful returns SystemP_SUCCESS, else error on failure

◆ GPADC_setupResultBuffer()

int32_t GPADC_setupResultBuffer ( uint16_t * ResBufferPtr )

Initializes GPADC driver with the group specific result buffer start address where the conversion results will be stored.

The application has to ensure that the application buffer, where ResBufferPtr points to, can hold all the conversion results of the specified group. The initialization with GPADC_SetupResultBuffer is required after GPADC_Init(), before a group conversion can be started.

Parameters

[in] ResBufferPtr

Returns: If Result Buffer Setup is successful returns SystemP_SUCCESS, else error on failure

◆ GPADC_readResultBuffer()

int32_t GPADC_readResultBuffer ( uint16_t * ResBufferPtr )

The function is used to read the result buffer from the GPADC Driver.

        Reads the group conversion result of the last completed conversion round
        of the requested group and stores the channel values starting at the
        ResBufferPtr address.

Parameters

[out] ResBufferPtr

Returns: On Read Result Buffer is successful returns SystemP_SUCCESS , else error on failure

◆ GPADC_getStatus()

GPADC_StatusType GPADC_getStatus ( void )

Gets the status of GPADC Driver HW unit.

Returns: GPADC_IDLE: The conversion of the specified group has not been started. No result is available. GPADC_BUSY: The conversion of the specified group has been started and is still going on. So far no result is available. GPADC_COMPLETED: A conversion round of the specified group has been finished. A result is available for all specified channels of the group.

◆ GPADC_readTemperature()

int32_t GPADC_readTemperature	(	uint8_t	numAverages,
		uint8_t	numChannels,
		GPADC_TempSensValueType *	tempValuesPtr
	)

Read the temperature sensor value.

Parameters

[in]	numAverages	number of average samples
[in]	numChannels	number of channels
[out]	tempValuesPtr	Pointer to store the temperature values

Returns: If temperature read is successful returns SystemP_SUCCESS, else error on failure

◆ GPADC_initTempMeasurement()

void GPADC_initTempMeasurement ( void )

Initialize GPADC efuse temperature parameters.

Introduction

Files

Data Structures

Functions

Enumerations

Macros

GPADC Macros

GPADC Modes

Instruction RAM Index

Macro Definition Documentation

◆ GPADC_DISABLE

◆ GPADC_ENABLE

◆ GPADC_ASSERT_RESET

◆ GPADC_DEASSERT_RESET

◆ GPADC_FSM_ASSERT_RESET

◆ GPADC_FSM_DEASSERT_RESET

◆ GPADC_MODE_DISABLE

◆ GPADC_MODE_IFM

◆ GPADC_MODE_CTM

◆ GPADC_MON_INSTR_RAM_ST_IND

◆ GPADC_MAX_MON_INSTR_RAM

◆ MAX_CTM_GPADC_PARAMS

◆ GPADC_TIMEOUT_MAX

◆ EFUSE_TRIM_TEMPERATURE_CONST

◆ EFUSE_TRIM_TEMPERATURE_DIV_CONST

◆ ZERO_PT_TRIM_FIXED_TRIM_TEMP

◆ ZERO_PT_TRIM_FIXED_DIG_TEMP_SENSOR_TRIM_30C

◆ ZERO

◆ ZERO_PT_TRIM_FIXED_SLOPE

◆ ONE_PT_TRIM_FIXED_SLOPE

◆ EFUSE1_ROW_14_FUSEROM_VER_START_BIT

◆ EFUSE1_ROW_14_FUSEROM_VER_STOP_BIT

◆ EFUSE1_ROW_36_TRIM_TEMPERATURE_30C_START_BIT

◆ EFUSE1_ROW_36_TRIM_TEMPERATURE_30C_STOP_BIT

◆ EFUSE1_ROW_33_TRIM_TEMPERATURE_125C_START_BIT

◆ EFUSE1_ROW_33_TRIM_TEMPERATURE_125C_STOP_BIT

◆ EFUSE1_ROW_37_DIG_DSP_TEMP_SENSOR_TRIM0_30C_START_BIT

◆ EFUSE1_ROW_37_DIG_DSP_TEMP_SENSOR_TRIM0_30C_STOP_BIT

◆ EFUSE1_ROW_37_DIG_HWA_TEMP_SENSOR_TRIM1_30C_START_BIT

◆ EFUSE1_ROW_37_DIG_HWA_TEMP_SENSOR_TRIM1_30C_STOP_BIT

◆ EFUSE1_ROW_38_DIG_HSM_TEMP_SENSOR_TRIM2_30C_START_BIT

◆ EFUSE1_ROW_38_DIG_HSM_TEMP_SENSOR_TRIM2_30C_STOP_BIT

◆ EFUSE1_ROW_34_DIG_DSP_TEMP_SENSOR_TRIM0_125C_START_BIT

◆ EFUSE1_ROW_34_DIG_DSP_TEMP_SENSOR_TRIM0_125C_STOP_BIT

◆ EFUSE1_ROW_34_DIG_HWA_TEMP_SENSOR_TRIM1_125C_START_BIT

◆ EFUSE1_ROW_34_DIG_HWA_TEMP_SENSOR_TRIM1_125C_STOP_BIT

◆ EFUSE1_ROW_35_DIG_HSM_TEMP_SENSOR_TRIM2_125C_START_BIT

◆ EFUSE1_ROW_35_DIG_HSM_TEMP_SENSOR_TRIM2_125C_STOP_BIT

◆ GPADC_REGS_PTR

◆ GPADCPKTRAM_REGS_PTR

◆ GPADCOUT_RAM_PTR

◆ MSS_GPADC_RST_CTRL_ADDR

◆ MSS_GPADC_RST_CTRL_PTR

◆ MSS_GPADC_CLK_DIV_VAL_ADDR

◆ MSS_GPADC_CLK_DIV_VAL_PTR

◆ MSS_GPADC_CLK_GATE_ADDR

◆ MSS_GPADC_CLK_GATE_PTR

◆ MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_ADDR

◆ MSS_TOPRCM_ANA_REG_TW_ANA_TMUX_CTRL_LOWV_PTR

◆ MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_ADDR

◆ MSS_TOPRCM_ANA_REG_REFSYS_SPARE_REG_LOWV_PTR

◆ MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_ADDR

◆ MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_PTR

◆ MSS_CTRL_MSS_GPADC_MEM_INIT_ADDR

◆ MSS_CTRL_MSS_GPADC_MEM_INIT_PTR

◆ REG_STRUCT_SWRITE

◆ REG32_SCOMPARE

◆ REG_STRUCT_SCLEAR

Enumeration Type Documentation

◆ GPADC_CtmTrigSrcType

◆ GPADC_ChannelConvModeType

◆ GPADC_TriggerSourceType

◆ GPADC_MeasExtSrcType

◆ GPADC_ConvResultType

◆ GPADC_StatusType

◆ GPADC_TempSensorSrcType

Function Documentation

◆ GPADC_init()

◆ GPADC_deinit()

◆ GPADC_open()