Interacts with the Cortex-M NVIC controller for configuring interrupts.
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Interacts with the Cortex-M NVIC controller for configuring interrupts.
Module Operation
The interrupt controller API provides a set of functions for dealing with the Nested Vectored Interrupt Controller (NVIC). Functions are provided to enable and disable interrupts, register interrupt handlers, and set the priority of interrupts.
The NVIC provides global interrupt masking, prioritization, and handler dispatching. Individual interrupt sources can be masked, and the processor interrupt can be globally masked as well (without affecting the individual source masks).
The NVIC is tightly coupled with the Cortex-M microprocessor. When the processor responds to an interrupt, the NVIC supplies the address of the function to handle the interrupt directly to the processor. This action eliminates the need for a global interrupt handler that queries the interrupt controller to determine the cause of the interrupt and branch to the appropriate handler, reducing interrupt response time.
The interrupt prioritization in the NVIC allows higher priority interrupts to be handled before lower priority interrupts, as well as allowing preemption of lower priority interrupt handlers by higher priority interrupts. Again, this helps reduce interrupt response time (for example, a 1 ms system control interrupt is not held off by the execution of a lower priority 1 second housekeeping interrupt handler).
Sub-prioritization is also possible; instead of having N bits of preemptable prioritization, the NVIC can be configured (via software) for N - M bits of preemptable prioritization and M bits of sub-priority. In this scheme, two interrupts with the same preemptable prioritization but different sub-priorities do not cause a preemption; tail chaining is used instead to process the two interrupts back-to-back.
If two interrupts with the same priority (and sub-priority if so configured) are asserted at the same time, the one with the lower interrupt number is processed first. The NVIC keeps track of the nesting of interrupt handlers, allowing the processor to return from interrupt context only once all nested and pending interrupts have been handled.
Interrupt handlers can be configured in one of two ways; statically at compile time or dynamically at run time. Static configuration of interrupt handlers is accomplished by editing the interrupt handler table in the application's startup code. When statically configured, the interrupts must be explicitly enabled in the NVIC via Interrupt_enableInterrupt() before the processor can respond to the interrupt (in addition to any interrupt enabling required within the peripheral itself). Statically configuring the interrupt table provides the fastest interrupt response time because the stacking operation (a write to SRAM) can be performed in parallel with the interrupt handler table fetch (a read from Flash), as well as the prefetch of the interrupt handler itself (assuming it is also in Flash).
Alternatively, interrupts can be configured at run-time using Interrupt_registerInterrupt(). When using Interrupt_registerInterrupt(), the interrupt must also be enabled as before; when using the analogue in each individual driver, Interrupt_enableInterrupt() is called by the driver and does not need to be called by the application. Run-time configuration of interrupts adds a small latency to the interrupt response time because the stacking operation (a write to SRAM) and the interrupt handler table fetch (a read from SRAM) must be performed sequentially.
Run-time configuration of interrupt handlers requires that the interrupt handler table be placed on a 1-kB boundary in SRAM (typically this is at the beginning of SRAM). Failure to do so results in an incorrect vector address being fetched in response to an interrupt. The vector table is in a section called ``vtable'' and should be placed appropriately with a linker script.
Basic Operation Modes
The primary function of the interrupt controller API is to manage the interrupt vector table used by the NVIC to dispatch interrupt requests. Registering an interrupt handler is a simple matter of inserting the handler address into the table. By default, the table is filled with pointers to an internal handler that loops forever; it is an error for an interrupt to occur when there is no interrupt handler registered to process it. Therefore, interrupt sources should not be enabled before a handler has been registered, and interrupt sources should be disabled before a handler is unregistered. Interrupt handlers are managed with
Interrupt_registerInterrupt() and
Interrupt_unregisterInterrupt().
Each interrupt source can be individually enabled and disabled via Interrupt_enableInterrupt() and Interrupt_disableInterrupt(). The processor interrupt can be enabled and disabled via Interrupt_enableMaster() and Interrupt_disableMaster(); this does not affect the individual interrupt enable states. Masking of the processor interrupt can be used as a simple critical section (only an NMI can interrupt the processor while the processor interrupt is disabled), although masking the processor interrupt can have adverse effects on the interrupt response time.
The priority of each interrupt source can be set and examined via Interrupt_setPriority() and Interrupt_getPriority(). The priority assignments are defined by the hardware; the upper N bits of the 8-bit priority are examined to determine the priority of an interrupt (for the MSP432 family, N is 3). This protocol allows priorities to be defined without knowledge of the exact number of supported priorities; moving to a device with more or fewer priority bits is made easier as the interrupt source continues to have a similar level of priority. Smaller priority numbers correspond to higher interrupt priority, so 0 is the highest priority.
Interrupt Programming Example
The DriverLib package contains a variety of different code examples that demonstrate the usage of the Interrupt module. These code examples are accessible under the examples/ folder of the SDK release as well as through TI Resource Explorer if using Code Composer Studio. These code examples provide a comprehensive list of use cases as well as practical applications involving each module.
Below is a very brief code example showing how to configure interrupt priorities. For a set of more detailed code examples, please refer to the code examples in the examples/ directory of the SDK release:
| #define FAULT_NMI ( 2) /* NMI fault */ |
| #define FAULT_HARD ( 3) /* Hard fault */ |
| #define FAULT_MPU ( 4) /* MPU fault */ |
| #define FAULT_BUS ( 5) /* Bus fault */ |
| #define FAULT_USAGE ( 6) /* Usage fault */ |
| #define FAULT_SVCALL (11) /* SVCall */ |
| #define FAULT_DEBUG (12) /* Debug monitor */ |
| #define FAULT_PENDSV (14) /* PendSV */ |
| #define FAULT_SYSTICK (15) /* System Tick */ |
| #define INT_PSS (16) /* PSS IRQ */ |
| #define INT_CS (17) /* CS IRQ */ |
| #define INT_PCM (18) /* PCM IRQ */ |
| #define INT_WDT_A (19) /* WDT_A IRQ */ |
| #define INT_FPU (20) /* FPU IRQ */ |
| #define INT_FLCTL (21) /* FLCTL IRQ */ |
| #define INT_COMP_E0 (22) /* COMP_E0 IRQ */ |
| #define INT_COMP_E1 (23) /* COMP_E1 IRQ */ |
| #define INT_TA0_0 (24) /* TA0_0 IRQ */ |
| #define INT_TA0_N (25) /* TA0_N IRQ */ |
| #define INT_TA1_0 (26) /* TA1_0 IRQ */ |
| #define INT_TA1_N (27) /* TA1_N IRQ */ |
| #define INT_TA2_0 (28) /* TA2_0 IRQ */ |
| #define INT_TA2_N (29) /* TA2_N IRQ */ |
| #define INT_TA3_0 (30) /* TA3_0 IRQ */ |
| #define INT_TA3_N (31) /* TA3_N IRQ */ |
| #define INT_EUSCIA0 (32) /* EUSCIA0 IRQ */ |
| #define INT_EUSCIA1 (33) /* EUSCIA1 IRQ */ |
| #define INT_EUSCIA2 (34) /* EUSCIA2 IRQ */ |
| #define INT_EUSCIA3 (35) /* EUSCIA3 IRQ */ |
| #define INT_EUSCIB0 (36) /* EUSCIB0 IRQ */ |
| #define INT_EUSCIB1 (37) /* EUSCIB1 IRQ */ |
| #define INT_EUSCIB2 (38) /* EUSCIB2 IRQ */ |
| #define INT_EUSCIB3 (39) /* EUSCIB3 IRQ */ |
| #define INT_ADC14 (40) /* ADC14 IRQ */ |
| #define INT_T32_INT1 (41) /* T32_INT1 IRQ */ |
| #define INT_T32_INT2 (42) /* T32_INT2 IRQ */ |
| #define INT_T32_INTC (43) /* T32_INTC IRQ */ |
| #define INT_AES256 (44) /* AES256 IRQ */ |
| #define INT_RTC_C (45) /* RTC_C IRQ */ |
| #define INT_DMA_ERR (46) /* DMA_ERR IRQ */ |
| #define INT_DMA_INT3 (47) /* DMA_INT3 IRQ */ |
| #define INT_DMA_INT2 (48) /* DMA_INT2 IRQ */ |
| #define INT_DMA_INT1 (49) /* DMA_INT1 IRQ */ |
| #define INT_DMA_INT0 (50) /* DMA_INT0 IRQ */ |
| #define INT_PORT1 (51) /* PORT1 IRQ */ |
| #define INT_PORT2 (52) /* PORT2 IRQ */ |
| #define INT_PORT3 (53) /* PORT3 IRQ */ |
| #define INT_PORT4 (54) /* PORT4 IRQ */ |
| #define INT_PORT5 (55) /* PORT5 IRQ */ |
| #define INT_PORT6 (56) /* PORT6 IRQ */ |
| #define INT_LCD_F (57) /* PORT6 IRQ */ |
| #define NUM_INTERRUPTS (57) |
| #define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) |
| #define NVIC_APINT_PRIGROUP_M 0x00000700 |
| #define NVIC_APINT_PRIGROUP_7_1 0x00000000 |
| #define NVIC_APINT_PRIGROUP_6_2 0x00000100 |
| #define NVIC_APINT_PRIGROUP_5_3 0x00000200 |
| #define NVIC_APINT_PRIGROUP_4_4 0x00000300 |
| #define NVIC_APINT_PRIGROUP_3_5 0x00000400 |
| #define NVIC_APINT_PRIGROUP_2_6 0x00000500 |
| #define NVIC_APINT_PRIGROUP_1_7 0x00000600 |
| #define NVIC_APINT_PRIGROUP_0_8 0x00000700 |
| #define NVIC_SYS_PRI1_R 0xE000ED18 |
| #define NVIC_SYS_PRI2_R 0xE000ED1C |
| #define NVIC_SYS_PRI3_R 0xE000ED20 |
| #define NVIC_PRI0_R 0xE000E400 |
| #define NVIC_PRI1_R 0xE000E404 |
| #define NVIC_PRI2_R 0xE000E408 |
| #define NVIC_PRI3_R 0xE000E40C |
| #define NVIC_PRI4_R 0xE000E410 |
| #define NVIC_PRI5_R 0xE000E414 |
| #define NVIC_PRI6_R 0xE000E418 |
| #define NVIC_PRI7_R 0xE000E41C |
| #define NVIC_PRI8_R 0xE000E420 |
| #define NVIC_PRI9_R 0xE000E424 |
| #define NVIC_PRI10_R 0xE000E428 |
| #define NVIC_PRI11_R 0xE000E42C |
| #define NVIC_PRI12_R 0xE000E430 |
| #define NVIC_PRI13_R 0xE000E434 |
| #define NVIC_PRI14_R 0xE000E438 |
| #define NVIC_PRI15_R 0xE000E43C |
| #define NVIC_EN0_R 0xE000E100 |
| #define NVIC_EN1_R 0xE000E104 |
| #define NVIC_DIS0_R 0xE000E180 |
| #define NVIC_DIS1_R 0xE000E184 |
| #define NVIC_PEND0_R 0xE000E200 |
| #define NVIC_PEND1_R 0xE000E204 |
| #define NVIC_UNPEND0_R 0xE000E280 |
| #define NVIC_UNPEND1_R 0xE000E284 |
| bool Interrupt_enableMaster |
( |
void |
| ) |
|
Enables the processor interrupt.
This function allows the processor to respond to interrupts. This function does not affect the set of interrupts enabled in the interrupt controller; it just gates the single interrupt from the controller to the processor.
- Returns
- Returns true if interrupts were disabled when the function was called or false if they were initially enabled.
Referenced by FlashCtl_A_eraseSector(), FlashCtl_A_performMassErase(), FlashCtl_A_programMemory(), FlashCtl_A_verifyMemory(), FlashCtl_eraseSector(), FlashCtl_performMassErase(), FlashCtl_programMemory(), FlashCtl_verifyMemory(), PCM_gotoLPM0InterruptSafe(), PCM_gotoLPM3InterruptSafe(), and PCM_gotoLPM4InterruptSafe().
| bool Interrupt_disableMaster |
( |
void |
| ) |
|
Disables the processor interrupt.
This function prevents the processor from receiving interrupts. This function does not affect the set of interrupts enabled in the interrupt controller; it just gates the single interrupt from the controller to the processor.
- Returns
- Returns true if interrupts were already disabled when the function was called or false if they were initially enabled.
References CPU_cpsid().
Referenced by FlashCtl_A_eraseSector(), FlashCtl_A_performMassErase(), FlashCtl_A_programMemory(), FlashCtl_A_verifyMemory(), FlashCtl_eraseSector(), FlashCtl_performMassErase(), FlashCtl_programMemory(), FlashCtl_verifyMemory(), PCM_gotoLPM0InterruptSafe(), PCM_gotoLPM3InterruptSafe(), and PCM_gotoLPM4InterruptSafe().
| void Interrupt_registerInterrupt |
( |
uint32_t |
interruptNumber, |
|
|
void(*)(void) |
intHandler |
|
) |
| |
Registers a function to be called when an interrupt occurs.
- Parameters
-
| interruptNumber | specifies the interrupt in question. |
| intHandler | is a pointer to the function to be called. |
- Note
- The use of this function (directly or indirectly via a peripheral driver interrupt register function) moves the interrupt vector table from flash to SRAM. Therefore, care must be taken when linking the application to ensure that the SRAM vector table is located at the beginning of SRAM; otherwise the NVIC does not look in the correct portion of memory for the vector table (it requires the vector table be on a 1 kB memory alignment). Normally, the SRAM vector table is so placed via the use of linker scripts. See the discussion of compile-time versus run-time interrupt handler registration in the introduction to this chapter.
-
This function is only used if the customer wants to specify the interrupt handler at run time. In most cases, this is done through means of the user setting the ISR function pointer in the startup file. Refer Refer to the Module Operation section for more details.
See Interrupt_enableInterrupt for details about the interrupt parameter
- Returns
- None.
References ASSERT, HWREG32, and NUM_INTERRUPTS.
Referenced by ADC14_registerInterrupt(), AES256_registerInterrupt(), COMP_E_registerInterrupt(), CS_registerInterrupt(), DMA_registerInterrupt(), FlashCtl_A_registerInterrupt(), FlashCtl_registerInterrupt(), GPIO_registerInterrupt(), I2C_registerInterrupt(), LCD_F_registerInterrupt(), MPU_registerInterrupt(), PCM_registerInterrupt(), PSS_registerInterrupt(), RTC_C_registerInterrupt(), SPI_registerInterrupt(), SysTick_registerInterrupt(), Timer32_registerInterrupt(), Timer_A_registerInterrupt(), UART_registerInterrupt(), and WDT_A_registerInterrupt().
| void Interrupt_unregisterInterrupt |
( |
uint32_t |
interruptNumber | ) |
|
Unregisters the function to be called when an interrupt occurs.
- Parameters
-
| interruptNumber | specifies the interrupt in question. |
This function is used to indicate that no handler should be called when the given interrupt is asserted to the processor. The interrupt source is automatically disabled (via Interrupt_disableInterrupt()) if necessary.
- See Also
- Interrupt_registerInterrupt() for important information about registering interrupt handlers.
See Interrupt_enableInterrupt for details about the interrupt parameter
- Returns
- None.
References ASSERT, and NUM_INTERRUPTS.
Referenced by ADC14_unregisterInterrupt(), AES256_unregisterInterrupt(), COMP_E_unregisterInterrupt(), CS_unregisterInterrupt(), DMA_unregisterInterrupt(), FlashCtl_A_unregisterInterrupt(), FlashCtl_unregisterInterrupt(), GPIO_unregisterInterrupt(), I2C_unregisterInterrupt(), LCD_F_unregisterInterrupt(), MPU_unregisterInterrupt(), PCM_unregisterInterrupt(), PSS_unregisterInterrupt(), RTC_C_unregisterInterrupt(), SPI_unregisterInterrupt(), SysTick_unregisterInterrupt(), Timer32_unregisterInterrupt(), Timer_A_unregisterInterrupt(), UART_unregisterInterrupt(), and WDT_A_unregisterInterrupt().
| void Interrupt_setPriorityGrouping |
( |
uint32_t |
bits | ) |
|
Sets the priority grouping of the interrupt controller.
- Parameters
-
| bits | specifies the number of bits of preemptable priority. |
This function specifies the split between preemptable priority levels and sub-priority levels in the interrupt priority specification. The range of the grouping values are dependent upon the hardware implementation; on the MSP432 family, three bits are available for hardware interrupt prioritization and therefore priority grouping values of three through seven have the same effect.
- Returns
- None.
References ASSERT, and NUM_PRIORITY.
| uint32_t Interrupt_getPriorityGrouping |
( |
void |
| ) |
|
Gets the priority grouping of the interrupt controller.
This function returns the split between preemptable priority levels and sub-priority levels in the interrupt priority specification.
- Returns
- The number of bits of preemptable priority.
References NUM_PRIORITY, and NVIC_APINT_PRIGROUP_M.
| void Interrupt_setPriority |
( |
uint32_t |
interruptNumber, |
|
|
uint8_t |
priority |
|
) |
| |
Sets the priority of an interrupt.
- Parameters
-
| interruptNumber | specifies the interrupt in question. |
| priority | specifies the priority of the interrupt. |
This function is used to set the priority of an interrupt. When multiple interrupts are asserted simultaneously, the ones with the highest priority are processed before the lower priority interrupts. Smaller numbers correspond to higher interrupt priorities; priority 0 is the highest interrupt priority.
The hardware priority mechanism only looks at the upper N bits of the priority level (where N is 3 for the MSP432 family), so any prioritization must be performed in those bits. The remaining bits can be used to sub-prioritize the interrupt sources, and may be used by the hardware priority mechanism on a future part. This arrangement allows priorities to migrate to different NVIC implementations without changing the gross prioritization of the interrupts.
See Interrupt_enableInterrupt for details about the interrupt parameter
- Returns
- None.
References ASSERT, HWREG32, and NUM_INTERRUPTS.
| uint8_t Interrupt_getPriority |
( |
uint32_t |
interruptNumber | ) |
|
Gets the priority of an interrupt.
- Parameters
-
| interruptNumber | specifies the interrupt in question. |
This function gets the priority of an interrupt. See Interrupt_setPriority() for a definition of the priority value.
See Interrupt_enableInterrupt for details about the interrupt parameter
- Returns
- Returns the interrupt priority, or -1 if an invalid interrupt was specified.
References ASSERT, HWREG32, and NUM_INTERRUPTS.
| void Interrupt_enableInterrupt |
( |
uint32_t |
interruptNumber | ) |
|
Enables an interrupt.
- Parameters
-
| interruptNumber | specifies the interrupt to be enabled. |
The specified interrupt is enabled in the interrupt controller. Other enables for the interrupt (such as at the peripheral level) are unaffected by this function.
Valid values will vary from part to part, so it is important to check the device specific datasheet, however for MSP432 101 the following values can be provided:
- FAULT_NMI
- FAULT_HARD
- FAULT_MPU
- FAULT_BUS
- FAULT_USAGE
- FAULT_SVCALL
- FAULT_DEBUG
- FAULT_PENDSV
- FAULT_SYSTICK
- INT_PSS
- INT_CS
- INT_PCM
- INT_WDT_A
- INT_FPU
- INT_FLCTL
- INT_COMP0
- INT_COMP1
- INT_TA0_0
- INT_TA0_N
- INT_TA1_0
- INT_TA1_N
- INT_TA2_0
- INT_TA2_N
- INT_TA3_0
- INT_TA3_N
- INT_EUSCIA0
- INT_EUSCIA1
- INT_EUSCIA2
- INT_EUSCIA3
- INT_EUSCIB0
- INT_EUSCIB1
- INT_EUSCIB2
- INT_EUSCIB3
- INT_ADC14
- INT_T32_INT1
- INT_T32_INT2
- INT_T32_INTC
- INT_AES
- INT_RTCC
- INT_DMA_ERR
- INT_DMA_INT3
- INT_DMA_INT2
- INT_DMA_INT1
- INT_DMA_INT0
- INT_PORT1
- INT_PORT2
- INT_PORT3
- INT_PORT4
- INT_PORT5
- INT_PORT6
- Returns
- None.
References ASSERT, FAULT_BUS, FAULT_MPU, FAULT_SYSTICK, FAULT_USAGE, HWREG32, and NUM_INTERRUPTS.
Referenced by ADC14_registerInterrupt(), AES256_registerInterrupt(), COMP_E_registerInterrupt(), CS_registerInterrupt(), DMA_registerInterrupt(), FlashCtl_A_registerInterrupt(), FlashCtl_registerInterrupt(), GPIO_registerInterrupt(), I2C_registerInterrupt(), LCD_F_registerInterrupt(), MPU_enableInterrupt(), PCM_registerInterrupt(), PSS_registerInterrupt(), RTC_C_registerInterrupt(), SPI_registerInterrupt(), Timer32_registerInterrupt(), Timer_A_registerInterrupt(), UART_registerInterrupt(), and WDT_A_registerInterrupt().
| void Interrupt_disableInterrupt |
( |
uint32_t |
interruptNumber | ) |
|
Disables an interrupt.
- Parameters
-
| interruptNumber | specifies the interrupt to be disabled. |
The specified interrupt is disabled in the interrupt controller. Other enables for the interrupt (such as at the peripheral level) are unaffected by this function.
See Interrupt_enableInterrupt for details about the interrupt parameter
- Returns
- None.
References ASSERT, FAULT_BUS, FAULT_MPU, FAULT_SYSTICK, FAULT_USAGE, HWREG32, and NUM_INTERRUPTS.
Referenced by ADC14_unregisterInterrupt(), AES256_unregisterInterrupt(), COMP_E_unregisterInterrupt(), CS_unregisterInterrupt(), DMA_unregisterInterrupt(), FlashCtl_A_unregisterInterrupt(), FlashCtl_unregisterInterrupt(), GPIO_unregisterInterrupt(), I2C_unregisterInterrupt(), LCD_F_unregisterInterrupt(), MPU_disableInterrupt(), PCM_unregisterInterrupt(), PSS_unregisterInterrupt(), RTC_C_unregisterInterrupt(), SPI_unregisterInterrupt(), Timer32_unregisterInterrupt(), Timer_A_unregisterInterrupt(), UART_unregisterInterrupt(), and WDT_A_unregisterInterrupt().
| bool Interrupt_isEnabled |
( |
uint32_t |
interruptNumber | ) |
|
| void Interrupt_pendInterrupt |
( |
uint32_t |
interruptNumber | ) |
|
Pends an interrupt.
- Parameters
-
| interruptNumber | specifies the interrupt to be pended. |
The specified interrupt is pended in the interrupt controller. Pending an interrupt causes the interrupt controller to execute the corresponding interrupt handler at the next available time, based on the current interrupt state priorities. For example, if called by a higher priority interrupt handler, the specified interrupt handler is not called until after the current interrupt handler has completed execution. The interrupt must have been enabled for it to be called.
See Interrupt_enableInterrupt for details about the interrupt parameter
- Returns
- None.
References ASSERT, FAULT_NMI, FAULT_PENDSV, FAULT_SYSTICK, HWREG32, and NUM_INTERRUPTS.
| void Interrupt_unpendInterrupt |
( |
uint32_t |
interruptNumber | ) |
|
Un-pends an interrupt.
- Parameters
-
| interruptNumber | specifies the interrupt to be un-pended. |
The specified interrupt is un-pended in the interrupt controller. This will cause any previously generated interrupts that have not been handled yet (due to higher priority interrupts or the interrupt no having been enabled yet) to be discarded.
See Interrupt_enableInterrupt for details about the interrupt parameter
- Returns
- None.
References ASSERT, FAULT_PENDSV, FAULT_SYSTICK, HWREG32, and NUM_INTERRUPTS.
| void Interrupt_setPriorityMask |
( |
uint8_t |
priorityMask | ) |
|
Sets the priority masking level
- Parameters
-
| priorityMask | is the priority level that is masked. |
This function sets the interrupt priority masking level so that all interrupts at the specified or lesser priority level are masked. Masking interrupts can be used to globally disable a set of interrupts with priority below a predetermined threshold. A value of 0 disables priority masking.
Smaller numbers correspond to higher interrupt priorities. So for example a priority level mask of 4 allows interrupts of priority level 0-3, and interrupts with a numerical priority of 4 and greater are blocked.
The hardware priority mechanism only looks at the upper N bits of the priority level (where N is 3 for the MSP432 family), so any prioritization must be performed in those bits.
- Returns
- None.
References CPU_basepriSet().
| uint8_t Interrupt_getPriorityMask |
( |
void |
| ) |
|
Gets the priority masking level
This function gets the current setting of the interrupt priority masking level. The value returned is the priority level such that all interrupts of that and lesser priority are masked. A value of 0 means that priority masking is disabled.
Smaller numbers correspond to higher interrupt priorities. So for example a priority level mask of 4 allows interrupts of priority level 0-3, and interrupts with a numerical priority of 4 and greater are blocked.
The hardware priority mechanism only looks at the upper N bits of the priority level (where N is 3 for the MSP432 family), so any prioritization must be performed in those bits.
- Returns
- Returns the value of the interrupt priority level mask.
References CPU_basepriGet().
| void Interrupt_setVectorTableAddress |
( |
uint32_t |
addr | ) |
|
Sets the address of the vector table. This function is for advanced users who might want to switch between multiple instances of vector tables (perhaps between flash/ram).
- Parameters
-
| addr | is the new address of the vector table. |
- Returns
- None.
| uint32_t Interrupt_getVectorTableAddress |
( |
void |
| ) |
|
Returns the address of the interrupt vector table.
- Returns
- Address of the vector table.
| void Interrupt_enableSleepOnIsrExit |
( |
void |
| ) |
|
Enables the processor to sleep when exiting an ISR. For low power operation, this is ideal as power cycles are not wasted with the processing required for waking up from an ISR and going back to sleep.
- Returns
- None
| void Interrupt_disableSleepOnIsrExit |
( |
void |
| ) |
|
Disables the processor to sleep when exiting an ISR.
- Returns
- None
