EVTSVT

Instance: EVTSVT
Component: EVTSVT
Base address: 0x40025000


This is top module of SVT Event Fabric

TOP:EVTSVT Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

DESC

RO

32

0x3045 1010

0x0000 0000

0x4002 5000

DESCEX

RO

32

0x0218 2D31

0x0000 0004

0x4002 5004

DTB

RW

32

0x0000 0000

0x0000 0064

0x4002 5064

NMISEL

RW

32

0x0000 0000

0x0000 0400

0x4002 5400

CPUIRQ0SEL

RW

32

0x0000 0000

0x0000 0404

0x4002 5404

CPUIRQ1SEL

RW

32

0x0000 0000

0x0000 0408

0x4002 5408

CPUIRQ2SEL

RW

32

0x0000 0000

0x0000 040C

0x4002 540C

CPUIRQ3SEL

RW

32

0x0000 0000

0x0000 0410

0x4002 5410

CPUIRQ4SEL

RW

32

0x0000 0000

0x0000 0414

0x4002 5414

CPUIRQ5SEL

RO

32

0x0000 0009

0x0000 0418

0x4002 5418

CPUIRQ6SEL

RO

32

0x0000 000C

0x0000 041C

0x4002 541C

CPUIRQ7SEL

RO

32

0x0000 000D

0x0000 0420

0x4002 5420

CPUIRQ8SEL

RO

32

0x0000 0014

0x0000 0424

0x4002 5424

CPUIRQ9SEL

RO

32

0x0000 0016

0x0000 0428

0x4002 5428

CPUIRQ10SEL

RO

32

0x0000 000F

0x0000 042C

0x4002 542C

CPUIRQ11SEL

RO

32

0x0000 0017

0x0000 0430

0x4002 5430

CPUIRQ12SEL

RO

32

0x0000 0018

0x0000 0434

0x4002 5434

CPUIRQ13SEL

RO

32

0x0000 0012

0x0000 0438

0x4002 5438

CPUIRQ14SEL

RO

32

0x0000 0013

0x0000 043C

0x4002 543C

CPUIRQ15SEL

RO

32

0x0000 0010

0x0000 0440

0x4002 5440

CPUIRQ16SEL

RW

32

0x0000 0000

0x0000 0444

0x4002 5444

CPUIRQ17SEL

RO

32

0x0000 0031

0x0000 0448

0x4002 5448

CPUIRQ18SEL

RO

32

0x0000 0037

0x0000 044C

0x4002 544C

SYSTIMC0SEL

RO

32

0x0000 0004

0x0000 0450

0x4002 5450

SYSTIMC1SEL

RW

32

0x0000 0000

0x0000 0454

0x4002 5454

SYSTIMC2SEL

RO

32

0x0000 002A

0x0000 0458

0x4002 5458

SYSTIMC3SEL

RO

32

0x0000 002B

0x0000 045C

0x4002 545C

SYSTIMC4SEL

RO

32

0x0000 002C

0x0000 0460

0x4002 5460

ADCTRGSEL

RW

32

0x0000 0000

0x0000 0464

0x4002 5464

LGPTSYNCSEL

RW

32

0x0000 0000

0x0000 0468

0x4002 5468

LGPT0IN0SEL

RW

32

0x0000 0000

0x0000 046C

0x4002 546C

LGPT0IN1SEL

RW

32

0x0000 0000

0x0000 0470

0x4002 5470

LGPT0IN2SEL

RW

32

0x0000 0000

0x0000 0474

0x4002 5474

LGPT0TENSEL

RW

32

0x0000 0000

0x0000 0478

0x4002 5478

LGPT1IN0SEL

RW

32

0x0000 0000

0x0000 047C

0x4002 547C

LGPT1IN1SEL

RW

32

0x0000 0000

0x0000 0480

0x4002 5480

LGPT1IN2SEL

RW

32

0x0000 0000

0x0000 0484

0x4002 5484

LGPT1TENSEL

RW

32

0x0000 0000

0x0000 0488

0x4002 5488

LGPT2IN0SEL

RW

32

0x0000 0000

0x0000 048C

0x4002 548C

LGPT2IN1SEL

RW

32

0x0000 0000

0x0000 0490

0x4002 5490

LGPT2IN2SEL

RW

32

0x0000 0000

0x0000 0494

0x4002 5494

LGPT2TENSEL

RW

32

0x0000 0000

0x0000 0498

0x4002 5498

LGPT3IN0SEL

RW

32

0x0000 0000

0x0000 049C

0x4002 549C

LGPT3IN1SEL

RW

32

0x0000 0000

0x0000 04A0

0x4002 54A0

LGPT3IN2SEL

RW

32

0x0000 0000

0x0000 04A4

0x4002 54A4

LGPT3TENSEL

RW

32

0x0000 0000

0x0000 04A8

0x4002 54A8

LRFDIN0SEL

RO

32

0x0000 001D

0x0000 04AC

0x4002 54AC

LRFDIN1SEL

RO

32

0x0000 001E

0x0000 04B0

0x4002 54B0

LRFDIN2SEL

RO

32

0x0000 001F

0x0000 04B4

0x4002 54B4

DMACH0SEL

RW

32

0x0000 0000

0x0000 0C00

0x4002 5C00

DMACH1SEL

RW

32

0x0000 0000

0x0000 0C04

0x4002 5C04

DMACH2SEL

RW

32

0x0000 0000

0x0000 0C08

0x4002 5C08

DMACH3SEL

RW

32

0x0000 0000

0x0000 0C0C

0x4002 5C0C

DMACH4SEL

RW

32

0x0000 0000

0x0000 0C10

0x4002 5C10

DMACH5SEL

RW

32

0x0000 0000

0x0000 0C14

0x4002 5C14

DMACH6SEL

RW

32

0x0000 0000

0x0000 0C18

0x4002 5C18

DMACH7SEL

RW

32

0x0000 0000

0x0000 0C1C

0x4002 5C1C

TOP:EVTSVT Register Descriptions

TOP:EVTSVT:DESC

Address Offset 0x0000 0000
Physical Address 0x4002 5000 Instance 0x4002 5000
Description Description

This register provides IP module ID, revision information, instance index and standard MMR registers offset.
Type RO
Bits Field Name Description Type Reset
31:16 MODID Module identifier used to uniquely identify this IP. RO 0x3045
15:12 STDIPOFF Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)		 RO 0x1
11:8 INSTIDX IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15). RO 0x0
7:4 MAJREV Major revision of IP (0-15). RO 0x1
3:0 MINREV Minor revision of IP (0-15). RO 0x0

TOP:EVTSVT:DESCEX

Address Offset 0x0000 0004
Physical Address 0x4002 5004 Instance 0x4002 5004
Description Extended Description

This register provides configuration details of the IP to software drivers and end users.
Type RO
Bits Field Name Description Type Reset
31:22 IDMA Number of DMA input channels RO 0b00 0000 1000
21:17 NDMA Number of DMA output channels RO 0b0 1100
16 PD Power Domain.
0 : SVT
1 : ULL		 RO 0
15:8 NSUB Number of Subscribers RO 0x2D
7:0 NPUB Number of Publishers RO 0x31

TOP:EVTSVT:DTB

Address Offset 0x0000 0064
Physical Address 0x4002 5064 Instance 0x4002 5064
Description Digital test bus control

This register can be used to bring out IP internal signals to the pads for observation. 16 signals can be observed per select value.
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000 0000
1:0 SEL Digital test bus selection mux control.
Non-zero select values output a 16 bit selected group of signals per value.
Value ENUM Name Description
0x0 DIS All 16 observation signals are set to zero.
RW 0b00

TOP:EVTSVT:NMISEL

Address Offset 0x0000 0400
Physical Address 0x4002 5400 Instance 0x4002 5400
Description Output Selection for CPU NMI Exception
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x1 AON_NMI_SEL Selects an AON_NMI source, controlled by EVTULL:NMISEL
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:CPUIRQ0SEL

Address Offset 0x0000 0404
Physical Address 0x4002 5404 Instance 0x4002 5404
Description Output Selection for CPU Interrupt CPUIRQ0
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:CPUIRQ1SEL

Address Offset 0x0000 0408
Physical Address 0x4002 5408 Instance 0x4002 5408
Description Output Selection for CPU Interrupt CPUIRQ1
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:CPUIRQ2SEL

Address Offset 0x0000 040C
Physical Address 0x4002 540C Instance 0x4002 540C
Description Output Selection for CPU Interrupt CPUIRQ2
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
RW 0b00 0000

TOP:EVTSVT:CPUIRQ3SEL

Address Offset 0x0000 0410
Physical Address 0x4002 5410 Instance 0x4002 5410
Description Output Selection for CPU Interrupt CPUIRQ3
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
RW 0b00 0000

TOP:EVTSVT:CPUIRQ4SEL

Address Offset 0x0000 0414
Physical Address 0x4002 5414 Instance 0x4002 5414
Description Output Selection for CPU Interrupt CPUIRQ4
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
RW 0b00 0000

TOP:EVTSVT:CPUIRQ5SEL

Address Offset 0x0000 0418
Physical Address 0x4002 5418 Instance 0x4002 5418
Description Output Selection for CPU Interrupt CPUIRQ5
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
RO 0b00 1001

TOP:EVTSVT:CPUIRQ6SEL

Address Offset 0x0000 041C
Physical Address 0x4002 541C Instance 0x4002 541C
Description Output Selection for CPU Interrupt CPUIRQ6
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
RO 0b00 1100

TOP:EVTSVT:CPUIRQ7SEL

Address Offset 0x0000 0420
Physical Address 0x4002 5420 Instance 0x4002 5420
Description Output Selection for CPU Interrupt CPUIRQ7
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
RO 0b00 1101

TOP:EVTSVT:CPUIRQ8SEL

Address Offset 0x0000 0424
Physical Address 0x4002 5424 Instance 0x4002 5424
Description Output Selection for CPU Interrupt CPUIRQ8
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
RO 0b01 0100

TOP:EVTSVT:CPUIRQ9SEL

Address Offset 0x0000 0428
Physical Address 0x4002 5428 Instance 0x4002 5428
Description Output Selection for CPU Interrupt CPUIRQ9
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
RO 0b01 0110

TOP:EVTSVT:CPUIRQ10SEL

Address Offset 0x0000 042C
Physical Address 0x4002 542C Instance 0x4002 542C
Description Output Selection for CPU Interrupt CPUIRQ10
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
RO 0b00 1111

TOP:EVTSVT:CPUIRQ11SEL

Address Offset 0x0000 0430
Physical Address 0x4002 5430 Instance 0x4002 5430
Description Output Selection for CPU Interrupt CPUIRQ11
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
RO 0b01 0111

TOP:EVTSVT:CPUIRQ12SEL

Address Offset 0x0000 0434
Physical Address 0x4002 5434 Instance 0x4002 5434
Description Output Selection for CPU Interrupt CPUIRQ12
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
RO 0b01 1000

TOP:EVTSVT:CPUIRQ13SEL

Address Offset 0x0000 0438
Physical Address 0x4002 5438 Instance 0x4002 5438
Description Output Selection for CPU Interrupt CPUIRQ13
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
RO 0b01 0010

TOP:EVTSVT:CPUIRQ14SEL

Address Offset 0x0000 043C
Physical Address 0x4002 543C Instance 0x4002 543C
Description Output Selection for CPU Interrupt CPUIRQ14
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
RO 0b01 0011

TOP:EVTSVT:CPUIRQ15SEL

Address Offset 0x0000 0440
Physical Address 0x4002 5440 Instance 0x4002 5440
Description Output Selection for CPU Interrupt CPUIRQ15
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
RO 0b01 0000

TOP:EVTSVT:CPUIRQ16SEL

Address Offset 0x0000 0444
Physical Address 0x4002 5444 Instance 0x4002 5444
Description Output Selection for CPU Interrupt CPUIRQ16
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:CPUIRQ17SEL

Address Offset 0x0000 0448
Physical Address 0x4002 5448 Instance 0x4002 5448
Description Output Selection for CPU Interrupt CPUIRQ17
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
RO 0b11 0001

TOP:EVTSVT:CPUIRQ18SEL

Address Offset 0x0000 044C
Physical Address 0x4002 544C Instance 0x4002 544C
Description Output Selection for CPU Interrupt CPUIRQ18
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
RO 0b11 0111

TOP:EVTSVT:SYSTIMC0SEL

Address Offset 0x0000 0450
Physical Address 0x4002 5450 Instance 0x4002 5450
Description Output Selection for SYSTIMC0
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
RO 0b00 0100

TOP:EVTSVT:SYSTIMC1SEL

Address Offset 0x0000 0454
Physical Address 0x4002 5454 Instance 0x4002 5454
Description Output Selection for SYSTIMC1
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:SYSTIMC2SEL

Address Offset 0x0000 0458
Physical Address 0x4002 5458 Instance 0x4002 5458
Description Output Selection for SYSTIMC2
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
RO 0b10 1010

TOP:EVTSVT:SYSTIMC3SEL

Address Offset 0x0000 045C
Physical Address 0x4002 545C Instance 0x4002 545C
Description Output Selection for SYSTIMC3
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
RO 0b10 1011

TOP:EVTSVT:SYSTIMC4SEL

Address Offset 0x0000 0460
Physical Address 0x4002 5460 Instance 0x4002 5460
Description Output Selection for SYSTIMC4
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
RO 0b10 1100

TOP:EVTSVT:ADCTRGSEL

Address Offset 0x0000 0464
Physical Address 0x4002 5464 Instance 0x4002 5464
Description Output Selection for ADCTRG
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPTSYNCSEL

Address Offset 0x0000 0468
Physical Address 0x4002 5468 Instance 0x4002 5468
Description Output Selection for LGPTSYNC
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT0IN0SEL

Address Offset 0x0000 046C
Physical Address 0x4002 546C Instance 0x4002 546C
Description Output Selection for LGPT0IN0
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT0IN1SEL

Address Offset 0x0000 0470
Physical Address 0x4002 5470 Instance 0x4002 5470
Description Output Selection for LGPT0IN1
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT0IN2SEL

Address Offset 0x0000 0474
Physical Address 0x4002 5474 Instance 0x4002 5474
Description Output Selection for LGPT0IN2
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT0TENSEL

Address Offset 0x0000 0478
Physical Address 0x4002 5478 Instance 0x4002 5478
Description Output Selection for LGPT0TEN
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT1IN0SEL

Address Offset 0x0000 047C
Physical Address 0x4002 547C Instance 0x4002 547C
Description Output Selection for LGPT1IN0
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT1IN1SEL

Address Offset 0x0000 0480
Physical Address 0x4002 5480 Instance 0x4002 5480
Description Output Selection for LGPT1IN1
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT1IN2SEL

Address Offset 0x0000 0484
Physical Address 0x4002 5484 Instance 0x4002 5484
Description Output Selection for LGPT1IN2
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT1TENSEL

Address Offset 0x0000 0488
Physical Address 0x4002 5488 Instance 0x4002 5488
Description Output Selection for LGPT1TEN
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT2IN0SEL

Address Offset 0x0000 048C
Physical Address 0x4002 548C Instance 0x4002 548C
Description Output Selection for LGPT2IN0
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT2IN1SEL

Address Offset 0x0000 0490
Physical Address 0x4002 5490 Instance 0x4002 5490
Description Output Selection for LGPT2IN1
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT2IN2SEL

Address Offset 0x0000 0494
Physical Address 0x4002 5494 Instance 0x4002 5494
Description Output Selection for LGPT2IN2
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT2TENSEL

Address Offset 0x0000 0498
Physical Address 0x4002 5498 Instance 0x4002 5498
Description Output Selection for LGPT2TEN
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT3IN0SEL

Address Offset 0x0000 049C
Physical Address 0x4002 549C Instance 0x4002 549C
Description Output Selection for LGPT3IN0
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT3IN1SEL

Address Offset 0x0000 04A0
Physical Address 0x4002 54A0 Instance 0x4002 54A0
Description Output Selection for LGPT3IN1
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT3IN2SEL

Address Offset 0x0000 04A4
Physical Address 0x4002 54A4 Instance 0x4002 54A4
Description Output Selection for LGPT3IN2
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LGPT3TENSEL

Address Offset 0x0000 04A8
Physical Address 0x4002 54A8 Instance 0x4002 54A8
Description Output Selection for LGPT3TEN
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:LRFDIN0SEL

Address Offset 0x0000 04AC
Physical Address 0x4002 54AC Instance 0x4002 54AC
Description Output Selection for LRFDIN0
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
RO 0b01 1101

TOP:EVTSVT:LRFDIN1SEL

Address Offset 0x0000 04B0
Physical Address 0x4002 54B0 Instance 0x4002 54B0
Description Output Selection for LRFDIN1
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
RO 0b01 1110

TOP:EVTSVT:LRFDIN2SEL

Address Offset 0x0000 04B4
Physical Address 0x4002 54B4 Instance 0x4002 54B4
Description Output Selection for LRFDIN2
Type RO
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
5:0 PUBID Read only selection value
Value ENUM Name Description
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
RO 0b01 1111

TOP:EVTSVT:DMACH0SEL

Address Offset 0x0000 0C00
Physical Address 0x4002 5C00 Instance 0x4002 5C00
Description Output Selection for DMA CH0
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
2:0 IPID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 SPI0TXTRG Selects spi0txtrg as channel source
0x7 UART0RXTRG Selects uart0rxtrg as channel source
RW 0b000

TOP:EVTSVT:DMACH1SEL

Address Offset 0x0000 0C04
Physical Address 0x4002 5C04 Instance 0x4002 5C04
Description Output Selection for DMA CH1
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
2:0 IPID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x1 SPI0RXTRG Selects spi0rxtrg as channel source
0x6 UART0TXTRG Selects uart0txtrg as channel source
RW 0b000

TOP:EVTSVT:DMACH2SEL

Address Offset 0x0000 0C08
Physical Address 0x4002 5C08 Instance 0x4002 5C08
Description Output Selection for DMA CH2
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
2:0 IPID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x2 RSVD Reserved value. Should not be programmed.
0x6 UART0TXTRG Selects uart0txtrg as channel source
RW 0b000

TOP:EVTSVT:DMACH3SEL

Address Offset 0x0000 0C0C
Physical Address 0x4002 5C0C Instance 0x4002 5C0C
Description Output Selection for DMA CH3
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
2:0 IPID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x5 ADC0TRG Selects adc0trg as channel source
0x7 UART0RXTRG Selects uart0rxtrg as channel source
RW 0b000

TOP:EVTSVT:DMACH4SEL

Address Offset 0x0000 0C10
Physical Address 0x4002 5C10 Instance 0x4002 5C10
Description Output Selection for DMA CH4
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
2:0 IPID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x2 RSVD Reserved value. Should not be programmed.
0x3 LAESTRGA Selects laestrga as channel source
RW 0b000

TOP:EVTSVT:DMACH5SEL

Address Offset 0x0000 0C14
Physical Address 0x4002 5C14 Instance 0x4002 5C14
Description Output Selection for DMA CH5
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000 0000 0000 0000 0000
2:0 IPID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x4 LAESTRGB Selects laestrgb as channel source
0x5 ADC0TRG Selects adc0trg as channel source
RW 0b000

TOP:EVTSVT:DMACH6SEL

Address Offset 0x0000 0C18
Physical Address 0x4002 5C18 Instance 0x4002 5C18
Description Output Selection for DMA CH6
Type RW
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
16 EDGDETDIS Edge detect disable.
0: Enabled.
1: Disabled		 RW 0
15:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000

TOP:EVTSVT:DMACH7SEL

Address Offset 0x0000 0C1C
Physical Address 0x4002 5C1C Instance 0x4002 5C1C
Description Output Selection for DMA CH7
Type RW
Bits Field Name Description Type Reset
31:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b000 0000 0000 0000
16 EDGDETDIS Edge detect disable.
0: Enabled.
1: Disabled		 RW 0
15:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior RO 0b00 0000 0000
5:0 PUBID Read/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
Value ENUM Name Description
0x0 NONE Always inactive
0x2 AON_PMU_COMB PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
0x3 AON_CKM_COMB CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
0x4 AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting
0x5 AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
0x6 AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
0x7 AON_IOC_COMB IOC synchronous combined event, controlled by IOC:EVTCFG
0x8 SYSTIM_COMB SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
0x9 GPIO_COMB GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
0xA GPIO_EVT GPIO generic published event, controlled by GPIO:EVTCFG
0xB FLASH_IRQ NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
0xC LRFD_IRQ0 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
0xD LRFD_IRQ1 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
0xE LRFD_IRQ2 LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
0xF SPI0_COMB SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
0x10 ADC_COMB ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
0x11 ADC_EVT ADC general published event, interrupt flags can be found here ADC:MIS1
0x12 LGPT0_COMB LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
0x13 LGPT1_COMB LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
0x14 DMA_DONE_COMB DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
0x15 DMA_ERR DMA bus error, corresponds to DMA:ERROR.STATUS
0x16 AES_COMB AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
0x17 UART0_COMB UART0 combined interrupt, interrupt flags are found here UART0:MIS
0x18 I2C0_IRQ Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
0x19 SYSTIM_HB SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
0x1A SYSTIM_LT SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
0x1B SYSTIM0 SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
0x1C SYSTIM1 SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
0x1D SYSTIM2 SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
0x1E SYSTIM3 SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
0x1F SYSTIM4 SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
0x20 LGPT0C0 LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
0x21 LGPT0C1 LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
0x22 LGPT0C2 LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
0x23 LGPT0_DMA LGPT0 DMA request event, controlled by LGPT0:DMA setting
0x24 LGPT0_ADC LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
0x25 LGPT1C0 LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
0x26 LGPT1C1 LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
0x27 LGPT1C2 LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
0x28 LGPT1_DMA LGPT1 DMA request event, controlled by LGPT1:DMA setting
0x29 LGPT1_ADC LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
0x2A LRFD_EVT0 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
0x2B LRFD_EVT1 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
0x2C LRFD_EVT2 LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
0x2E LGPT2C0 LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
0x2F LGPT2C1 LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
0x30 LGPT2C2 LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
0x31 LGPT2_COMB LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
0x32 LGPT2_DMA LGPT2 DMA request event, controlled by LGPT2:DMA setting
0x33 LGPT2_ADC LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
0x34 LGPT3C0 LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
0x35 LGPT3C1 LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
0x36 LGPT3C2 LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
0x37 LGPT3_COMB LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
0x38 LGPT3_DMA LGPT3 DMA request event, controlled by LGPT3:DMA setting
0x39 LGPT3_ADC LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting
RW 0b00 0000


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