UART0

Instance: UART0
Component: UART
Base address: 0x40034000


Universal Asynchronous Receiver/Transmitter (UART) interface

TOP:UART0 Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

DR

RW

32

0x0000 0000

0x0000 0000

0x4003 4000

RSR_ECR

RW

32

0x0000 0000

0x0000 0004

0x4003 4004

FR

RO

32

0x0000 0091

0x0000 0018

0x4003 4018

UARTILPR

RW

32

0x0000 0000

0x0000 0020

0x4003 4020

IBRD

RW

32

0x0000 0000

0x0000 0024

0x4003 4024

FBRD

RW

32

0x0000 0000

0x0000 0028

0x4003 4028

LCRH

RW

32

0x0000 0000

0x0000 002C

0x4003 402C

CTL

RW

32

0x0000 0300

0x0000 0030

0x4003 4030

IFLS

RW

32

0x0000 0012

0x0000 0034

0x4003 4034

IMSC

RW

32

0x0000 0000

0x0000 0038

0x4003 4038

RIS

RO

32

0x0000 000D

0x0000 003C

0x4003 403C

MIS

RO

32

0x0000 0000

0x0000 0040

0x4003 4040

ICR

WO

32

0x0000 0000

0x0000 0044

0x4003 4044

DMACTL

RW

32

0x0000 0000

0x0000 0048

0x4003 4048

TOP:UART0 Register Descriptions

TOP:UART0:DR

Address Offset 0x0000 0000
Physical Address 0x4003 4000 Instance 0x4003 4000
Description Data
For words to be transmitted:
- if the FIFOs are enabled (LCRH.FEN = 1), data written to this location is pushed onto the transmit FIFO
- if the FIFOs are not enabled (LCRH.FEN = 0), data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
The write operation initiates transmission from the UART. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit.
The resultant word is then transmitted.
For received words:
- if the FIFOs are enabled (LCRH.FEN = 1), the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO
- if the FIFOs are not enabled (LCRH.FEN = 0), the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO).
The received data byte is read by performing reads from this register along with the corresponding status information. The status information can also be read by a read of the RSR_ECR register.
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Reads to this field return zero, writes to this field are ignored. RO 0x0 0000
11 OE UART Overrun Error:
This bit is set to 1 if data is received and the receive FIFO is already full. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten.
This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.		 RO 0
10 BE UART Break Error:
This bit is set to 1 if a break condition was detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits).
In FIFO mode, this error is associated with the character at the top of the FIFO (i.e., the oldest received data character since last read). When a break occurs, a 0 character is loaded into the FIFO. The next character is enabled after the receive data input (UARTRXD input pin) goes to a 1 (marking state), and the next valid start bit is received.		 RO 0
9 PE UART Parity Error:
When set to 1, it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select.
In FIFO mode, this error is associated with the character at the top of the FIFO (i.e., the oldest received data character since last read).		 RO 0
8 FE UART Framing Error:
When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1).
In FIFO mode, this error is associated with the character at the top of the FIFO (i.e., the oldest received data character since last read).		 RO 0
7:0 DATA Data transmitted or received:
On writes, the transmit data character is pushed into the FIFO.
On reads, the oldest received data character since the last read is returned.		 RW 0x00

TOP:UART0:RSR_ECR

Address Offset 0x0000 0004
Physical Address 0x4003 4004 Instance 0x4003 4004
Description Status
This register is mapped to the same address as ECR register. Reads from this address are associated with RSR_ECR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors).
If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from the Data Register DR, prior to reading the RSR_ECR. The status information for overrun is set immediately when an overrun condition occurs.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Reads to this field return zero, writes to this field are ignored. RO 0x000 0000
3 OE UART Overrun Error:
This bit is set to 1 if data is received and the receive FIFO is already full. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten.
This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.
Value ENUM Name Description
0x0 ERROR_NOTSET Error flag is not set
0x1 CLEAR_ERROR_1 Clears error flag if error is set. Write value is not important.
RW 0
2 BE UART Break Error:
This bit is set to 1 if a break condition was detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits).
When a break occurs, a 0 character is loaded into the FIFO. The next character is enabled after the receive data input (UARTRXD input pin) goes to a 1 (marking state), and the next valid start bit is received.
Value ENUM Name Description
0x0 ERROR_NOTSET Error flag is not set
0x1 CLEAR_ERROR_1 Clears error flag if error is set. Write value is not important.
RW 0
1 PE UART Parity Error:
When set to 1, it indicates that the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select.
Value ENUM Name Description
0x0 ERROR_NOTSET Error flag is not set
0x1 CLEAR_ERROR_1 Clears error flag if error is set. Write value is not important.
RW 0
0 FE UART Framing Error:
When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1).
Value ENUM Name Description
0x0 ERROR_NOTSET Error flag is not set
0x1 CLEAR_ERROR_1 Clears error flag if error is set. Write value is not important.
RW 0

TOP:UART0:FR

Address Offset 0x0000 0018
Physical Address 0x4003 4018 Instance 0x4003 4018
Description Flag
Reads from this register return the UART flags.
Type RO
Bits Field Name Description Type Reset
31:8 RESERVED8 Reads to this field return zero, writes to this field are ignored. RO 0x00 0000
7 TXFE UART Transmit FIFO Empty:
The meaning of this bit depends on the state of LCRH.FEN .
- If the FIFO is disabled, this bit is set when the transmit holding register is empty.
- If the FIFO is enabled, this bit is set when the transmit FIFO is empty.
This bit does not indicate if there is data in the transmit shift register.		 RO 1
6 RXFF UART Receive FIFO Full:
The meaning of this bit depends on the state of LCRH.FEN.
- If the FIFO is disabled, this bit is set when the receive holding register is full.
- If the FIFO is enabled, this bit is set when the receive FIFO is full.		 RO 0
5 TXFF UART Transmit FIFO Full:
Transmit FIFO full. The meaning of this bit depends on the state of LCRH.FEN.
- If the FIFO is disabled, this bit is set when the transmit holding register is full.
- If the FIFO is enabled, this bit is set when the transmit FIFO is full.		 RO 0
4 RXFE UART Receive FIFO Empty:
Receive FIFO empty. The meaning of this bit depends on the state of LCRH.FEN.
- If the FIFO is disabled, this bit is set when the receive holding register is empty.
- If the FIFO is enabled, this bit is set when the receive FIFO is empty.		 RO 1
3 BUSY UART Busy:
If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.		 RO 0
2:1 RESERVED0 Reserved RO 0b00
0 CTS Clear To Send:
This bit is the complement of the active-low UART CTS input pin.
That is, the bit is 1 when CTS input pin is LOW.		 RO 1

TOP:UART0:UARTILPR

Address Offset 0x0000 0020
Physical Address 0x4003 4020 Instance 0x4003 4020
Description IrDA Low-Power Counter Register.

This is an 8-bit register that stores the low-power counter divisor value used to generate the IrLPBaud16 signal by dividing down of UARTCLK.
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Reads to this field return zero, writes to this field are ignored. RW 0x00 0000
7:0 ILPDVSR 8 bit low-power divisor value. In low-power IrDA mode the UART rejects random noise on the received serial data
input by ignoring SIRIN pulses that are less than 3 periods of IrLPBaud16.		 RW 0x00

TOP:UART0:IBRD

Address Offset 0x0000 0024
Physical Address 0x4003 4024 Instance 0x4003 4024
Description Integer Baud-Rate Divisor
If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Reads to this field return zero, writes to this field are ignored. RW 0x0000
15:0 DIVINT The integer baud rate divisor:
The baud rate divisor is calculated using the formula below:
Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)
Baud rate divisor must be minimum 1 and maximum 65535.
That is, DIVINT=0 does not give a valid baud rate.
Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be illegal.
Refer to Section 19.1.5 for an example calculation.
A valid value must be written to this field before the UART can be used for RX or TX operations.		 RW 0x0000

TOP:UART0:FBRD

Address Offset 0x0000 0028
Physical Address 0x4003 4028 Instance 0x4003 4028
Description Fractional Baud-Rate Divisor
If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete.
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Reads to this field return zero, writes to this field are ignored. RW 0b00 0000 0000 0000 0000 0000 0000
5:0 DIVFRAC Fractional Baud-Rate Divisor:
The baud rate divisor is calculated using the formula below:
Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)
Baud rate divisor must be minimum 1 and maximum 65535.
That is, IBRD.DIVINT=0 does not give a valid baud rate.
Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be illegal.
Refer to Section 19.1.5 for an example calculation.
A valid value must be written to this field before the UART can be used for RX or TX operations.		 RW 0b00 0000

TOP:UART0:LCRH

Address Offset 0x0000 002C
Physical Address 0x4003 402C Instance 0x4003 402C
Description Line Control
Type RW
Bits Field Name Description Type Reset
31:8 RESERVED8 Reads to this field return zero, writes to this field are ignored. RW 0x00 0000
7 SPS UART Stick Parity Select:

0: Stick parity is disabled
1: The parity bit is transmitted and checked as invert of EPS field (i.e. the parity bit is transmitted and checked as 1 when EPS = 0).

This bit has no effect when PEN disables parity checking and generation.		 RW 0
6:5 WLEN UART Word Length:
These bits indicate the number of data bits transmitted or received in a frame.
Value ENUM Name Description
0x0 BITL5 Word Length 5 bits
0x1 BITL6 Word Length 6 bits
0x2 BITL7 Word Length 7 bits
0x3 BITL8 Word Length 8 bits
RW 0b00
4 FEN UART Enable FIFOs
Value ENUM Name Description
0x0 DIS FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers.
0x1 EN Transmit and receive FIFO buffers are enabled (FIFO mode)
RW 0
3 STP2 UART Two Stop Bits Select:
If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.		 RW 0
2 EPS UART Even Parity Select
Value ENUM Name Description
0x0 ODD Odd parity: The UART generates or checks for an odd number of 1s in the data and parity bits.
0x1 EVEN Even parity: The UART generates or checks for an even number of 1s in the data and parity bits.
RW 0
1 PEN UART Parity Enable
This bit controls generation and checking of parity bit.
Value ENUM Name Description
0x0 DIS Parity is disabled and no parity bit is added to the data frame
0x1 EN Parity checking and generation is enabled.
RW 0
0 BRK UART Send Break
If this bit is set to 1, a low-level is continually output on the UARTTXD output pin, after completing transmission of the current character. For the proper execution of the break command, the
software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.		 RW 0

TOP:UART0:CTL

Address Offset 0x0000 0030
Physical Address 0x4003 4030 Instance 0x4003 4030
Description Control
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Reads to this field return zero, writes to this field are ignored. RO 0x0000
15 CTSEN CTS hardware flow control enable
Value ENUM Name Description
0x0 DIS CTS hardware flow control disabled
0x1 EN CTS hardware flow control enabled
RW 0
14 RTSEN RTS hardware flow control enable
Value ENUM Name Description
0x0 DIS RTS hardware flow control disabled
0x1 EN RTS hardware flow control enabled
RW 0
13:12 RESERVED12 Reads to this field return zero, writes to this field are ignored. RW 0b00
11 RTS Request to Send
This bit is the complement of the active-low UART RTS output. That is, when the bit is programmed to a 1 then RTS output on the pins is LOW.		 RW 0
10 RESERVED10 Reads to this field return zero, writes to this field are ignored. RW 0
9 RXE UART Receive Enable
If the UART is disabled in the middle of reception, it completes the current character before stopping.
Value ENUM Name Description
0x0 DIS UART Receive disabled
0x1 EN UART Receive enabled
RW 1
8 TXE UART Transmit Enable
If the UART is disabled in the middle of transmission, it completes the current character before stopping.
Value ENUM Name Description
0x0 DIS UART Transmit disabled
0x1 EN UART Transmit enabled
RW 1
7 LBE UART Loop Back Enable
Enabling the loop-back mode connects the UARTTXD output from the UART to UARTRXD input of the UART.
Value ENUM Name Description
0x0 DIS Loop Back disabled
0x1 EN Loop Back enabled
RW 0
6 FCEN UART FIFO Concatenation Enable
Enabling the FIFO concatenation in TX mode resulting in 16 TX buffers.
Value ENUM Name Description
0x0 DIS UART FIFO Concatenation disabled
0x1 EN UART FIFO Concatenation enabled
RW 0
5:3 RESERVED1 Reads to this field return zero, writes to this field are ignored. RW 0b000
2 SIRLP SIR low power IrDA mode
This bit selects the IrDA encoding mode
Value ENUM Name Description
0x0 DIS Low-level bits are transmitted as active high with a 3/16th period width,
0x1 EN Low-level bits are transmitted with a pulse width of 3 times the period of IrLPBaud16(which has a frequency of (UARTCLK frequency)/UARTILP.ILPDVSR), regardless of the selected bit rate.
In low-power IrDA mode the UART rejects random noise on the received serial data
input by ignoring SIRIN pulses that are less than 3 periods of IrLPBaud16.
RW 0
1 SIREN SIR Enable
This bit has no effect if UARTEN bit disables the UART.
Value ENUM Name Description
0x0 DIS IrDA SIR ENDEC is disabled
0x1 EN IrDA SIR ENDEC is enabled. Data is transmitted and received via nSIROUT and SIRIN.
RW 0
0 UARTEN UART Enable
Value ENUM Name Description
0x0 DIS UART disabled
0x1 EN UART enabled
RW 0

TOP:UART0:IFLS

Address Offset 0x0000 0034
Physical Address 0x4003 4034 Instance 0x4003 4034
Description Interrupt FIFO Level Select
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Reads to this field return zero, writes to this field are ignored. RW 0b00 0000 0000 0000 0000 0000 0000
5:3 RXSEL Receive interrupt FIFO level select:
This field sets the trigger points for the receive interrupt. Values 0b101-0b111 are reserved.
Value ENUM Name Description
0x1 QUARTER Receive FIFO becomes >= 1/4 full
0x2 HALF Receive FIFO becomes >= 1/2 full
0x3 THREEQU Receive FIFO becomes >= 3/4 full
RW 0b010
2:0 TXSEL Transmit interrupt FIFO level select:
This field sets the trigger points for the transmit interrupt. Values 0b101-0b111 are reserved.
Value ENUM Name Description
0x1 QUARTER Transmit FIFO becomes <= 1/4 full
0x2 HALF Transmit FIFO becomes <= 1/2 full
0x3 THREEQU Transmit FIFO becomes <= 3/4 full
RW 0b010

TOP:UART0:IMSC

Address Offset 0x0000 0038
Physical Address 0x4003 4038 Instance 0x4003 4038
Description Interrupt Mask Set/Clear
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Reads to this field return zero, writes to this field are ignored. RW 0b00 0000 0000 0000 0000
13 RXDMADONE RX DMA done interrupt mask. A read returns the current mask for UART's RXDMADONE interrupt. On a write of 1, the mask of the RXDMADONE interrupt is set which means the interrupt state will be reflected in MIS.RXDMADONE. A write of 0 clears the mask which means MIS.RXDMADONE will not reflect the interrupt. RW 0
12 TXDMADONE TX DMA done interrupt mask. A read returns the current mask for UART's TXDMADONE interrupt. On a write of 1, the mask of the TXDMADONE interrupt is set which means the interrupt state will be reflected in MIS.TXDMADONE. A write of 0 clears the mask which means MIS.TXDMADONE will not reflect the interrupt. RW 0
11 EOT End of Transmission interrupt mask. A read returns the current mask for UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set which means the interrupt state will be reflected in MIS.EOT. A write of 0 clears the mask which means MIS.EOT will not reflect the interrupt. RW 0
10 OE Overrun error interrupt mask. A read returns the current mask for UART's overrun error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.OE. A write of 0 clears the mask which means MIS.OE will not reflect the interrupt. RW 0
9 BE Break error interrupt mask. A read returns the current mask for UART's break error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.BE. A write of 0 clears the mask which means MIS.BE will not reflect the interrupt. RW 0
8 PE Parity error interrupt mask. A read returns the current mask for UART's parity error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.PE. A write of 0 clears the mask which means MIS.PE will not reflect the interrupt. RW 0
7 FE Framing error interrupt mask. A read returns the current mask for UART's framing error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.FE. A write of 0 clears the mask which means MIS.FE will not reflect the interrupt. RW 0
6 RT Receive timeout interrupt mask. A read returns the current mask for UART's receive timeout interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.RT. A write of 0 clears the mask which means this bitfield will not reflect the interrupt.
The raw interrupt for receive timeout RIS.RT cannot be set unless the mask is set (RT = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from MIS.RT and RIS.RT.		 RW 0
5 TX Transmit interrupt mask. A read returns the current mask for UART's transmit interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.TX. A write of 0 clears the mask which means MIS.TX will not reflect the interrupt. RW 0
4 RX Receive interrupt mask. A read returns the current mask for UART's receive interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.RX. A write of 0 clears the mask which means MIS.RX will not reflect the interrupt. RW 0
3:2 RESERVED2 Reads to this field return zero, writes to this field are ignored. RW 0b00
1 CTSM Clear to Send (CTS) modem interrupt mask. A read returns the current mask for UART's clear to send interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.CTSM. A write of 0 clears the mask which means MIS.CTSM will not reflect the interrupt. RW 0
0 RESERVED0 Reads to this field return zero, writes to this field are ignored. RW 0

TOP:UART0:RIS

Address Offset 0x0000 003C
Physical Address 0x4003 403C Instance 0x4003 403C
Description Raw Interrupt Status
Type RO
Bits Field Name Description Type Reset
31:14 RESERVED14 Reads to this field return zero, writes to this field are ignored. RO 0b00 0000 0000 0000 0000
13 RXDMADONE RX DMA done interrupt status:
This field returns the raw interrupt state of UART's RX DMA done interrupt. RX DMA done flag is set when you recieve RX DMA done status from dma module.		 RO 0
12 TXDMADONE TX DMA done interrupt status:
This field returns the raw interrupt state of UART's TX DMA done interrupt. TX DMA done flag is set when you recieve TX DMA done status from dma module.		 RO 0
11 EOT End of Transmission interrupt status:
This field returns the raw interrupt state of UART's end of transmission interrupt. End of transmission flag is set when all the Transmit data in the FIFO and on the TX Line is tranmitted.		 RO 0
10 OE Overrun error interrupt status:
This field returns the raw interrupt state of UART's overrun error interrupt. Overrun error occurs if data is received and the receive FIFO is full.		 RO 0
9 BE Break error interrupt status:
This field returns the raw interrupt state of UART's break error interrupt. Break error is set when a break condition is detected, indicating that the received data input (UARTRXD input pin) was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits).		 RO 0
8 PE Parity error interrupt status:
This field returns the raw interrupt state of UART's parity error interrupt. Parity error is set if the parity of the received data character does not match the parity that the LCRH.EPS and LCRH.SPS select.		 RO 0
7 FE Framing error interrupt status:
This field returns the raw interrupt state of UART's framing error interrupt. Framing error is set if the received character does not have a valid stop bit (a valid stop bit is 1).		 RO 0
6 RT Receive timeout interrupt status:
This field returns the raw interrupt state of UART's receive timeout interrupt. The receive timeout interrupt is asserted when the receive FIFO is not empty, and no more data is received during a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data, or when a 1 is written to ICR.RT.
The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RT = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from MIS.RT and RT.		 RO 0
5 TX Transmit interrupt status:
This field returns the raw interrupt state of UART's transmit interrupt.
When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if the number of bytes in transmit FIFO is equal to or lower than the programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the trigger level, or by clearing the interrupt through ICR.TX.
When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one location, the transmit interrupt is asserted if there is no data present in the transmitters single location. It is cleared by performing a single write to the transmit FIFO, or by clearing the interrupt through ICR.TX.		 RO 0
4 RX Receive interrupt status:
This field returns the raw interrupt state of UART's receive interrupt.
When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if the receive FIFO reaches the programmed trigger
level (IFLS.RXSEL). The receive interrupt is cleared by reading data from the receive FIFO until it becomes less than the trigger level, or by clearing the interrupt through ICR.RX.
When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one location, the receive interrupt is asserted if data is received
thereby filling the location. The receive interrupt is cleared by performing a single read of the receive FIFO, or by clearing the interrupt through ICR.RX.		 RO 0
3:2 RESERVED2 Reads to this field return zero, writes to this field are ignored. RO 0b11
1 CTSM Clear to Send (CTS) modem interrupt status:
This field returns the raw interrupt state of UART's clear to send interrupt.		 RO 0
0 RESERVED0 Reads to this field return zero, writes to this field are ignored. RO 1

TOP:UART0:MIS

Address Offset 0x0000 0040
Physical Address 0x4003 4040 Instance 0x4003 4040
Description Masked Interrupt Status
Type RO
Bits Field Name Description Type Reset
31:14 RESERVED14 Reads to this field return zero, writes to this field are ignored. Read as zero, do not modify RO 0b00 0000 0000 0000 0000
13 RXDMADONE RX DMA done interrupt status:
This field returns the masked interrupt state of the RX DMA done interrupt which is the bitiwse AND product of raw interrupt state RIS.RXDMADONE and the mask setting IMSC.RXDMADONE.		 RO 0
12 TXDMADONE TX DMA done interrupt status:
This field returns the masked interrupt state of the TX DMA done interrupt which is the bitwise AND product of raw interrupt state RIS.TXDMADONE and the mask setting IMSC.TXDMADONE.		 RO 0
11 EOT End of Transmission interrupt status:
This field returns the masked interrupt state of the End of transmission interrupt which is the bitwise AND product of raw interrupt state RIS.EOT and the mask setting IMSC.EOT.		 RO 0
10 OE Overrun error masked interrupt status:
This field returns the masked interrupt state of the overrun interrupt which is the bitwise AND product of raw interrupt state RIS.OE and the mask setting IMSC.OE.		 RO 0
9 BE Break error masked interrupt status:
This field returns the masked interrupt state of the break error interrupt which is the bitiwse AND product of raw interrupt state RIS.BE and the mask setting IMSC.BE.		 RO 0
8 PE Parity error masked interrupt status:
This field returns the masked interrupt state of the parity error interrupt which is the bitiwise AND product of raw interrupt state RIS.PE and the mask setting IMSC.PE.		 RO 0
7 FE Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the bitiwse AND product of raw interrupt state RIS.FE and the mask setting IMSC.FE. RO 0
6 RT Receive timeout masked interrupt status:
Returns the masked interrupt state of the receive timeout interrupt.
The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RT = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from MIS.RT and RIS.RT.		 RO 0
5 TX Transmit masked interrupt status:
This field returns the masked interrupt state of the transmit interrupt which is the bitiwse AND product of raw interrupt state RIS.TX and the mask setting IMSC.TX.		 RO 0
4 RX Receive masked interrupt status:
This field returns the masked interrupt state of the receive interrupt which is the bitwise AND product of raw interrupt state RIS.RX and the mask setting IMSC.RX.		 RO 0
3:2 RESERVED2 Reads to this field return zero, writes to this field are ignored. RO 0b00
1 CTSM Clear to Send (CTS) modem masked interrupt status:
This field returns the masked interrupt state of the clear to send interrupt which is the bitwise AND product of raw interrupt state RIS.CTS and the mask setting IMSC.CTS.		 RO 0
0 RESERVED0 Reads to this field return zero, writes to this field are ignored. Write 0. RO 0

TOP:UART0:ICR

Address Offset 0x0000 0044
Physical Address 0x4003 4044 Instance 0x4003 4044
Description Interrupt Clear
On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
Type WO
Bits Field Name Description Type Reset
31:14 RESERVED16 Reads to this field return zero, writes to this field are ignored. Read as zero, do not modify WO 0b00 0000 0000 0000 0000
13 RXDMADONE RX DMA Done interrupt clear:
Writing 1 to this field clears the RX DMA done interrupt (RIS.RXDMADONE). Writing 0 has no effect.		 WO 0
12 TXDMADONE TX DMA Done interrupt clear:
Writing 1 to this field clears the TX DMA done interrupt (RIS.TXDMADONE). Writing 0 has no effect.		 WO 0
11 EOT End of Transmission interrupt clear:
Writing 1 to this field clears the End of Transmission interrupt (RIS.EOT). Writing 0 has no effect.		 WO 0
10 OE Overrun error interrupt clear:
Writing 1 to this field clears the overrun error interrupt (RIS.OE). Writing 0 has no effect.		 WO 0
9 BE Break error interrupt clear:
Writing 1 to this field clears the break error interrupt (RIS.BE). Writing 0 has no effect.		 WO 0
8 PE Parity error interrupt clear:
Writing 1 to this field clears the parity error interrupt (RIS.PE). Writing 0 has no effect.		 WO 0
7 FE Framing error interrupt clear:
Writing 1 to this field clears the framing error interrupt (RIS.FE). Writing 0 has no effect.		 WO 0
6 RT Receive timeout interrupt clear:
Writing 1 to this field clears the receive timeout interrupt (RIS.RT). Writing 0 has no effect.		 WO 0
5 TX Transmit interrupt clear:
Writing 1 to this field clears the transmit interrupt (RIS.TX). Writing 0 has no effect.		 WO 0
4 RX Receive interrupt clear:
Writing 1 to this field clears the receive interrupt (RIS.RX). Writing 0 has no effect.		 WO 0
3:2 RESERVED2 Reads to this field return zero, writes to this field are ignored. Write 0 WO 0b00
1 CTSM Clear to Send (CTS) modem interrupt clear:
Writing 1 to this field clears the clear to send interrupt (RIS.CTS). Writing 0 has no effect.		 WO 0
0 RESERVED0 Reads to this field return zero, writes to this field are ignored. Write 0. WO 0

TOP:UART0:DMACTL

Address Offset 0x0000 0048
Physical Address 0x4003 4048 Instance 0x4003 4048
Description DMA Control
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Reads to this field return zero, writes to this field are ignored. Read as zero, do not modify. RW 0b0 0000 0000 0000 0000 0000 0000 0000
2 DMAONERR DMA on error. If this bit is set to 1, the DMA receive request outputs (for single and burst requests) are disabled when the UART error interrupt is asserted (more specifically if any of the error interrupts RIS.PERIS, RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). RW 0
1 TXDMAE Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. RW 0
0 RXDMAE Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. RW 0


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