I2C0

Instance: I2C0
Component: I2C
Base address: 0x40038000

I2C IP module with peripheral and controller capabilities

TOP:I2C0 Register Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset	Physical Address
TOAR	RW	32	0x0000 0000	0x0000 0000	0x4003 8000
TSTA	RO	32	0x0000 0000	0x0000 0004	0x4003 8004
TCTL	WO	32	0x0000 0000	0x0000 0004	0x4003 8004
TDR	RW	32	0x0000 0000	0x0000 0008	0x4003 8008
TIMR	RW	32	0x0000 0000	0x0000 000C	0x4003 800C
TRIS	RO	32	0x0000 0000	0x0000 0010	0x4003 8010
TMIS	RO	32	0x0000 0000	0x0000 0014	0x4003 8014
TICR	RW	32	0x0000 0000	0x0000 0018	0x4003 8018
CTA	RW	32	0x0000 0000	0x0000 0800	0x4003 8800
CSTA	RO	32	0x0000 0020	0x0000 0804	0x4003 8804
CCTL	WO	32	0x0000 0000	0x0000 0804	0x4003 8804
CDR	RW	32	0x0000 0000	0x0000 0808	0x4003 8808
CTPR	RW	32	0x0000 0001	0x0000 080C	0x4003 880C
CIMR	RW	32	0x0000 0000	0x0000 0810	0x4003 8810
CRIS	RO	32	0x0000 0000	0x0000 0814	0x4003 8814
CMIS	RO	32	0x0000 0000	0x0000 0818	0x4003 8818
CICR	RW	32	0x0000 0000	0x0000 081C	0x4003 881C
CCR	RW	32	0x0000 0000	0x0000 0820	0x4003 8820

TOP:I2C0 Register Descriptions

TOP:I2C0:TOAR

Address Offset	0x0000 0000
Physical Address	0x4003 8000	Instance	0x4003 8000
Description	Target Own Address This register consists of seven address bits that identify this I2C device on the I2C bus.
Type	RW

Bits	Field Name	Description	Type	Reset
31:7	RESERVED7	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b0 0000 0000 0000 0000 0000 0000
6:0	OAR	Target own address. This field specifies bits a6 through a0 of the target address.	RW	0b000 0000

TOP:I2C0:TSTA

Address Offset	0x0000 0004
Physical Address	0x4003 8004	Instance	0x4003 8004
Description	Target status This register functions as a status register of the target.
Type	RO

Bits

Field Name

Description

Type

Reset

31:3

RESERVED3

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b0 0000 0000 0000 0000 0000 0000 0000

FBR

First byte received.
This bit is only applicable when the TSTA.RREQ bit is set and is automatically cleared when data has been read from the TDR register.
Note: This bit is not used for target transmit operations.

Value	ENUM Name	Description
0x0	CLR	The first byte following the target's own address has not been received
0x1	SET	The first byte following the target's own address has been received.

TREQ

This field reflects the transmit request status

Value	ENUM Name	Description
0x0	CLR	No outstanding transmit request
0x1	SET	The I2C has been addressed as a target transmitter and is using clock stretching to delay the controller until data has been written to the TDR register

RREQ

This field reflects the receive request status.

Value	ENUM Name	Description
0x0	CLR	No outstanding receive data
0x1	SET	The target has outstanding receive data from the external controller and is using clock stretching to delay the controller until data has been read from the TDR register

TOP:I2C0:TCTL

Address Offset	0x0000 0004
Physical Address	0x4003 8004	Instance	0x4003 8004
Description	Target control This registers functions as a target control register
Type	WO

Bits

Field Name

Description

Type

Reset

31:1

RESERVED1

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b000 0000 0000 0000 0000 0000 0000 0000

This field sets the device active control

Value	ENUM Name	Description
0x0	DIS	Disable the target operation
0x1	EN	Enable the target operation

TOP:I2C0:TDR

Address Offset	0x0000 0008
Physical Address	0x4003 8008	Instance	0x4003 8008
Description	Target data register This register contains the data to be transmitted when in the target transmit state, and the data received when in the target receive state.
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	RESERVED8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x00 0000
7:0	DATA	Data for transfer. This field contains the data for transfer during a target receive or a transmit operation. When written, the register data is used as transmit data. When read, this register returns the last data received. Data is stored until next update, either by a system write to the controller for transmit or by an external controller to the target for receive.	RW	0x00

TOP:I2C0:TIMR

Address Offset	0x0000 000C
Physical Address	0x4003 800C	Instance	0x4003 800C
Description	Target interrupt mask This register controls whether a raw interrupt is promoted to a controller interrupt
Type	RW

Bits

Field Name

Description

Type

Reset

31:3

RESERVED3

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b0 0000 0000 0000 0000 0000 0000 0000

STOPIM

Stop condition interrupt mask

Value	ENUM Name	Description
0x0	DIS	Disable interrupt mask
0x1	EN	Enable interrupt mask

STARTIM

Start condition interrupt mask

Value	ENUM Name	Description
0x0	DIS	Disable interrupt mask
0x1	EN	Enable interrupt mask

DATAIM

Data interrupt mask

Value	ENUM Name	Description
0x0	DIS	Disable interrupt mask
0x1	EN	Enable interrupt mask

TOP:I2C0:TRIS

Address Offset	0x0000 0010
Physical Address	0x4003 8010	Instance	0x4003 8010
Description	Target raw interrupt status This register shows the unmasked interrupt status.
Type	RO

Bits

Field Name

Description

Type

Reset

31:3

RESERVED3

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b0 0000 0000 0000 0000 0000 0000 0000

STOPRIS

Stop condition raw interrupt status
This bit is cleared by writing a 1 to TICR.STOPIC.

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

STARTRIS

Start condition raw interrupt status
This bit is cleared by writing a 1 to TICR.STARTIC.

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

DATARIS

Data raw interrupt status
This bit is cleared by writing a 1 to TICR.DATAIC.

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

TOP:I2C0:TMIS

Address Offset	0x0000 0014
Physical Address	0x4003 8014	Instance	0x4003 8014
Description	Target Masked Interrupt Status This register shows which interrupt is active (based on result from TRIS and TIMR registers).
Type	RO

Bits

Field Name

Description

Type

Reset

31:3

RESERVED3

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b0 0000 0000 0000 0000 0000 0000 0000

STOPMIS

Stop condition masked interrupt status
This bit is cleared by writing a 1 to TICR.STOPIC.

Value	ENUM Name	Description
0x0	CLR	Masked interrupt did not occur
0x1	SET	Masked interrupt occured

STARTMIS

Start condition masked interrupt status
This bit is cleared by writing a 1 to TICR.STARTIC.

Value	ENUM Name	Description
0x0	CLR	Masked interrupt did not occur
0x1	SET	Masked interrput occured

DATAMIS

Start condition masked interrupt status
This bit is cleared by writing a 1 to TICR.DATAIC.

Value	ENUM Name	Description
0x0	CLR	Masked interrupt did not occur
0x1	SET	Masked interrupt occured

TOP:I2C0:TICR

Address Offset	0x0000 0018
Physical Address	0x4003 8018	Instance	0x4003 8018
Description	Target Interrupt Clear This register clears the raw interrupt TRIS
Type	RW

Bits

Field Name

Description

Type

Reset

31:3

RESERVED3

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b0 0000 0000 0000 0000 0000 0000 0000

STOPIC

Stop condition interrupt clear

Value	ENUM Name	Description
0x0	DIS	No effect
0x1	EN	Clear interrupt Writing 1 to this bit clears TRIS.STOPRIS and TMIS.STOPMIS

STARTIC

Start condition interrupt clear

Value	ENUM Name	Description
0x0	DIS	No effect
0x1	EN	Clear interrupt Writing 1 to this bit clears TRIS.STARTRIS and TMIS.STARTMIS

DATAIC

Data interrupt clear

Value	ENUM Name	Description
0x0	DIS	No effect
0x1	EN	Clear interrupt Writing 1 to this bit clears TRIS.DATARIS and TMIS.DATAMIS

TOP:I2C0:CTA

Address Offset	0x0000 0800
Physical Address	0x4003 8800	Instance	0x4003 8800
Description	Controller target address This register contains seven address bits of the target to be accessed by the controller (a6-a0), and an CTA.RS bit determining if the next operation is a receive or transmit
Type	RW

Bits

Field Name

Description

Type

Reset

31:8

RESERVED8

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0x00 0000

7:1

Controller target address
Defines which target is addressed for the transaction in controller mode

0b000 0000

Receive or Send
This bit-field specifies the next operation with addressed target CTA.SA.

Value	ENUM Name	Description
0x0	DIS	Transmit/send data to target
0x1	EN	Receive data from target

TOP:I2C0:CSTA

Address Offset	0x0000 0804
Physical Address	0x4003 8804	Instance	0x4003 8804
Description	Controller status This register functions as a controller status register
Type	RO

Bits

Field Name

Description

Type

Reset

31:7

RESERVED7

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b0 0000 0000 0000 0000 0000 0000

BUSBSY

Bus busy
Note:The bit changes based on the CCTRL.START and CCTRL.STOP conditions.

Value	ENUM Name	Description
0x0	CLR	The bus is idle.
0x1	SET	The bus is busy.

IDLE

This field specifies whether I2C is idle or not

Value	ENUM Name	Description
0x0	CLR	The controller is not idle.
0x1	SET	The controller is idle.

ARBLST

The filed specifies the arbitration status

Value	ENUM Name	Description
0x0	CLR	The controller won arbitration.
0x1	SET	The controller lost arbitration.

DATACKN

This field contains Data acknowledge status

Value	ENUM Name	Description
0x0	CLR	The transmitted data was acknowledged
0x1	SET	The transmitted data was not acknowledged

ADRACKN

This field reflects the address acknowledge status

Value	ENUM Name	Description
0x0	CLR	The transmitted address was acknowledged
0x1	SET	The transmitted address was not acknowledged

ERR

This field reflects the error status

Value	ENUM Name	Description
0x0	CLR	No error was detected on the last operation
0x1	SET	An error occurred with the last operation

BUSY

This field reflects the I2C busy status
Note: The I2C controller requires four CLKSVT clock cycles to assert the BUSY status after I2C controller operation has been initiated through a write into CCTL register.
Hence after programming CCTL register, application is requested to wait for four CLKSVT clock cycles before issuing a controller status inquiry through a read from CSTA register. Any prior inquiry would result in wrong status being reported.

Value	ENUM Name	Description
0x0	CLR	The controller is idle
0x1	SET	The controller is busy

TOP:I2C0:CCTL

Address Offset	0x0000 0804
Physical Address	0x4003 8804	Instance	0x4003 8804
Description	Controller control This register functions as a controller control register
Type	WO

Bits

Field Name

Description

Type

Reset

31:4

RESERVED4

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0x000 0000

ACK

This field is to enable the data acknowledge.
Note:This bit-field must be cleared when the I2C bus controller requires no further data to be transmitted from the target transmitter.

Value	ENUM Name	Description
0x0	DIS	The received data byte is not acknowledged automatically by the controller
0x1	EN	The received data byte is acknowledged automatically by the controller

STOP

This field is to set stop condition .
Note: This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated start condition.

Value	ENUM Name	Description
0x0	DIS	The controller does not generate the stop condition
0x1	EN	The controller generates the stop condition

START

This field is to set start or repeated start condition.

Value	ENUM Name	Description
0x0	DIS	The controller does not generate the start condition
0x1	EN	The controller generates the start condition.

RUN

This field is to set the controller enable.

Value	ENUM Name	Description
0x0	DIS	The controller is disabled.
0x1	EN	The controller is enabled to transmit or receive data

TOP:I2C0:CDR

Address Offset	0x0000 0808
Physical Address	0x4003 8808	Instance	0x4003 8808
Description	Controller data This register contains the data to be transmitted when in the controller transmit state and the data received when in the controller receive state.
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	RESERVED8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x00 0000
7:0	DATA	When Read: Last RX Data is returned When Written: Data is transferred during TX transaction	RW	0x00

TOP:I2C0:CTPR

Address Offset	0x0000 080C
Physical Address	0x4003 880C	Instance	0x4003 880C
Description	Controller timer period This register specifies the period of the SCL clock.
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	RESERVED8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x00 0000
7	TPR_7	Must be set to 0 to set CTPR.TPR. If set to 1, a write to CTPR.TPR will be ignored.	RW	0
6:0	TPR	SCL clock period This field specifies the period of the SCL clock. SCL_PRD = 2(1+TPR)(SCL_LP + SCL_HP)*CLK_PRD, where: SCL_PRD is the SCL line period (I2C clock). TPR is the timer period register value (range of 1 to 127) SCL_LP is the SCL low period (fixed at 6). SCL_HP is the SCL high period (fixed at 4). CLK_PRD is the CLKSVT period in ns.	RW	0b000 0001

TOP:I2C0:CIMR

Address Offset	0x0000 0810
Physical Address	0x4003 8810	Instance	0x4003 8810
Description	Controller interrupt mask This register controls whether a raw interrupt is promoted to a controller interrupt.
Type	RW

Bits

Field Name

Description

Type

Reset

31:1

RESERVED1

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b000 0000 0000 0000 0000 0000 0000 0000

Interrupt mask

Value	ENUM Name	Description
0x0	DIS	Disable interrupt mask
0x1	EN	Enable interrupt mask

TOP:I2C0:CRIS

Address Offset	0x0000 0814
Physical Address	0x4003 8814	Instance	0x4003 8814
Description	Controller raw interrupt status This register shows the unmasked interrupt status.
Type	RO

Bits

Field Name

Description

Type

Reset

31:1

RESERVED1

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b000 0000 0000 0000 0000 0000 0000 0000

RIS

Raw interrupt status
This bit is cleared by writing 1 to CICR.IC bit.

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

TOP:I2C0:CMIS

Address Offset	0x0000 0818
Physical Address	0x4003 8818	Instance	0x4003 8818
Description	Controller masked interrupt status This register shows which interrupt is active (based on result from CRIS and CIMR registers).
Type	RO

Bits

Field Name

Description

Type

Reset

31:1

RESERVED1

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b000 0000 0000 0000 0000 0000 0000 0000

MIS

Masked interrupt status
This bit is cleared by writing 1 to CICR.IC bit.

Value	ENUM Name	Description
0x0	CLR	Masked interrupt did not occur
0x1	SET	Masked interrupt occured

TOP:I2C0:CICR

Address Offset	0x0000 081C
Physical Address	0x4003 881C	Instance	0x4003 881C
Description	Controller interrupt clear This register clears the raw and masked interrupt.
Type	RW

Bits

Field Name

Description

Type

Reset

31:1

RESERVED1

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b000 0000 0000 0000 0000 0000 0000 0000

Interrupt clear

Value	ENUM Name	Description
0x0	DIS	No effect
0x1	EN	Clear Interrupt Writing 1 to this bit clears CRIS.RIS and CMIS.MIS.

TOP:I2C0:CCR

Address Offset	0x0000 0820
Physical Address	0x4003 8820	Instance	0x4003 8820
Description	Controller Configuration This register configures the mode (Controller or Target) and sets the interface for test mode loopback.
Type	RW

Bits

Field Name

Description

Type

Reset

31:6

RESERVED6

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000

TFE

I2C target function enable

Value	ENUM Name	Description
0x0	DIS	Target mode disabled
0x1	EN	Target mode enabled

CFE

I2C controller function enable

Value	ENUM Name	Description
0x0	DIS	Controller mode disabled
0x1	EN	Controller mode enabled

3:1

RESERVED1

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b000

LPBK

I2C loopback

Value	ENUM Name	Description
0x0	DIS	Test mode (Loopback operation) disabled
0x1	EN	Test mode (Loopback operation) enabled