RTC

Instance: RTC
Component: RTC
Base address: 0x40002000

ULL Real Time Clock module
RTC includes 2 channels.
- Channel 0 is a compare channel
- Channel 1 is a capture channel

TOP:RTC Register Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset	Physical Address
DESC	RO	32	0x6442 1010	0x0000 0000	0x4000 2000
CTL	RW	32	0x0000 0000	0x0000 0004	0x4000 2004
ARMSET	RW	32	0x0000 0000	0x0000 0008	0x4000 2008
ARMCLR	RW	32	0x0000 0000	0x0000 000C	0x4000 200C
TIME8U	RO	32	0x0000 0000	0x0000 0018	0x4000 2018
TIME524M	RO	32	0x0000 0000	0x0000 001C	0x4000 201C
CH0CC8U	RW	32	0x0000 0000	0x0000 0028	0x4000 2028
CH1CC8U	RO	32	0x0000 0000	0x0000 0038	0x4000 2038
CH1CFG	RW	32	0x0000 0000	0x0000 003C	0x4000 203C
IMASK	RW	32	0x0000 0000	0x0000 0044	0x4000 2044
RIS	RO	32	0x0000 0000	0x0000 0048	0x4000 2048
MIS	RO	32	0x0000 0000	0x0000 004C	0x4000 204C
ISET	WO	32	0x0000 0000	0x0000 0050	0x4000 2050
ICLR	WO	32	0x0000 0000	0x0000 0054	0x4000 2054
IMSET	WO	32	0x0000 0000	0x0000 0058	0x4000 2058
IMCLR	WO	32	0x0000 0000	0x0000 005C	0x4000 205C
EMU	RW	32	0x0000 0000	0x0000 0060	0x4000 2060

TOP:RTC Register Descriptions

TOP:RTC:DESC

Address Offset	0x0000 0000
Physical Address	0x4000 2000	Instance	0x4000 2000
Description	Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	MODID	Module identifier used to uniquely identify this IP.	RW	0x6442
15:12	STDIPOFF	Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)	RW	0x1
11:8	INSTIDX	IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).	RW	0x0
7:4	MAJREV	Major revision of IP (0-15).	RW	0x1
3:0	MINREV	Minor revision of IP (0-15).	RW	0x0

TOP:RTC:CTL

Address Offset	0x0000 0004
Physical Address	0x4000 2004	Instance	0x4000 2004
Description	RTC Control register. This register controls resetting the of RTC counter
Type	RW

Bits

Field Name

Description

Type

Reset

31:1

RESERVED1

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b000 0000 0000 0000 0000 0000 0000 0000

RST

RTC counter reset. Writing 1 to this bit will reset the RTC counter, and cause it to resume counting from 0x0

Value	ENUM Name	Description
0x0	NOEFF	No effect
0x1	CLR	Reset the timer.

TOP:RTC:ARMSET

Address Offset	0x0000 0008
Physical Address	0x4000 2008	Instance	0x4000 2008
Description	RTC channel mode set register. Read to each bit field of this register provides the current channel mode. - Read of 1'b0 indicates the channel is unarmed. - Read of 1'b1 indicates the channel is either in capture or compare mode. A write to each bitfield of this register the following effect: - Write of 1'b0 has no effect on channel mode. - Write of 1'b1 has no effect on the compare channel. While write of 1'b1 for capture channel will arm it in capture mode if it is disabled.
Type	RW

Bits

Field Name

Description

Type

Reset

31:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000 0000

CH1

Arming Channel 1 for capture operation.

Value	ENUM Name	Description
0x0	NOEFF	No effect on the channel
0x1	SET	Enable the Channel 1 for capture operation

CH0

No effect on arming the channel. Read will give the status of the Channel 0.

Value	ENUM Name	Description
0x0	NOEFF	No effect on the channel
0x1	SET	No effect on the compare channel

TOP:RTC:ARMCLR

Address Offset	0x0000 000C
Physical Address	0x4000 200C	Instance	0x4000 200C
Description	RTC channel mode clear register. Read to each bit field of this register provides the current channel mode. - Read of 1'b0 indicates the channel is unarmed. - Read of 1'b1 indicates the channel is either in capture or compare mode. A write to each bitfield of this register the following effect: - Write of 1'b0 has no effect on channel mode. - Write of 1'b1 for capture/compare channel will disarm it without triggering event unless a compare/capture event happens in the same cycle.
Type	RW

Bits

Field Name

Description

Type

Reset

31:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000 0000

CH1

Disarming Channel 1

Value	ENUM Name	Description
0x0	NOEFF	No effect on the channel
0x1	CLR	Set channel in UNARMED state without triggering event unless a capture event happens in the same cycle

CH0

Disarming Channel 0

Value	ENUM Name	Description
0x0	NOEFF	No effect on the channel
0x1	CLR	Set channel in UNARMED state without triggering event unless a compare event happens in the same cycle

TOP:RTC:TIME8U

Address Offset	0x0000 0018
Physical Address	0x4000 2018	Instance	0x4000 2018
Description	RTC Time value register. 32-bit unsigned integer representing [34:3] time slice of the real time clock counter. The counter runs on LFCLK. This field has a resolution of 8us, and range of about 9.5 hours.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	VAL	Unsigned integer representing [34:3]slice of real time counter.			RO	0x0000 0000

TOP:RTC:TIME524M

Address Offset	0x0000 001C
Physical Address	0x4000 201C	Instance	0x4000 201C
Description	RTC time value register. 32-bit unsigned integer representing [50:19] time slice of the real time clock counter. This field has a resolution of about 0.5s and a range of about 71.4 years.
Type	RO

Bits	Field Name	Description			Type	Reset
31:0	VAL	Unsigned integer representing. [50:19]slice of real time counter.			RO	0x0000 0000

TOP:RTC:CH0CC8U

Address Offset	0x0000 0028
Physical Address	0x4000 2028	Instance	0x4000 2028
Description	Channel 0 compare value. A write to this register automatically enables the channel to trigger an event when RTC timer reaches the programmed value or if the programmed value is 1 sec in the past.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	RTC Channel 0 compare value. This value is compared against TIME8U.VAL. A Channel 0 event is generated when TIME8U.VAL value reaches or exceeds this compare value.			RW	0x0000 0000

TOP:RTC:CH1CC8U

Address Offset	0x0000 0038
Physical Address	0x4000 2038	Instance	0x4000 2038
Description	Channel 1 capture value. This register captures the RTC time slice [34:3] on each selected edge of the capture event when the ARMSET.CH1 = 1.
Type	RO

Bits	Field Name	Description	Type	Reset
31:21	RESERVED21	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b000 0000 0000
20:0	VAL	TIME8U.VAL captured value at the last selected edge of capture event.	RO	0b0 0000 0000 0000 0000 0000

TOP:RTC:CH1CFG

Address Offset	0x0000 003C
Physical Address	0x4000 203C	Instance	0x4000 203C
Description	Channel 1 configuration register. This register can be used to select the capture edge for generating the capture event.
Type	RW

Bits

Field Name

Description

Type

Reset

31:1

RESERVED1

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b000 0000 0000 0000 0000 0000 0000 0000

EDGE

Edge detect configuration for capture source

Value	ENUM Name	Description
0x0	RISE	Rising Edge.
0x1	FALL	Falling Edge.

TOP:RTC:IMASK

Address Offset	0x0000 0044
Physical Address	0x4000 2044	Instance	0x4000 2044
Description	Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
Type	RW

Bits

Field Name

Description

Type

Reset

31:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000 0000

EV1

Channel 1 Event Interrupt Mask.

Value	ENUM Name	Description
0x0	DIS	Clear Interrupt Mask
0x1	EN	Enable Interrrupt Mask

EV0

Channel 0 Event Interrupt Mask.

Value	ENUM Name	Description
0x0	DIS	Disable Interrupt Mask
0x1	EN	Enable Interrrupt Mask

TOP:RTC:RIS

Address Offset	0x0000 0048
Physical Address	0x4000 2048	Instance	0x4000 2048
Description	Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.
Type	RO

Bits

Field Name

Description

Type

Reset

31:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000 0000

EV1

Raw interrupt status for Channel 1 event.
This bit is set to 1 when a capture event is received on Channel 1.
This bit will be cleared when the bit in ICLR.EV1 is set to 1 or when the captured time value is read from the CH1CC8U register.

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

EV0

Raw interrupt status for Channel 0 event.
This bit is set to 1 when a compare event occurs on Channel 0.
This bit will be cleared. When the corresponding bit in ICLR.EV0 is set to 1. Or when a new compare value is written in CH0CC8U register

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

TOP:RTC:MIS

Address Offset	0x0000 004C
Physical Address	0x4000 204C	Instance	0x4000 204C
Description	Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.
Type	RO

Bits

Field Name

Description

Type

Reset

31:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000 0000

EV1

Masked interrupt status for channel 1 event.

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

EV0

Masked interrupt status for channel 0 event.

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

TOP:RTC:ISET

Address Offset	0x0000 0050
Physical Address	0x4000 2050	Instance	0x4000 2050
Description	Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.
Type	WO

Bits

Field Name

Description

Type

Reset

31:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000 0000

EV1

Set Channel 1 event Interrupt.

Value	ENUM Name	Description
0x0	NO_EFFECT	Writing 0 has no effect
0x1	SET	Set interrupt

EV0

Set Channel 0 event Interrupt.

Value	ENUM Name	Description
0x0	NO_EFFECT	Writing 0 has no effect
0x1	SET	Set interrupt

TOP:RTC:ICLR

Address Offset	0x0000 0054
Physical Address	0x4000 2054	Instance	0x4000 2054
Description	Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.
Type	WO

Bits

Field Name

Description

Type

Reset

31:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000 0000

EV1

Clears channel 1 event interrupt.

Value	ENUM Name	Description
0x0	NO_EFF	Writing 0 has no effect
0x1	CLR	Clear Interrupt

EV0

Clears channel 0 event interrupt.

Value	ENUM Name	Description
0x0	NO_EFF	Writing 0 has no effect
0x1	CLR	Clear Interrupt.

TOP:RTC:IMSET

Address Offset	0x0000 0058
Physical Address	0x4000 2058	Instance	0x4000 2058
Description	Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding IMASK bit.
Type	WO

Bits

Field Name

Description

Type

Reset

31:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000 0000

EV1

Set channel 1 event interrupt mask.

Value	ENUM Name	Description
0x0	NO_EFF	Writing 0 has no effect
0x1	SET	Set interrupt mask

EV0

Set channel 0 event interrupt mask.

Value	ENUM Name	Description
0x0	NO_EFF	Writing 0 has no effect
0x1	SET	Set interrupt mask

TOP:RTC:IMCLR

Address Offset	0x0000 005C
Physical Address	0x4000 205C	Instance	0x4000 205C
Description	Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding IMASK bit.
Type	WO

Bits

Field Name

Description

Type

Reset

31:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000 0000

EV1

Clears Channel 1 event interrupt mask.

Value	ENUM Name	Description
0x0	NO_EFF	Writing 0 has no effect
0x1	CLR	Clear Interrupt Mask

EV0

Clears Channel 0 event interrupt mask.

Value	ENUM Name	Description
0x0	NO_EFF	Writing 0 has no effect
0x1	CLR	Clear Interrupt Mask

TOP:RTC:EMU

Address Offset	0x0000 0060
Physical Address	0x4000 2060	Instance	0x4000 2060
Description	Emulation control register. This register controls the behavior of the IP related to core halted input.
Type	RW

Bits

Field Name

Description

Type

Reset

31:1

RESERVED1

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b000 0000 0000 0000 0000 0000 0000 0000

HALT

Halt control.

Value	ENUM Name	Description
0x0	RUN	Free run option. The IP ignores the state of the core halted input.
0x1	STOP	Freeze option. The IP freezes functionality when the core halted input is asserted, and resumes when it is deasserted. The freeze can either be immediate or after the IP has reached a boundary from where it can resume without corruption.