ADC

Instance: ADC
Component: ADC
Base address: 0x40050000


ADC (Analog to Digital Converter) module

TOP:ADC Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

IMASK0

RW

32

0x0000 0000

0x0000 0028

0x4005 0028

RIS0

RO

32

0x0000 0000

0x0000 0030

0x4005 0030

MIS0

RO

32

0x0000 0000

0x0000 0038

0x4005 0038

ISET0

WO

32

0x0000 0000

0x0000 0040

0x4005 0040

ICLR0

WO

32

0x0000 0000

0x0000 0048

0x4005 0048

IMASK1

RW

32

0x0000 0000

0x0000 0058

0x4005 0058

RIS1

RO

32

0x0000 0000

0x0000 0060

0x4005 0060

MIS1

RO

32

0x0000 0000

0x0000 0068

0x4005 0068

ISET1

WO

32

0x0000 0000

0x0000 0070

0x4005 0070

ICLR1

WO

32

0x0000 0000

0x0000 0078

0x4005 0078

IMASK2

RW

32

0x0000 0000

0x0000 0088

0x4005 0088

RIS2

RO

32

0x0000 0000

0x0000 0090

0x4005 0090

MIS2

RO

32

0x0000 0000

0x0000 0098

0x4005 0098

ISET2

WO

32

0x0000 0000

0x0000 00A0

0x4005 00A0

ICLR2

WO

32

0x0000 0000

0x0000 00A8

0x4005 00A8

CTL0

RW

32

0x0000 0000

0x0000 0100

0x4005 0100

CTL1

RW

32

0x0000 0000

0x0000 0104

0x4005 0104

CTL2

RW

32

0x0000 0000

0x0000 0108

0x4005 0108

CTL3

RW

32

0x0000 0000

0x0000 010C

0x4005 010C

SCOMP0

RW

32

0x0000 0000

0x0000 0114

0x4005 0114

SCOMP1

RW

32

0x0000 0000

0x0000 0118

0x4005 0118

REFCFG

RW

32

0x0000 0000

0x0000 011C

0x4005 011C

WCLOW

RW

32

0x0000 0000

0x0000 0148

0x4005 0148

WCHIGH

RW

32

0x0000 0000

0x0000 0150

0x4005 0150

FIFODATA

RO

32

0x0000 0000

0x0000 0160

0x4005 0160

ASCRES

RO

32

0x0000 0000

0x0000 0170

0x4005 0170

MEMCTL0

RW

32

0x0000 0000

0x0000 0180

0x4005 0180

MEMCTL1

RW

32

0x0000 0000

0x0000 0184

0x4005 0184

MEMCTL2

RW

32

0x0000 0000

0x0000 0188

0x4005 0188

MEMCTL3

RW

32

0x0000 0000

0x0000 018C

0x4005 018C

MEMRES0

RO

32

0x0000 0000

0x0000 0280

0x4005 0280

MEMRES1

RO

32

0x0000 0000

0x0000 0284

0x4005 0284

MEMRES2

RO

32

0x0000 0000

0x0000 0288

0x4005 0288

MEMRES3

RO

32

0x0000 0000

0x0000 028C

0x4005 028C

STA

RO

32

0x0000 0000

0x0000 0340

0x4005 0340

TEST0

RW

32

0x0000 0000

0x0000 0E00

0x4005 0E00

TEST2

RW

32

0x0000 0000

0x0000 0E08

0x4005 0E08

TEST3

RW

32

0x0000 0000

0x0000 0E0C

0x4005 0E0C

TEST4

RW

32

0x0000 0000

0x0000 0E10

0x4005 0E10

TEST5

RW

32

0x0000 0000

0x0000 0E14

0x4005 0E14

TEST6

RW

32

0x0000 0000

0x0000 0E18

0x4005 0E18

DEBUG1

RW

32

0x0080 1000

0x0000 0E20

0x4005 0E20

DEBUG2

RW

32

0x0000 0000

0x0000 0E24

0x4005 0E24

DEBUG3

RW

32

0x0000 0000

0x0000 0E28

0x4005 0E28

DEBUG4

RW

32

0x0000 0000

0x0000 0E2C

0x4005 0E2C

TOP:ADC Register Descriptions

TOP:ADC:IMASK0

Address Offset 0x0000 0028
Physical Address 0x4005 0028 Instance 0x4005 0028
Description Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS0 to MIS0 when the corresponding bit-fields are set to 1.
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 MEMRES3 conversion result interrupt mask.
Value ENUM Name Description
0x0 DIS Disable interrupt mask
0x1 EN Enable interrupt mask
RW 0
10 MEMRESIFG2 MEMRES2 conversion result interrupt mask.
Value ENUM Name Description
0x0 DIS Disable interrupt mask
0x1 EN Enable interrupt mask
RW 0
9 MEMRESIFG1 MEMRES1 conversion result interrupt mask.
Value ENUM Name Description
0x0 DIS Disable interrupt mask
0x1 EN Enable interrupt mask
RW 0
8 MEMRESIFG0 MEMRES0 conversion result interrupt mask.
Value ENUM Name Description
0x0 DIS Disable interrupt mask
0x1 EN Enable interrupt mask
RW 0
7 ASCDONE Mask for ASC done raw interrupt flag.
Value ENUM Name Description
0x0 DIS Disable interrupt mask
0x1 EN Enable interrupt mask
RW 0
6 UVIFG Conversion underflow interrupt mask.
Value ENUM Name Description
0x0 DIS Disable interrupt mask
0x1 EN Enable interrupt mask
RW 0
5 DMADONE DMA done interrupt mask.
Value ENUM Name Description
0x0 DIS Disable interrupt mask
0x1 EN Enable interrupt mask
RW 0
4 INIFG In-range comparator interrupt mask.
Value ENUM Name Description
0x0 DIS Disable interrupt mask
0x1 EN Enable interrupt mask
RW 0
3 LOWIFG Low threshold compare interrupt mask.
Value ENUM Name Description
0x0 DIS Disable interrupt mask
0x1 EN Enable interrupt mask
RW 0
2 HIGHIFG High threshold compare interrupt mask.
Value ENUM Name Description
0x0 DIS Disable interrupt mask
0x1 EN Enable interrupt mask
RW 0
1 TOVIFG Sequence conversion time overflow interrupt mask.
Value ENUM Name Description
0x0 DIS Disable interrupt mask
0x1 EN Enable interrupt mask
RW 0
0 OVIFG Conversion overflow interrupt mask.
Value ENUM Name Description
0x0 DIS Disable interrupt mask
0x1 EN Enable interrupt mask
RW 0

TOP:ADC:RIS0

Address Offset 0x0000 0030
Physical Address 0x4005 0030 Instance 0x4005 0030
Description Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR0 register bit.
Type RO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Raw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR0 is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 Raw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR0 is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 Raw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR0 is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR0 is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7 ASCDONE Raw interrupt flag for ASC done.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
6 UVIFG Raw interrupt flag for MEMRESx underflow.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
5 DMADONE Raw interrupt flag for DMADONE.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
4 INIFG Raw interrupt status for In-range comparator.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1 TOVIFG Raw interrupt flag for sequence conversion trigger overflow.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
0 OVIFG Raw interrupt flag for MEMRESx overflow.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0

TOP:ADC:MIS0

Address Offset 0x0000 0038
Physical Address 0x4005 0038 Instance 0x4005 0038
Description Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.
Type RO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Masked interrupt status for MEMRES3.
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 Masked interrupt status for MEMRES2.
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 Masked interrupt status for MEMRES1.
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 Masked interrupt status for MEMRES0.
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7 ASCDONE Masked interrupt status for ASC done.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
6 UVIFG Masked interrupt flag for MEMRESx underflow.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
5 DMADONE Masked interrupt flag for DMADONE.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
4 INIFG Mask INIFG in MIS0 register.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Masked interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG Masked interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1 TOVIFG Masked interrupt flag for sequence conversion timeout overflow.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
0 OVIFG Masked interrupt flag for MEMRESx overflow.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0

TOP:ADC:ISET0

Address Offset 0x0000 0040
Physical Address 0x4005 0040 Instance 0x4005 0040
Description Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.
Type WO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Set interrupt status for MEMRES3.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 Set interrupt status for MEMRES2.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 Set interrupt status for MEMRES1.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 Set Interrupt status for MEMRES0.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7 ASCDONE Set interrupt for ASC done.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
6 UVIFG Set interrupt for MEMRESx underflow.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
5 DMADONE Set interrupt for DMADONE.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
4 INIFG Set INIFG interrupt register.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Set interrupt for MEMRESx result register being below than the WCLOWx threshold of the window comparator.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG Set Interrupt for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1 TOVIFG Set interrupt for sequence conversion timeout overflow.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
0 OVIFG Set Interrupt for MEMRESx overflow.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0

TOP:ADC:ICLR0

Address Offset 0x0000 0048
Physical Address 0x4005 0048 Instance 0x4005 0048
Description Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.
Type WO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Clear interrupt status for MEMRES3.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
10 MEMRESIFG2 Clear interrupt status for MEMRES2.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
9 MEMRESIFG1 Clear interrupt status for MEMRES1.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
8 MEMRESIFG0 Clear interrupt status for MEMRES0.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
7 ASCDONE Clear ASC done flag in RIS.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
6 UVIFG Clear interrupt flag for MEMRESx underflow.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
5 DMADONE Clear interrupt flag for DMADONE.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
4 INIFG Clear INIFG in MIS0 register.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
3 LOWIFG Clear interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
2 HIGHIFG Clear interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
1 TOVIFG Clear interrupt flag for sequence conversion timeout overflow.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
0 OVIFG Clear interrupt flag for MEMRESx overflow.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0

TOP:ADC:IMASK1

Address Offset 0x0000 0058
Physical Address 0x4005 0058 Instance 0x4005 0058
Description Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS0 to MIS0 when the corresponding bit-fields are set to 1.
Type RW
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 MEMRESIFG0 MEMRES0 conversion result interrupt mask.
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4 INIFG In-range comparator interrupt mask.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Low threshold compare interrupt mask.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG High threshold compare interrupt mask.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00

TOP:ADC:RIS1

Address Offset 0x0000 0060
Physical Address 0x4005 0060 Instance 0x4005 0060
Description Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR0 register bit.
Type RO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR1 is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4 INIFG Raw interrupt status for In-range comparator.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00

TOP:ADC:MIS1

Address Offset 0x0000 0068
Physical Address 0x4005 0068 Instance 0x4005 0068
Description Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.
Type RO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 MEMRESIFG0 Masked interrupt status for MEMRES0.
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4 INIFG Mask INIFG in MIS1 register.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Masked interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG Masked interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
Value ENUM Name Description
0x0 CLR Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00

TOP:ADC:ISET1

Address Offset 0x0000 0070
Physical Address 0x4005 0070 Instance 0x4005 0070
Description Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.
Type WO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 MEMRESIFG0 Set Interrupt status for MEMRES0.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4 INIFG Set INIFG interrupt register.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
3 LOWIFG Set interrupt for MEMRESx result register being below than the WCLOWx threshold of the window comparator.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
2 HIGHIFG Set Interrupt for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 SET Interrupt is pending.
RW 0
1:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00

TOP:ADC:ICLR1

Address Offset 0x0000 0078
Physical Address 0x4005 0078 Instance 0x4005 0078
Description Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.
Type WO
Bits Field Name Description Type Reset
31:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000
8 MEMRESIFG0 Clear interrupt status for MEMRES0.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4 INIFG Clear INIFG in MIS1 register.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
3 LOWIFG Clear interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
2 HIGHIFG Clear interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
Value ENUM Name Description
0x0 NO_EFFECT Interrupt is not pending.
0x1 CLR Interrupt is pending.
RW 0
1:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00

TOP:ADC:IMASK2

Address Offset 0x0000 0088
Physical Address 0x4005 0088 Instance 0x4005 0088
Description Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS0 to MIS0 when the corresponding bit-fields are set to 1.
Type RW
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 MEMRES3 conversion result interrupt mask.
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 MEMRES2 conversion result interrupt mask.
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 MEMRES1 conversion result interrupt mask.
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 MEMRES0 conversion result interrupt mask.
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00

TOP:ADC:RIS2

Address Offset 0x0000 0090
Physical Address 0x4005 0090 Instance 0x4005 0090
Description Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR0 register bit.
Type RO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Raw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR2 is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 Raw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR2 is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 Raw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR2 is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 Raw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR2 is set to 1
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00

TOP:ADC:MIS2

Address Offset 0x0000 0098
Physical Address 0x4005 0098 Instance 0x4005 0098
Description Extension of Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.
Type RO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Masked interrupt status for MEMRES3.
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 Masked interrupt status for MEMRES2.
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 Masked interrupt status for MEMRES1.
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 Masked interrupt status for MEMRES0.
Value ENUM Name Description
0x0 CLR No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00

TOP:ADC:ISET2

Address Offset 0x0000 00A0
Physical Address 0x4005 00A0 Instance 0x4005 00A0
Description Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.
Type WO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Set interrupt status for MEMRES3.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
10 MEMRESIFG2 Set interrupt status for MEMRES2.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
9 MEMRESIFG1 Set interrupt status for MEMRES1.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
8 MEMRESIFG0 Set Interrupt status for MEMRES0.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 SET A new data is ready to be read.
RW 0
7:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00

TOP:ADC:ICLR2

Address Offset 0x0000 00A8
Physical Address 0x4005 00A8 Instance 0x4005 00A8
Description Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.
Type WO
Bits Field Name Description Type Reset
31:12 RESERVED12 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0 0000
11 MEMRESIFG3 Clear interrupt status for MEMRES3.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
10 MEMRESIFG2 Clear interrupt status for MEMRES2.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
9 MEMRESIFG1 Clear interrupt status for MEMRES1.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
8 MEMRESIFG0 Clear interrupt status for MEMRES0.
Value ENUM Name Description
0x0 NO_EFFECT No new data ready.
0x1 CLR A new data is ready to be read.
RW 0
7:0 RESERVED0 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x00

TOP:ADC:CTL0

Address Offset 0x0000 0100
Physical Address 0x4005 0100 Instance 0x4005 0100
Description Control Register 0
Type RW
Bits Field Name Description Type Reset
31:27 RESERVED27 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
26:24 SCLKDIV Sample clock divider
Value ENUM Name Description
0x0 DIV_BY_1 Do not divide clock source
0x1 DIV_BY_2 Divide clock source by 2
0x2 DIV_BY_4 Divide clock source by 4
0x3 DIV_BY_8 Divide clock source by 8
0x4 DIV_BY_16 Divide clock source by 16
0x5 DIV_BY_24 Divide clock source by 24
0x6 DIV_BY_32 Divide clock source by 32
0x7 DIV_BY_48 Divide clock source by 48
RW 0b000
23:17 RESERVED17 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
16 PWRDN Power down policy
Value ENUM Name Description
0x0 AUTO ADC is powered down on completion of a conversion if there is no pending trigger
0x1 MANUAL ADC remains powered on as long as it is enabled through software.
RW 0
15:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000
0 ENC Enable conversion
Value ENUM Name Description
0x0 OFF Conversion disabled. ENC change from ON to OFF will abort single or repeat sequence on a MEMCTLx boundary. The current conversion will finish and result stored in corresponding MEMRESx.
0x1 ON Conversion enabled. ADC sequencer waits for the programmed trigger (software or hardware).
RW 0

TOP:ADC:CTL1

Address Offset 0x0000 0104
Physical Address 0x4005 0104 Instance 0x4005 0104
Description Control Register 1
Type RW
Bits Field Name Description Type Reset
31:21 RESERVED21 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
20 SAMPMODE Sample mode. This bit selects the source of the sampling signal.
MANUAL option is not applicable when TRIGSRC is selected as hardware event trigger.
Value ENUM Name Description
0x0 AUTO Sample timer high phase is used as sample signal
0x1 MANUAL Software trigger is used as sample signal
RW 0
19:18 RESERVED18 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
17:16 CONSEQ Conversion sequence mode
Value ENUM Name Description
0x0 SINGLE ADC channel in MEMCTLx pointed by STARTADD will be converted once
0x1 SEQUENCE ADC channel sequence pointed by STARTADD and ENDADD will be converted once
0x2 REPEATSINGLE ADC channel in MEMCTLx pointed by STARTADD will be converted repeatedly
0x3 REPEATSEQUENCE ADC channel sequence pointed by STARTADD and ENDADD will be converted repeatedly
RW 0b00
15:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
8 SC Start of conversion
Value ENUM Name Description
0x0 STOP When SAMPMODE is set to MANUAL, clearing this bit will end the sample phase and the conversion phase will start.
When SAMPMODE is set to AUTO, writing 0 has no effect.
0x1 START When SAMPMODE is set to MANUAL, setting this bit will start the sample phase. Sample phase will last as long as this bit is set.
When SAMPMODE is set to AUTO, setting this bit will trigger the timer based sample time.
RW 0
7:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000
0 TRIGSRC Sample trigger source
Value ENUM Name Description
0x0 SOFTWARE Software trigger
0x1 EVENT Hardware event trigger
RW 0

TOP:ADC:CTL2

Address Offset 0x0000 0108
Physical Address 0x4005 0108 Instance 0x4005 0108
Description Control Register 2
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28:24 ENDADD Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode.
The value of ENDADD is 0x00 to 0x03 corresponding to MEMRES0 to MEMRES3.
Value ENUM Name Description
0x0 ADDR_00 MEMCTL0 is selected as end address of sequence.
0x1 ADDR_01 MEMCTL1 is selected as end address of sequence.
0x2 ADDR_02 MEMCTL2 is selected as end address of sequence.
0x3 ADDR_03 MEMCTL3 is selected as end address of sequence.
RW 0b0 0000
23:21 RESERVED21 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
20:16 STARTADD Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode.
The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
Value ENUM Name Description
0x0 ADDR_00 MEMCTL0 is selected as start address of a sequence or for a single conversion.
0x1 ADDR_01 MEMCTL1 is selected as start address of a sequence or for a single conversion.
0x2 ADDR_02 MEMCTL2 is selected as start address of a sequence or for a single conversion.
0x3 ADDR_03 MEMCTL3 is selected as start address of a sequence or for a single conversion.
RW 0b0 0000
15:11 RESERVED11 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
10 FIFOEN Enable FIFO based operation
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
8 DMAEN Enable DMA trigger for data transfer.
Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers.
Value ENUM Name Description
0x0 DIS DMA trigger not enabled
0x1 EN DMA trigger enabled
RW 0
7:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000
2:1 RES Resolution. These bits define the resolutoin of ADC conversion result.
Note : A value of 3 defaults to 12-bits resolution.
Value ENUM Name Description
0x0 BIT_12 12-bits resolution
0x1 BIT_10 10-bits resolution
0x2 BIT_8 8-bits resolution
RW 0b00
0 DF Data read-back format. Data is always stored in binary unsigned format.
Value ENUM Name Description
0x0 UNSIGNED Digital result reads as Binary Unsigned.
0x1 SIGNED Digital result reads Signed Binary. (2s complement), left aligned.
RW 0

TOP:ADC:CTL3

Address Offset 0x0000 010C
Physical Address 0x4005 010C Instance 0x4005 010C
Description Control Register 3. This register is used to configure ADC for ad-hoc single conversion.
Type RW
Bits Field Name Description Type Reset
31:14 RESERVED14 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000
13:12 ASCVRSEL Selects voltage reference for ASC operation. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
Value ENUM Name Description
0x0 VDDS VDDS reference
0x1 EXTREF External reference from AREF+/AREF- pins
0x2 INTREF Internal reference
RW 0b00
11:9 RESERVED9 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
8 ASCSTIME ASC sample time compare value select. This is used to select between SCOMP0 and SCOMP1 registers for ASC operation.
Value ENUM Name Description
0x0 SEL_SCOMP0 Select SCOMP0
0x1 SEL_SCOMP1 Select SCOMP1
RW 0
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4:0 ASCCHSEL ASC channel select
Value ENUM Name Description
0x0 CHAN_0 Selects channel 0
0x1 CHAN_1 Selects channel 1
0x2 CHAN_2 Selects channel 2
0x3 CHAN_3 Selects channel 3
0x4 CHAN_4 Selects channel 4
0x5 CHAN_5 Selects channel 5
0x6 CHAN_6 Selects channel 6
0x7 CHAN_7 Selects channel 7
0x8 CHAN_8 Selects channel 8
0x9 CHAN_9 Selects channel 9
0xA CHAN_10 Selects channel 10
0xB CHAN_11 Selects channel 11
0xC CHAN_12 Selects channel 12
0xD CHAN_13 Selects channel 13
0xE CHAN_14 Selects channel 14
0xF CHAN_15 Selects channel 15
RW 0b0 0000

TOP:ADC:SCOMP0

Address Offset 0x0000 0114
Physical Address 0x4005 0114 Instance 0x4005 0114
Description Sample time compare 0 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be set to 0 to write to this register.
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 VAL Specifies the number of sample clocks.
When VAL = 0 or 1, number of sample clocks = Sample clock divide value.
When VAL > 1, number of sample clocks = VAL x Sample clock divide value.
Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4).
Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.		 RW 0b00 0000 0000

TOP:ADC:SCOMP1

Address Offset 0x0000 0118
Physical Address 0x4005 0118 Instance 0x4005 0118
Description Sample time compare 1 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be set to 0 to write to this register.
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000
9:0 VAL Specifies the number of sample clocks.
When VAL = 0 or 1, number of sample clocks = Sample clock divide value.
When VAL > 1, number of sample clocks = VAL x Sample clock divide value.
Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4).
Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.		 RW 0b00 0000 0000

TOP:ADC:REFCFG

Address Offset 0x0000 011C
Physical Address 0x4005 011C Instance 0x4005 011C
Description Reference buffer configuration register
Type RW
Bits Field Name Description Type Reset
31:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000
4:3 IBPROG Configures reference buffer bias current output value
Value ENUM Name Description
0x0 VAL0 1uA
0x1 VAL1 0.5uA
0x2 VAL2 2uA
0x3 VAL3 0.67uA
RW 0b00
2 SPARE Spare bit RW 0
1 REFVSEL Configures reference buffer output voltage
Value ENUM Name Description
0x0 V2P5 REFBUF generates 2.5V output
0x1 V1P4 REFBUF generates 1.4V output
RW 0
0 REFEN Reference buffer enable
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0

TOP:ADC:WCLOW

Address Offset 0x0000 0148
Physical Address 0x4005 0148 Instance 0x4005 0148
Description Window Comparator Low Threshold Register.
The data format that is used to write and read WCLOW depends on the value of DF bit in CTL2 register.
CTL0.ENC must be 0 to write to this register.
Note: Change in ADC data format or resolution does not reset WCLOW.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA If DF = 0, unsigned binary format has to be used.
The value based on the resolution has to be right aligned with the MSB on the left.
For 10-bits and 8-bits resolution, unused bits have to be 0s.

If DF = 1, 2s-complement format has to be used.
The value based on the resolution has to be left aligned with the LSB on the right.
For 10-bits and 8-bits resolution, unused bits have to be 0s.		 RW 0x0000

TOP:ADC:WCHIGH

Address Offset 0x0000 0150
Physical Address 0x4005 0150 Instance 0x4005 0150
Description Window Comparator High Threshold Register.
The data format that is used to write and read WCHIGH depends on the value of DF bit in CTL2 register.
CTL0.ENC must be 0 to write to this register.
Note: Change in ADC data format or resolution does not reset WCHIGH.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA If DF = 0, unsigned binary format has to be used.
The threshold value has to be right aligned, with the MSB on the left.
For 10-bits and 8-bits resolution, unused bit have to be 0s.

If DF = 1, 2s-complement format has to be used.
The value based on the resolution has to be left aligned with the LSB on the right.
For 10-bits and 8-bits resolution, unused bit have to be 0s.		 RW 0x0000

TOP:ADC:FIFODATA

Address Offset 0x0000 0160
Physical Address 0x4005 0160 Instance 0x4005 0160
Description FIFO data register. This is a virtual register used to read from FIFO.
Type RO
Bits Field Name Description Type Reset
31:0 DATA Read from this data field returns the ADC sample from FIFO. RW 0x0000 0000

TOP:ADC:ASCRES

Address Offset 0x0000 0170
Physical Address 0x4005 0170 Instance 0x4005 0170
Description ASC result register
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA Result of ADC ad-hoc single conversion.
If DF = 0, unsigned binary:
The conversion result is right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion result is left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.		 RO 0x0000

TOP:ADC:MEMCTL0

Address Offset 0x0000 0180
Physical Address 0x4005 0180 Instance 0x4005 0180
Description Conversion Memory Control Register 0.
CTL0.ENC must be set to 0 to write to this register.
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28 WINCOMP Enable window comparator.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
27:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
24 TRG Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
Value ENUM Name Description
0x0 AUTO_NEXT Next conversion is automatic
0x1 TRIGGER_NEXT Next conversion requires a trigger
RW 0
23:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
12 STIME Selects the source of sample timer period between SCOMP0 and SCOMP1.
Value ENUM Name Description
0x0 SEL_SCOMP0 Select SCOMP0
0x1 SEL_SCOMP1 Select SCOMP1
RW 0
11:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
9:8 VRSEL Voltage reference selection. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
Value ENUM Name Description
0x0 VDDS VDDS reference
0x1 EXTREF External reference from AREF+/AREF- pins
0x2 INTREF Internal reference
RW 0b00
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4:0 CHANSEL Input channel select.
Value ENUM Name Description
0x0 CHAN_0 Selects channel 0
0x1 CHAN_1 Selects channel 1
0x2 CHAN_2 Selects channel 2
0x3 CHAN_3 Selects channel 3
0x4 CHAN_4 Selects channel 4
0x5 CHAN_5 Selects channel 5
0x6 CHAN_6 Selects channel 6
0x7 CHAN_7 Selects channel 7
0x8 CHAN_8 Selects channel 8
0x9 CHAN_9 Selects channel 9
0xA CHAN_10 Selects channel 10
0xB CHAN_11 Selects channel 11
0xC CHAN_12 Selects channel 12
0xD CHAN_13 Selects channel 13
0xE CHAN_14 Selects channel 14
0xF CHAN_15 Selects channel 15
RW 0b0 0000

TOP:ADC:MEMCTL1

Address Offset 0x0000 0184
Physical Address 0x4005 0184 Instance 0x4005 0184
Description Conversion Memory Control Register 1.
CTL0.ENC must be set to 0 to write to this register.
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28 WINCOMP Enable window comparator.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
27:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
24 TRG Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
Value ENUM Name Description
0x0 AUTO_NEXT Next conversion is automatic
0x1 TRIGGER_NEXT Next conversion requires a trigger
RW 0
23:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
12 STIME Selects the source of sample timer period between SCOMP0 and SCOMP1.
Value ENUM Name Description
0x0 SEL_SCOMP0 Select SCOMP0
0x1 SEL_SCOMP1 Select SCOMP1
RW 0
11:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
9:8 VRSEL Voltage reference selection. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
Value ENUM Name Description
0x0 VDDS VDDS reference
0x1 EXTREF External reference from AREF+/AREF- pins
0x2 INTREF Internal reference
RW 0b00
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4:0 CHANSEL Input channel select.
Value ENUM Name Description
0x0 CHAN_0 Selects channel 0
0x1 CHAN_1 Selects channel 1
0x2 CHAN_2 Selects channel 2
0x3 CHAN_3 Selects channel 3
0x4 CHAN_4 Selects channel 4
0x5 CHAN_5 Selects channel 5
0x6 CHAN_6 Selects channel 6
0x7 CHAN_7 Selects channel 7
0x8 CHAN_8 Selects channel 8
0x9 CHAN_9 Selects channel 9
0xA CHAN_10 Selects channel 10
0xB CHAN_11 Selects channel 11
0xC CHAN_12 Selects channel 12
0xD CHAN_13 Selects channel 13
0xE CHAN_14 Selects channel 14
0xF CHAN_15 Selects channel 15
RW 0b0 0000

TOP:ADC:MEMCTL2

Address Offset 0x0000 0188
Physical Address 0x4005 0188 Instance 0x4005 0188
Description Conversion Memory Control Register 2.
CTL0.ENC must be set to 0 to write to this register.
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28 WINCOMP Enable window comparator.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
27:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
24 TRG Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
Value ENUM Name Description
0x0 AUTO_NEXT Next conversion is automatic
0x1 TRIGGER_NEXT Next conversion requires a trigger
RW 0
23:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
12 STIME Selects the source of sample timer period between SCOMP0 and SCOMP1.
Value ENUM Name Description
0x0 SEL_SCOMP0 Select SCOMP0
0x1 SEL_SCOMP1 Select SCOMP1
RW 0
11:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
9:8 VRSEL Voltage reference selection. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
Value ENUM Name Description
0x0 VDDS VDDS reference
0x1 EXTREF External reference from AREF+/AREF- pins
0x2 INTREF Internal reference
RW 0b00
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4:0 CHANSEL Input channel select.
Value ENUM Name Description
0x0 CHAN_0 Selects channel 0
0x1 CHAN_1 Selects channel 1
0x2 CHAN_2 Selects channel 2
0x3 CHAN_3 Selects channel 3
0x4 CHAN_4 Selects channel 4
0x5 CHAN_5 Selects channel 5
0x6 CHAN_6 Selects channel 6
0x7 CHAN_7 Selects channel 7
0x8 CHAN_8 Selects channel 8
0x9 CHAN_9 Selects channel 9
0xA CHAN_10 Selects channel 10
0xB CHAN_11 Selects channel 11
0xC CHAN_12 Selects channel 12
0xD CHAN_13 Selects channel 13
0xE CHAN_14 Selects channel 14
0xF CHAN_15 Selects channel 15
RW 0b0 0000

TOP:ADC:MEMCTL3

Address Offset 0x0000 018C
Physical Address 0x4005 018C Instance 0x4005 018C
Description Conversion Memory Control Register 3.
CTL0.ENC must be set to 0 to write to this register.
Type RW
Bits Field Name Description Type Reset
31:29 RESERVED29 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
28 WINCOMP Enable window comparator.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 0
27:25 RESERVED25 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
24 TRG Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
Value ENUM Name Description
0x0 AUTO_NEXT Next conversion is automatic
0x1 TRIGGER_NEXT Next conversion requires a trigger
RW 0
23:13 RESERVED13 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000
12 STIME Selects the source of sample timer period between SCOMP0 and SCOMP1.
Value ENUM Name Description
0x0 SEL_SCOMP0 Select SCOMP0
0x1 SEL_SCOMP1 Select SCOMP1
RW 0
11:10 RESERVED10 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00
9:8 VRSEL Voltage reference selection. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
Value ENUM Name Description
0x0 VDDS VDDS reference
0x1 EXTREF External reference from AREF+/AREF- pins
0x2 INTREF Internal reference
RW 0b00
7:5 RESERVED5 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000
4:0 CHANSEL Input channel select.
Value ENUM Name Description
0x0 CHAN_0 Selects channel 0
0x1 CHAN_1 Selects channel 1
0x2 CHAN_2 Selects channel 2
0x3 CHAN_3 Selects channel 3
0x4 CHAN_4 Selects channel 4
0x5 CHAN_5 Selects channel 5
0x6 CHAN_6 Selects channel 6
0x7 CHAN_7 Selects channel 7
0x8 CHAN_8 Selects channel 8
0x9 CHAN_9 Selects channel 9
0xA CHAN_10 Selects channel 10
0xB CHAN_11 Selects channel 11
0xC CHAN_12 Selects channel 12
0xD CHAN_13 Selects channel 13
0xE CHAN_14 Selects channel 14
0xF CHAN_15 Selects channel 15
RW 0b0 0000

TOP:ADC:MEMRES0

Address Offset 0x0000 0280
Physical Address 0x4005 0280 Instance 0x4005 0280
Description Memory Result Register 0
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA If DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.		 RW 0x0000

TOP:ADC:MEMRES1

Address Offset 0x0000 0284
Physical Address 0x4005 0284 Instance 0x4005 0284
Description Memory Result Register 1
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA If DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.		 RW 0x0000

TOP:ADC:MEMRES2

Address Offset 0x0000 0288
Physical Address 0x4005 0288 Instance 0x4005 0288
Description Memory Result Register 2
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA If DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.		 RW 0x0000

TOP:ADC:MEMRES3

Address Offset 0x0000 028C
Physical Address 0x4005 028C Instance 0x4005 028C
Description Memory Result Register 3
Type RO
Bits Field Name Description Type Reset
31:16 RESERVED16 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0000
15:0 DATA If DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.		 RW 0x0000

TOP:ADC:STA

Address Offset 0x0000 0340
Physical Address 0x4005 0340 Instance 0x4005 0340
Description Status Register
Type RO
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 ASCACT ASC active
Value ENUM Name Description
0x0 IDLE Idle or done
0x1 ACTIVE ASC active
RO 0
1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0
0 BUSY Busy. This bit indicates that an active ADC sample or conversion operation is in progress.
Value ENUM Name Description
0x0 IDLE No ADC sampling or conversion in progress.
0x1 ACTIVE ADC sampling or conversion is in progress.
RO 0

TOP:ADC:TEST0

Address Offset 0x0000 0E00
Physical Address 0x4005 0E00 Instance 0x4005 0E00
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31 RESERVED31 Internal. Only to be used through TI provided API. RO 0
30 ATEST0_EN Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 DIS Internal. Only to be used through TI provided API.
0x1 EN Internal. Only to be used through TI provided API.
RW 0
29 ATEST1_EN Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 DIS Internal. Only to be used through TI provided API.
0x1 EN Internal. Only to be used through TI provided API.
RW 0
28:13 RESERVED13 Internal. Only to be used through TI provided API. RO 0x0000
12:8 ATEST1_MUXSEL Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x1 VAL1 Internal. Only to be used through TI provided API.
0x2 VAL2 Internal. Only to be used through TI provided API.
0x4 VAL4 Internal. Only to be used through TI provided API.
0x8 VAL8 Internal. Only to be used through TI provided API.
0x10 VAL16 Internal. Only to be used through TI provided API.
RW 0b0 0000
7:5 RESERVED5 Internal. Only to be used through TI provided API. RO 0b000
4:0 ATEST0_MUXSEL Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x1 VAL1 Internal. Only to be used through TI provided API.
0x2 VAL2 Internal. Only to be used through TI provided API.
0x4 VAL4 Internal. Only to be used through TI provided API.
0x8 VAL8 Internal. Only to be used through TI provided API.
0x10 VAL16 Internal. Only to be used through TI provided API.
RW 0b0 0000

TOP:ADC:TEST2

Address Offset 0x0000 0E08
Physical Address 0x4005 0E08 Instance 0x4005 0E08
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31 CDAC_OVST_EN Internal. Only to be used through TI provided API. RW 0
30:25 RESERVED25 Internal. Only to be used through TI provided API. RO 0b00 0000
24 LATCH_TRIM_EN Internal. Only to be used through TI provided API. RW 0
23:21 RESERVED21 Internal. Only to be used through TI provided API. RO 0b000
20 COMP_GAIN_TRIM Internal. Only to be used through TI provided API. RW 0
19:9 RESERVED9 Internal. Only to be used through TI provided API. RO 0b000 0000 0000
8 MUX_TEST_SEL Internal. Only to be used through TI provided API. RW 0
7:0 RESERVED0 Internal. Only to be used through TI provided API. RO 0x00

TOP:ADC:TEST3

Address Offset 0x0000 0E0C
Physical Address 0x4005 0E0C Instance 0x4005 0E0C
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:0 CAL_ACUML Internal. Only to be used through TI provided API. RW 0x0000 0000

TOP:ADC:TEST4

Address Offset 0x0000 0E10
Physical Address 0x4005 0E10 Instance 0x4005 0E10
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31 HW_STEP_SEL_DIS Internal. Only to be used through TI provided API. RW 0
30:25 RESERVED25 Internal. Only to be used through TI provided API. RO 0b00 0000
24 CAL_MODE_EN Internal. Only to be used through TI provided API. RW 0
23:22 RESERVED22 Internal. Only to be used through TI provided API. RO 0b00
21:16 CAL_STEP_SEL Internal. Only to be used through TI provided API. RW 0b00 0000
15:0 RESERVED0 Internal. Only to be used through TI provided API. RO 0x0000

TOP:ADC:TEST5

Address Offset 0x0000 0E14
Physical Address 0x4005 0E14 Instance 0x4005 0E14
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:10 RESERVED10 Internal. Only to be used through TI provided API. RO 0b00 0000 0000 0000 0000 0000
9:0 CAL_CAP_CTL Internal. Only to be used through TI provided API. RW 0b00 0000 0000

TOP:ADC:TEST6

Address Offset 0x0000 0E18
Physical Address 0x4005 0E18 Instance 0x4005 0E18
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Internal. Only to be used through TI provided API. RO 0x000 0000
3:0 ATESTSEL Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 VAL0 Internal. Only to be used through TI provided API.
0x1 VAL1 Internal. Only to be used through TI provided API.
0x2 VAL2 Internal. Only to be used through TI provided API.
0x4 VAL4 Internal. Only to be used through TI provided API.
0x8 VAL8 Internal. Only to be used through TI provided API.
RW 0x0

TOP:ADC:DEBUG1

Address Offset 0x0000 0E20
Physical Address 0x4005 0E20 Instance 0x4005 0E20
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:0 CTRL Internal. Only to be used through TI provided API. RW 0x0080 1000

TOP:ADC:DEBUG2

Address Offset 0x0000 0E24
Physical Address 0x4005 0E24 Instance 0x4005 0E24
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:30 RESERVED30 Internal. Only to be used through TI provided API. RO 0b00
29:28 VTOI_CTRL Internal. Only to be used through TI provided API. RW 0b00
27:25 RESERVED25 Internal. Only to be used through TI provided API. RO 0b000
24 VTOI_TESTMODE_EN Internal. Only to be used through TI provided API. RW 0
23:0 RESERVED0 Internal. Only to be used through TI provided API. RO 0x00 0000

TOP:ADC:DEBUG3

Address Offset 0x0000 0E28
Physical Address 0x4005 0E28 Instance 0x4005 0E28
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Internal. Only to be used through TI provided API. RO 0b00 0000 0000 0000 0000 0000 0000
5 DEC1_DIS Internal. Only to be used through TI provided API. RW 0
4 DEC0_DIS Internal. Only to be used through TI provided API. RW 0
3:1 RESERVED1 Internal. Only to be used through TI provided API. RO 0b000
0 BOOST_ENZ Internal. Only to be used through TI provided API. RW 0

TOP:ADC:DEBUG4

Address Offset 0x0000 0E2C
Physical Address 0x4005 0E2C Instance 0x4005 0E2C
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:16 RESERVED16 Internal. Only to be used through TI provided API. RO 0x0000
15:0 ADC_CTRL0 Internal. Only to be used through TI provided API. RW 0x0000


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