AM64x MCU+ SDK  08.02.00

Detailed Description

CIP Sync configuration. Instance Attribute for PTP Class (Class Code 0x43. CIP Spec Vol 1)

Data Fields

uint8_t ifPTPEnable
uint8_t IsSynchronized
uint64_t systemTimeMicrosec
uint64_t systemTimeNanosec
int64_t offsetFromMaster
uint64_t maxOffsetFromMaster
int64_t meanPathDelayToMaster
clockClass_t grandMasterClkInfo
clockClass_t parentClkInfo
clockClass_t localClkInfo
uint16_t numberOfPorts
uint16_t portLogAnnounceInterval [ICSS_EMAC_MAX_PORTS_PER_INSTANCE]
uint16_t portLogSyncInterval [ICSS_EMAC_MAX_PORTS_PER_INSTANCE]
uint8_t priority1
uint8_t priority2
uint8_t domainNumber
clockType clockType
uint8_t manufacturerIdentity [4]
descr_t productType
descr_t revData
descr_t userDesc
portProfileIdentity_t profileInfo [ICSS_EMAC_MAX_PORTS_PER_INSTANCE]
uint16_t stepsRemoved
sysTimeOffset_t timeOffset

Field Documentation

◆ ifPTPEnable

uint8_t cipSyncConfig_t::ifPTPEnable

If PTP is enabled on system. Only applicable for OC

◆ IsSynchronized

uint8_t cipSyncConfig_t::IsSynchronized

If PTP is synchronized with Master

◆ systemTimeMicrosec

uint64_t cipSyncConfig_t::systemTimeMicrosec

Current system time in Microseconds

◆ systemTimeNanosec

uint64_t cipSyncConfig_t::systemTimeNanosec

Current system time in Nanoseconds

◆ offsetFromMaster

int64_t cipSyncConfig_t::offsetFromMaster

Offset between local clock and master clock

◆ maxOffsetFromMaster

uint64_t cipSyncConfig_t::maxOffsetFromMaster

Maximum offset between local clock and master clock

◆ meanPathDelayToMaster

int64_t cipSyncConfig_t::meanPathDelayToMaster

Mean path delay to master

◆ grandMasterClkInfo

clockClass_t cipSyncConfig_t::grandMasterClkInfo

Grand master clock info

◆ parentClkInfo

clockClass_t cipSyncConfig_t::parentClkInfo

Parent clock info

◆ localClkInfo

clockClass_t cipSyncConfig_t::localClkInfo

Local clock info

◆ numberOfPorts

uint16_t cipSyncConfig_t::numberOfPorts

Number of PTP Ports on the device. See Spec

◆ portState

port_State cipSyncConfig_t::portState[ICSS_EMAC_MAX_PORTS_PER_INSTANCE]

Status of PORT. PTP State machine values. See Spec

◆ portEnable

uint16_t cipSyncConfig_t::portEnable[ICSS_EMAC_MAX_PORTS_PER_INSTANCE]

Port Enable/Disable

◆ portLogAnnounceInterval

uint16_t cipSyncConfig_t::portLogAnnounceInterval[ICSS_EMAC_MAX_PORTS_PER_INSTANCE]

PTP announce interval between successive "Announce" messages issued by a master clock on each PTP port of the device

◆ portLogSyncInterval

uint16_t cipSyncConfig_t::portLogSyncInterval[ICSS_EMAC_MAX_PORTS_PER_INSTANCE]

specifies the PTP sync interval between successive "Sync" messages issued by a master clock on each PTP port of the device

◆ priority1

uint8_t cipSyncConfig_t::priority1

attribute allows the user to override the automatic selection of the best master clock before any quality measures are evaluated

◆ priority2

uint8_t cipSyncConfig_t::priority2

Same as above with a difference that it is used after clock is chosen

◆ domainNumber

uint8_t cipSyncConfig_t::domainNumber

Domain Number as per PTP algorithm

◆ clockType

clockType cipSyncConfig_t::clockType

Clock Type. OC, TC, BC etc

◆ manufacturerIdentity

uint8_t cipSyncConfig_t::manufacturerIdentity[4]

OUI given by IEEE

◆ productType

descr_t cipSyncConfig_t::productType

Product Type, Product description in Unicode format

◆ revData

descr_t cipSyncConfig_t::revData

Revision data of Clock, Firmware and Software. In Unicode

◆ userDesc

descr_t cipSyncConfig_t::userDesc

Description of device that contains the clock

◆ profileInfo

the PTP profile of each port of the device

◆ physInfo

Physical Address Info of each port

◆ protInfo

Protocol Address Info of each port

◆ stepsRemoved

uint16_t cipSyncConfig_t::stepsRemoved

number of communication paths traversed between the local clock and the grandmaster clock

◆ timeOffset

sysTimeOffset_t cipSyncConfig_t::timeOffset

Specifies the system time in microseconds and the Offset to the local clock value