|
| #define | ETH_VERSION_INFO_API (STD_ON) |
| | Enable/disable SPI get version info API. More...
|
| |
| #define | ETH_GLOBALTIMESUPPORT_API (STD_ON) |
| | Enable/disable Eth time sync related API. More...
|
| |
| #define | ETH_DEV_ERROR_DETECT (STD_ON) |
| | Enable/Disable Development Error Detection. More...
|
| |
| #define | ETH_GET_COUNTER_VALUES_API (STD_ON) |
| | Enable/disable Eth get counter values API. More...
|
| |
| #define | ETH_GET_RX_STATS_API (STD_ON) |
| | Enable/disable Eth get RX stats count API. More...
|
| |
| #define | ETH_GET_TX_STATS_API (STD_ON) |
| | Enable/disable Eth get TX stats count API. More...
|
| |
| #define | ETH_GET_TX_ERROR_COUNTERSVALUES_API (STD_ON) |
| | Enable/disable Eth get TX error stats count API. More...
|
| |
| #define | ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_ICMP (STD_OFF) |
| | Enable/disable Hardware Offloading for ICMP checksums. More...
|
| |
| #define | ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_IPV4 (STD_OFF) |
| | Enable/disable Hardware offloading for IPv4 Header checksums. More...
|
| |
| #define | ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_TCP (STD_OFF) |
| | Enable/disable Hardware offloading for TCP checksums. More...
|
| |
| #define | ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_UDP (STD_OFF) |
| | Enable/disable Hardware offloading for UDP checksums. More...
|
| |
| #define | ETH_ENABLE_MII_API (STD_ON) |
| | Enable/disable Eth MII related API. More...
|
| |
| #define | ETH_UPDATE_PHYS_ADDR_FILTER_API (STD_ON) |
| | Enable/disable optional API Eth_UpdatePhysAddrFilter. More...
|
| |
| #define | ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API (STD_OFF) |
| | Enable/disable optional API Eth_NotifyVirtmacMsgReceived. More...
|
| |
| #define | ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API (STD_OFF) |
| | Enable/disable optional API Eth_DispatchVirtmacSubscribeAllTraffic. More...
|
| |
| #define | ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API (STD_OFF) |
| | Enable/disable optional API Eth_DispatchVirtmacUnsubscribeAllTraffic. More...
|
| |
| #define | ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API (STD_OFF) |
| | Enable/disable optional API Eth_DispatchVirtmacSubscribeDstMac. More...
|
| |
| #define | ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API (STD_OFF) |
| | Enable/disable optional API Eth_DispatchVirtmacUnsubscribeDstMac. More...
|
| |
| #define | ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API (STD_OFF) |
| | Enable/disable optional API Eth_DispatchVirtmacAssociateIPv4Macaddr. More...
|
| |
| #define | ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API (STD_OFF) |
| | Enable/disable optional API Eth_DispatchVirtmacDisassociateIPv4Macaddr. More...
|
| |
| #define | ETH_VIRTUALMAC_ADD_UNICAST_MACADDR_API (STD_OFF) |
| | Enable/disable optional API Eth_DispatchVirtmacAddUnicastAddr. More...
|
| |
| #define | ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API (STD_OFF) |
| | Enable/disable optional API Eth_DispatchVirtmacAddMcastAddr. More...
|
| |
| #define | ETH_VIRTUALMAC_DEL_MACADDR_API (STD_OFF) |
| | Enable/disable optional API Eth_DispatchVirtmacDelAddr. More...
|
| |
| #define | ETH_VIRTUALMAC_SEND_CUSTOM_NOTIFY_API (STD_OFF) |
| | Enable/disable optional API Eth_SendCustomNotify. More...
|
| |
| #define | ETH_VIRTUALMAC_ADD_VLAN_API (STD_OFF) |
| | Enable/disable optional API Eth_DispatchVirtmacAddVlan. More...
|
| |
| #define | ETH_VIRTUALMAC_DEL_VLAN_API (STD_OFF) |
| | Enable/disable optional API Eth_DispatchVirtmacDelVlan. More...
|
| |
| #define | ETH_ISR_TYPE (ETH_ISR_CAT2) |
| | ISR type. More...
|
| |
| #define | ETH_OS_COUNTER_ID ((CounterType)OsCounter_0) |
| | Counter ID for counter used to count wait ticks. More...
|
| |
| #define | ETH_OS_COUNTER_FREQ (1000000000U) |
| | Frequency in Hz of the counter specified in ETH_OS_COUNTER_ID. More...
|
| |
| #define | ETH_VIRTUALMAC_SUPPORT (STD_OFF) |
| | Enable/disable Virtual MAC support. More...
|
| |
| #define | ETH_VIRTUALMAC_FWINFO_TIMEOUT (0U) |
| | Timeout value for Firmware Attach msg received from server. More...
|
| |
| #define | EthConf_EthCtrlConfig_EthConfig_0 (0U) |
| | Eth controller ID Configured controller ID(s) More...
|
| |
| #define | ETH_CTRL_ID_MAX (1u) |
| | Eth max controller ID. More...
|
| |
| #define | UDMA_WAIT_TEARDOWN_COUNTER (10000u) |
| | Eth DMA max teardown timeout. More...
|
| |
| #define | ETH_START_SEC_CONST_UNSPECIFIED |
| |
| #define | ETH_STOP_SEC_CONST_UNSPECIFIED |
| |
| #define | ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128 |
| |
| #define | ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128 |
| |
| #define | ETH_START_SEC_VAR_NO_INIT_8 |
| |
| #define | ETH_STOP_SEC_VAR_NO_INIT_8 |
| |
| #define | ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED |
| |
| #define | ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED |
| |
| #define | ETH_START_SEC_CODE |
| |
| #define | ETH_STOP_SEC_CODE |
| |
|
| #define | ETH_PRE_COMPILE_VARIANT (STD_ON) |
| | Eth configuration variant. More...
|
| |
| #define | ETH_LINK_TIME_VARIANT (STD_OFF) |
| |
| #define | ETH_POST_BUILD_VARIANT (STD_OFF) |
| |
|
| #define | ETH_DMA_IR_SUPPORT (STD_ON) |
| | Eth DMA feature flag support. More...
|
| |
| #define | ETH_DMA_CQ_RING_SUPPORT (STD_ON) |
| |
| #define | ETH_DMA_TEARDOWN_SUPPORT (STD_ON) |
| |
|
| #define | UDMA_DEVICE_ID_RING (235U) |
| | Eth DMA devices ID. More...
|
| |
| #define | UDMA_DEVICE_ID_UDMA (236U) |
| |
| #define | UDMA_DEVICE_ID_PSIL (232U) |
| |
| #define | UDMA_DEVICE_ID_IA (233U) |
| |
| #define | UDMA_DEVICE_ID_IR (237U) |
| |
| #define | UDMA_DEVICE_ID_CORE (250U) |
| |
|
| #define | UDMA_TX_CHANNEL_PEER_OFFSET (0xf000U) |
| | Eth DMA peer and thread offset. More...
|
| |
| #define | UDMA_RX_CHANNEL_PEER_OFFSET (0x7000U) |
| |
| #define | UDMA_SOURCE_THREAD_OFFSET (0x6000U) |
| |
| #define | UDMA_DEST_THREAD_OFFSET (0xe000U) |
| |
|
| #define | ETH_DMA_TX_BASE_REG (0x2aa00000U) |
| | Eth DMA base register address. More...
|
| |
| #define | ETH_DMA_RX_BASE_REG (0x2a800000U) |
| |
| #define | ETH_DMA_RINGRT_BASE (0x2b800000U) |
| |
| #define | ETH_DMA_RINGCFG_BASE (0x28440000U) |
| |
| #define | ETH_DMA_INTAGGR_INTR_BASE (0x2a700000U) |
| |
|
| #define | ETH_DMA_TXCRT_CHAN_CTL(CHAN) (0x00000000U + ((CHAN) * 0x1000U)) |
| | Eth DMA macro to calculate register address for DMA register address. More...
|
| |
| #define | ETH_DMA_TXCRT_CHAN_PEER8(CHAN) (0x00000220U + ((CHAN) * 0x1000U)) |
| |
| #define | ETH_DMA_RXCRT_CHAN_CTL(CHAN) (0x00000000U + ((CHAN) * 0x1000U)) |
| |
| #define | ETH_DMA_RXCRT_CHAN_PEER8(CHAN) (0x00000220U + ((CHAN) * 0x1000U)) |
| |
| #define | ETH_DMA_RINGRT_RING_FDB(RING) (0x00000010U + ((RING) * 0x1000U)) |
| |
| #define | ETH_DMA_RINGRT_RING_FOCC(RING) (0x00000018U + ((RING) * 0x1000U)) |
| |
| #define | ETH_DMA_RINGRT_RING_RDB(RING) (0x00000010U + ((RING) * 0x1000U)) |
| |
| #define | ETH_DMA_RINGRT_RING_ROCC(RING) (0x00000018U + ((RING) * 0x1000U)) |
| |
| #define | ETH_DMA_RINGCFG_RING_SIZE(RING) (0x00000048U + ((RING) * 0x100U)) |
| |
| #define | ETH_DMA_INTAGGR_INTR_VINT_ENABLE_SET(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000000U + ((VINT) * 0x1000U)) |
| |
| #define | ETH_DMA_INTAGGR_INTR_VINT_ENABLE_CLEAR(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000008U + ((VINT) * 0x1000U)) |
| |
| #define | ETH_DMA_INTAGGR_INTR_VINT_STATUS_SET(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000010U + ((VINT) * 0x1000U)) |
| |
| #define | ETH_DMA_INTAGGR_INTR_VINT_STATUS_CLEAR(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000018U + ((VINT) * 0x1000U)) |
| |
| #define | ETH_DMA_INTAGGR_INTR_VINT_STATUSM(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000020U + ((VINT) * 0x1000U)) |
| |
| #define | Eth_GetRingFDBReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FDB((RingNum))) |
| |
| #define | Eth_GetRingFOCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FOCC((RingNum))) |
| |
| #define | Eth_GetRingRDBReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_RDB((RingNum))) |
| |
| #define | Eth_GetRingROCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_ROCC((RingNum))) |
| |
| #define | Eth_GetRingSizeReg(RingNum) (ETH_DMA_RINGCFG_BASE + ETH_DMA_RINGCFG_RING_SIZE((RingNum))) |
| |
| #define | Eth_GetTxChannelCtlRegAddress(ChanId) (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_CTL((ChanId))) |
| |
| #define | Eth_GetTxChannelPeer8RegAddress(ChanId) (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_PEER8((ChanId))) |
| |
| #define | Eth_GetRxChannelCtlRegAddress(ChanId) (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_CTL((ChanId))) |
| |
| #define | Eth_GetRxChannelPeer8RegAddress(ChanId) (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_PEER8((ChanId))) |
| |
|
| #define | Eth_GetDem_E_HARDWARE_ERROR(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
| | ETH DEM Error codes to report. More...
|
| |
| #define | Eth_GetDem_E_LATECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
| |
| #define | Eth_GetDem_E_MULTIPLECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
| |
| #define | Eth_GetDem_E_SINGLECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
| |
| #define | Eth_GetDem_E_ALIGNMENT(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
| |
| #define | Eth_GetDem_E_OVERSIZEFRAME(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
| |
| #define | Eth_GetDem_E_UNDERSIZEFRAME(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
| |
| #define | Eth_GetDem_E_CRC(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
| |
| #define | Eth_GetDem_E_RX_FRAMES_LOST(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
| |
| #define | Eth_GetDem_E_ACCESS(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
| |
| #define | Eth_GetDem_E_TX_INTERNAL(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
| |
|
| #define | Eth_IsVirtualMacModeEnable(CtrlIndex) ( FALSE ) |
| | Eth function like macro to access controler configuration. More...
|
| |
| #define | Eth_GetTxChannelThreadOffset(CtrlIndex) ( 0xf000U ) |
| |
| #define | Eth_VirtMacGetEthFwRpcComChannelId(CtrlIndex) ( 0xFFFFU ) |
| |
| #define | Eth_VirtMacGetEthPollRecvMsgInEthMain(CtrlIndex) ( FALSE ) |
| |
| #define | Eth_VirtMacGetRpcCmdCompleteFuncPtr(CtrlIndex) ( (Eth_RpcCmdComplete)NULL_PTR ) |
| |
| #define | Eth_VirtMacGetFwRegisterFuncPtr(CtrlIndex) ( (Eth_RpcFwRegistered)NULL_PTR ) |
| |
| #define | Eth_GetTxEnableInterrupt(CtrlIndex) ( TRUE ) |
| |
| #define | Eth_GetRxEnableInterrupt(CtrlIndex) ( TRUE ) |
| |
| #define | Eth_GetEnetType(CtrlIndex) ( ETH_ENETTYPE_CPSW2G ) |
| |
| #define | Eth_GetMacPortNum(CtrlIndex) ( ETH_PORT_MAC_PORT_1 ) |
| |
| #define | Eth_GetMacAddressHigh(CtrlIndex) ( 0xaabbccddU ) |
| |
| #define | Eth_GetMacAddressLow(CtrlIndex) ( 0xeeffU ) |
| |
| #define | Eth_UseDefaultMacAddress(CtrlIndex) ( TRUE ) |
| |
| #define | Eth_GetMiiConnectionType(CtrlIndex) ( ETH_MAC_CONN_TYPE_RGMII_FORCE_1000_FULL ) |
| |
| #define | Eth_GetLoopBackMode(CtrlIndex) ( FALSE ) |
| |
| #define | Eth_GetHardwareLoopTimeout(CtrlIndex) ( 32000U ) |
| |
| #define | Eth_GetEnableCacheOps(CtrlIndex) ( TRUE ) |
| |
| #define | Eth_GetCacheWritebackInvalidateFuncPtr(CtrlIndex) ( &EthApp_wbInvCache ) |
| |
| #define | Eth_GetCacheWritebackFuncPtr(CtrlIndex) ( &EthApp_wbCache ) |
| |
| #define | Eth_GetCacheInvalidateFuncPtr(CtrlIndex) ( &EthApp_invCache ) |
| |
| #define | Eth_DescriptorGetCacheWritebackInvalidateFuncPtr(CtrlIndex) ( Eth_GetCacheWritebackInvalidateFuncPtr(CtrlIndex) ) |
| |
| #define | Eth_DescriptorGetCacheWritebackFuncPtr(CtrlIndex) ( Eth_GetCacheWritebackFuncPtr(CtrlIndex) ) |
| |
| #define | Eth_DescriptorGetCacheInvalidateFuncPtr(CtrlIndex) ( Eth_GetCacheInvalidateFuncPtr(CtrlIndex) ) |
| |
| #define | Eth_RingGetCacheWritebackInvalidateFuncPtr(CtrlIndex) ( Eth_GetCacheWritebackInvalidateFuncPtr(CtrlIndex) ) |
| |
| #define | Eth_RingGetCacheWritebackFuncPtr(CtrlIndex) ( Eth_GetCacheWritebackFuncPtr(CtrlIndex) ) |
| |
| #define | Eth_RingGetCacheInvalidateFuncPtr(CtrlIndex) ( Eth_GetCacheInvalidateFuncPtr(CtrlIndex) ) |
| |
| #define | Eth_Cpsw_GetPhyMacRegAddr() ( 0x40f00200U ) |
| |
| #define | Eth_Cpsw_GetAleRegAddr() ( 0x4603e000U ) |
| |
| #define | Eth_Cpsw_GetCptsRegAddr() ( 0x4603d000U ) |
| |
| #define | Eth_Cpsw_GetMdioRegAddr() ( 0x46000f00U ) |
| |
| #define | Eth_Cpsw_GetCtrlRegAddr() ( 0x46020000U ) |
| |
| #define | Eth_Cpsw_GetCptsRefClockFreq() ( 1U ) |
| |
| #define | Eth_Cpsw_GetCppiClockFreq() ( 333333333U ) |
| |
| #define | Eth_Cpsw_GetMdioBusClockFreq(CtrlIndex) ( 2200000U ) |
| |
| #define | Eth_Cpsw_GetMdioOpMode(CtrlIndex) ( ETH_MDIO_OPMODE_MANUAL ) |
| |
| #define | Eth_GetRxMtuLength(CtrlIndex) ( 1522U ) |
| |
| #define | Eth_GetTxChanStartNum(CtrlIndex) ( 30U ) |
| |
| #define | Eth_GetRxChanStartNum(CtrlIndex) ( 30U ) |
| |
| #define | Eth_GetEgressFifoTotalNum(CtrlIndex) ( 1U ) |
| |
| #define | Eth_GetIngressFifoTotalNum(CtrlIndex) ( 1U ) |
| |
| #define | Eth_GetRingTotalNum(CtrlIndex) ( 6U ) |
| |
| #define | Eth_GetTxChanTotalNum(CtrlIndex) ( 1U ) |
| |
| #define | Eth_GetRxChanTotalNum(CtrlIndex) ( 1U ) |
| |
| #define | Eth_GetFlowTotalNumber(CtrlIndex) ( 1U ) |
| |
| #define | Eth_GetEventTotalNum(CtrlIndex) ( 2U ) |
| |
| #define | Eth_GetRingEventTotalNum(CtrlIndex) ( 2U ) |
| |
| #define | Eth_GetEgressFifoPacketNum(CtrlIndex, FifoIdx) ( 128U ) |
| |
| #define | Eth_GetEgressFifoPacketSize(CtrlIndex, FifoIdx) ( 1522U ) |
| |
| #define | Eth_GetIngressFifoPacketNum(CtrlIndex, FifoIdx) ( 128U ) |
| |
| #define | Eth_GetIngressFifoPacketSize(CtrlIndex, FifoIdx) ( 1522U ) |
| |
| #define | Eth_GetEgressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)] ) |
| |
| #define | Eth_GetEgressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)].bufferInfo ) |
| |
| #define | Eth_GetEgressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_BufferMem_0[(DescIdx) * 1536U] ) |
| |
| #define | Eth_GetEgressFifoQueueAddress(CtrlIndex, FifoIdx) ( Eth_Ctrl_0_Egress_Queue_0 ) |
| |
| #define | Eth_GetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx) ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] ) |
| |
| #define | Eth_SetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val) ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] = Val ) |
| |
| #define | Eth_GetIngressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)] ) |
| |
| #define | Eth_GetIngressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)].bufferInfo ) |
| |
| #define | Eth_GetIngressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_BufferMem_0[(DescIdx) * 1536U] ) |
| |
| #define | Eth_GetIngressFifoQueueAddress(CtrlIndex, FifoIdx) ( Eth_Ctrl_0_Ingress_Queue_0 ) |
| |
| #define | Eth_GetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx) ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] ) |
| |
| #define | Eth_SetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val) ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] = Val ) |
| |
| #define | Eth_GetEgressFifoCqIdx(CtrlIndex, FifoIdx) ( 0U ) |
| |
| #define | Eth_GetEgressFifoFqIdx(CtrlIndex, FifoIdx) ( 2U ) |
| |
| #define | Eth_GetIngressFifoCqIdx(CtrlIndex, FifoIdx) ( 1U ) |
| |
| #define | Eth_GetIngressFifoFqIdx(CtrlIndex, FifoIdx) ( 3U ) |
| |
| #define | Eth_GetTxChanId(CtrlIndex, ChIdx) ( 30U ) |
| |
| #define | Eth_GetTxChanTdCqRingIdx(CtrlIndex, ChIdx) ( 4U ) |
| |
| #define | Eth_GetTxChanDepth(CtrlIndex, ChIdx) ( 128U ) |
| |
| #define | Eth_GetRxChanId(CtrlIndex, ChIdx) ( 30U ) |
| |
| #define | Eth_GetRxChanTdCqRingIdx(CtrlIndex, ChIdx) ( 5U ) |
| |
| #define | Eth_GetRxChanFlowTotalNum(CtrlIndex, ChIdx) ( 1U ) |
| |
| #define | Eth_GetRxChanFlowStartNum(CtrlIndex, ChIdx) ( 60U ) |
| |
| #define | Eth_GetFlowId(CtrlIndex, FlowIdx) ( 60U ) |
| |
| #define | Eth_GetFlowCqRingIdx(CtrlIndex, FlowIdx) ( 1U ) |
| |
| #define | Eth_GetFlowFqRingIdx(CtrlIndex, FlowIdx) ( 3U ) |
| |
| #define | Eth_GetDynRingElemAddress(CtrlIndex, RingIdx) ( &Eth_RingDyn_Ctrl_0[(RingIdx)] ) |
| |
| #define | Eth_GetRingHwId(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].hwId ) |
| |
| #define | Eth_GetRingTotalElemNum(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].size ) |
| |
| #define | Eth_GetRingPriority(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].priority ) |
| |
| #define | Eth_GetRingMemBaseAddress(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].memPtr ) |
| |
| #define | Eth_GetRingEventRingIdx(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].ringIdx ) |
| |
| #define | Eth_GetRingEventGlobalEventNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].globalEvent ) |
| |
| #define | Eth_GetRingEventVirtBitNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].virtBitNum ) |
| |
| #define | Eth_GetRingEventEventIdx(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].eventIdx ) |
| |
| #define | Eth_GetRingEventSrcOffsetNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].srcOffset ) |
| |
| #define | Eth_GetEventCoreIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].coreIntrNum ) |
| |
| #define | Eth_GetEventVirtIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].virtIntrNum ) |
| |
| #define | Eth_GetEventIrIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].IrIntrNum ) |
| |
| #define | Eth_GetTxEventCoreIntrNum(CtrlIndex) ( 80U ) |
| |
| #define | Eth_GetRxEventCoreIntrNum(CtrlIndex) ( 81U ) |
| |
| #define | Eth_GetHwTimerTotalNum(CtrlIndex) ( 0U ) |
| |
| #define | Eth_GetHwTimerId(CtrlIndex, Index) ( 0xFFU ) |
| |
| #define | Eth_GetHwTimerCounter(CtrlIndex, Index) ( 0xFFU ) |
| |
| #define | Eth_GetHwTimerIntervalMs(CtrlIndex, Index) ( 0xFFFFFFFFU ) |
| |
| #define | Eth_GetHwTimerBaseAddr(CtrlIndex, Index) ( 0xFFFFFFFFU ) |
| |
| #define | Eth_GetHwTimerDynRunningState(CtrlIndex, Index) ( FALSE ) |
| |
| #define | Eth_SetHwTimerDynRunningState(CtrlIndex, Index, Val) ( (void)(CtrlIndex) ) |
| |
| #define | Eth_GetRxIrqPacingEnable(CtrlIndex) ( FALSE ) |
| |
| #define | Eth_GetTxIrqPacingEnable(CtrlIndex) ( FALSE ) |
| |
| #define | Eth_GetRxHwTimerIdx(CtrlIndex) ( 255U ) |
| |
| #define | Eth_GetTxHwTimerIdx(CtrlIndex) ( 255U ) |
| |
| #define | Eth_GetIrqPacingEnable(CtrlIndex) ( Eth_GetTxIrqPacingEnable(CtrlIndex) || Eth_GetRxIrqPacingEnable(CtrlIndex) ) |
| |
1.8.15