metaonly interface ti.catalog.msp430.IMSP430x22xx
index URL

Common definition for MSP430x22xx devices

XDCspec summary sourced in ti/catalog/msp430/IMSP430x22xx.xdc
metaonly interface IMSP430x22xx {  ...
// inherits ti.catalog.msp430.IMSP430
    // inherits ti.catalog.ICpuDataSheet
        // inherits xdc.platform.ICpuDataSheet
instance:  ...
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
package ti.catalog.msp430;
 
metaonly interface IMSP430x22xx inherits IMSP430 {
 
instance:
per-instance config parameters
    config ADC10.Instance adc10// ;
    config Clock2xx.Instance clock// ;
    config IPlatform.Memory commonMap// Memory map elements shared by all MSP430x22xx devices[string] = [
        [
            "PERIPHERALS_8BIT",
            {
                comment: "Memory mapped I/O registers",
                name: "PERIPHERALS_8BIT",
                base: 0x0010,
                len: 0x00F0,
                space: "io",
                access: "RW"
            }
        ],
        [
            "PERIPHERALS_16BIT",
            {
                comment: "Memory mapped I/O registers",
                name: "PERIPHERALS_16BIT",
                base: 0x0100,
                len: 0x0100,
                space: "io",
                access: "RW"
            }
        ],
        [
            "BSLSKEY",
            {
                comment: "Boot loader security key",
                name: "BSLSKEY",
                base: 0xFFDE,
                len: 0x0002,
                space: "data",
                access: "RI"
            }
        ],
        [
            "INT00",
            {
                comment: "Reserved Vector (int00)",
                name: "INT00",
                base: 0xFFE0,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT01",
            {
                comment: "Reserved Vector (int01)",
                name: "INT01",
                base: 0xFFE2,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT02",
            {
                comment: "I/O Port P1 Vector (int02)",
                name: "INT02",
                base: 0xFFE4,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT03",
            {
                comment: "I/O Port P2 Vector (int03)",
                name: "INT03",
                base: 0xFFE6,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT04",
            {
                comment: "Reserved Vector (int04)",
                name: "INT04",
                base: 0xFFE8,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT05",
            {
                comment: "ADC10 Vector (int05)",
                name: "INT05",
                base: 0xFFEA,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT06",
            {
                comment: "USCI_A0/B0 Transmit Vector (int06)",
                name: "INT06",
                base: 0xFFEC,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT07",
            {
                comment: "USCI_A0/B0 Receive Vector (int07)",
                name: "INT07",
                base: 0xFFEE,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT08",
            {
                comment: "Timer_A3 TBCCR1 Vector (int08)",
                name: "INT08",
                base: 0xFFF0,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT09",
            {
                comment: "Timer_A3 TBCCR0 Vector (int09)",
                name: "INT09",
                base: 0xFFF2,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT10",
            {
                comment: "Watchdog Vector (int10)",
                name: "INT10",
                base: 0xFFF4,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT11",
            {
                comment: "Reserved Vector (int11)",
                name: "INT11",
                base: 0xFFF6,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT12",
            {
                comment: "Timer_B3 TBCCR1 Vector (int12)",
                name: "INT12",
                base: 0xFFF8,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT13",
            {
                comment: "Timer_B3 TBCCR0 Vector (int13)",
                name: "INT13",
                base: 0xFFFA,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT14",
            {
                comment: "NMI Vector (int14)",
                name: "INT14",
                base: 0xFFFC,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "RESET",
            {
                comment: "Reset Vector (int15)",
                name: "RESET",
                base: 0xFFFE,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INFOA",
            {
                comment: "INFO Flash Memory Segment A",
                name: "INFOA",
                base: 0x10C0,
                len: 0x0040,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INFOB",
            {
                comment: "INFO Flash Memory Segment B",
                name: "INFOB",
                base: 0x1080,
                len: 0x0040,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INFOC",
            {
                comment: "INFO Flash Memory Segment C",
                name: "INFOC",
                base: 0x1040,
                len: 0x0040,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INFOD",
            {
                comment: "INFO Flash Memory Segment D",
                name: "INFOD",
                base: 0x1000,
                len: 0x0040,
                space: "data",
                access: "RW"
            }
        ]
    ];
    override config String cpuCore// A string identifying the CPU Core = "MSP430";
    config String cpuCoreRevision// A string that uniquely identifies a revision of the core;
    override config Int dataWordSize// The size of an int on the target in 8-bit bytes = 2;
    config String deviceHeader// The optional header file that define device specific constants and structures;
    config Flash_2xx.Instance flash// ;
    config GPIO_MSP430x22xx.Instance gpio// ;
    config Interrupt_Controller.Instance interruptController// ;
    config IE1.Instance interruptEnableRegister1// ;
    config IE2.Instance interruptEnableRegister2// ;
    override config Int minDataUnitSize// The minimum addressable data unit size in 8-bit bytes = 1;
    override config Int minProgUnitSize// The minimum addressable program unit size in 8-bit bytes = 1;
    config OA_2.Instance oa// ;
    config IPeripheral.Instance peripherals// The map of peripherals available on the device[string];
    config Timer_A3.Instance timer_A3// ;
    config Timer_B3.Instance timer_B3// ;
    config USCI_A0_SPI_2xx.Instance usci_A0_SPI// ;
    config USCI_A0_UART_2xx.Instance usci_A0_UART// ;
    config USCI_B0_I2C_2xx.Instance usci_B0_I2C// ;
    config USCI_B0_SPI_2xx.Instance usci_B0_SPI// ;
    config WDTPlus.Instance wdtPlus// ;
per-instance creation
    create// Create an instance-object(String revision);
per-instance functions
    function getMemoryMap// Get the memory map that corresponds to the values of the specified registers(registers);
    function getRegisterSet// The set of valid register names for this CPU();
}
config IMSP430x22xx.adc10  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config ADC10.Instance adc10;
config IMSP430x22xx.clock  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config Clock2xx.Instance clock;
config IMSP430x22xx.commonMap  // instance
index URL

Memory map elements shared by all MSP430x22xx devices

XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config IPlatform.Memory commonMap[string] = [
    [
        "PERIPHERALS_8BIT",
        {
            comment: "Memory mapped I/O registers",
            name: "PERIPHERALS_8BIT",
            base: 0x0010,
            len: 0x00F0,
            space: "io",
            access: "RW"
        }
    ],
    [
        "PERIPHERALS_16BIT",
        {
            comment: "Memory mapped I/O registers",
            name: "PERIPHERALS_16BIT",
            base: 0x0100,
            len: 0x0100,
            space: "io",
            access: "RW"
        }
    ],
    [
        "BSLSKEY",
        {
            comment: "Boot loader security key",
            name: "BSLSKEY",
            base: 0xFFDE,
            len: 0x0002,
            space: "data",
            access: "RI"
        }
    ],
    [
        "INT00",
        {
            comment: "Reserved Vector (int00)",
            name: "INT00",
            base: 0xFFE0,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT01",
        {
            comment: "Reserved Vector (int01)",
            name: "INT01",
            base: 0xFFE2,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT02",
        {
            comment: "I/O Port P1 Vector (int02)",
            name: "INT02",
            base: 0xFFE4,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT03",
        {
            comment: "I/O Port P2 Vector (int03)",
            name: "INT03",
            base: 0xFFE6,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT04",
        {
            comment: "Reserved Vector (int04)",
            name: "INT04",
            base: 0xFFE8,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT05",
        {
            comment: "ADC10 Vector (int05)",
            name: "INT05",
            base: 0xFFEA,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT06",
        {
            comment: "USCI_A0/B0 Transmit Vector (int06)",
            name: "INT06",
            base: 0xFFEC,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT07",
        {
            comment: "USCI_A0/B0 Receive Vector (int07)",
            name: "INT07",
            base: 0xFFEE,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT08",
        {
            comment: "Timer_A3 TBCCR1 Vector (int08)",
            name: "INT08",
            base: 0xFFF0,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT09",
        {
            comment: "Timer_A3 TBCCR0 Vector (int09)",
            name: "INT09",
            base: 0xFFF2,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT10",
        {
            comment: "Watchdog Vector (int10)",
            name: "INT10",
            base: 0xFFF4,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT11",
        {
            comment: "Reserved Vector (int11)",
            name: "INT11",
            base: 0xFFF6,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT12",
        {
            comment: "Timer_B3 TBCCR1 Vector (int12)",
            name: "INT12",
            base: 0xFFF8,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT13",
        {
            comment: "Timer_B3 TBCCR0 Vector (int13)",
            name: "INT13",
            base: 0xFFFA,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT14",
        {
            comment: "NMI Vector (int14)",
            name: "INT14",
            base: 0xFFFC,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "RESET",
        {
            comment: "Reset Vector (int15)",
            name: "RESET",
            base: 0xFFFE,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INFOA",
        {
            comment: "INFO Flash Memory Segment A",
            name: "INFOA",
            base: 0x10C0,
            len: 0x0040,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INFOB",
        {
            comment: "INFO Flash Memory Segment B",
            name: "INFOB",
            base: 0x1080,
            len: 0x0040,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INFOC",
        {
            comment: "INFO Flash Memory Segment C",
            name: "INFOC",
            base: 0x1040,
            len: 0x0040,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INFOD",
        {
            comment: "INFO Flash Memory Segment D",
            name: "INFOD",
            base: 0x1000,
            len: 0x0040,
            space: "data",
            access: "RW"
        }
    ]
];
config IMSP430x22xx.cpuCore  // instance
index URL

A string identifying the CPU Core

XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
override config String cpuCore = "MSP430";
DETAILS
This uniquely identifies the instruction set that the CPU can decode and execute.
config IMSP430x22xx.cpuCoreRevision  // instance
index URL

A string that uniquely identifies a revision of the core

XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config String cpuCoreRevision;
config IMSP430x22xx.dataWordSize  // instance
index URL

The size of an int on the target in 8-bit bytes

XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
override config Int dataWordSize = 2;
config IMSP430x22xx.deviceHeader  // instance
index URL

The optional header file that define device specific constants and structures

XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config String deviceHeader;
config IMSP430x22xx.flash  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config Flash_2xx.Instance flash;
config IMSP430x22xx.gpio  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config GPIO_MSP430x22xx.Instance gpio;
config IMSP430x22xx.interruptController  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config Interrupt_Controller.Instance interruptController;
config IMSP430x22xx.interruptEnableRegister1  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config IE1.Instance interruptEnableRegister1;
config IMSP430x22xx.interruptEnableRegister2  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config IE2.Instance interruptEnableRegister2;
config IMSP430x22xx.minDataUnitSize  // instance
index URL

The minimum addressable data unit size in 8-bit bytes

XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
override config Int minDataUnitSize = 1;
config IMSP430x22xx.minProgUnitSize  // instance
index URL

The minimum addressable program unit size in 8-bit bytes

XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
override config Int minProgUnitSize = 1;
config IMSP430x22xx.oa  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config OA_2.Instance oa;
config IMSP430x22xx.peripherals  // instance
index URL

The map of peripherals available on the device

XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config IPeripheral.Instance peripherals[string];
config IMSP430x22xx.timer_A3  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config Timer_A3.Instance timer_A3;
config IMSP430x22xx.timer_B3  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config Timer_B3.Instance timer_B3;
config IMSP430x22xx.usci_A0_SPI  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config USCI_A0_SPI_2xx.Instance usci_A0_SPI;
config IMSP430x22xx.usci_A0_UART  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config USCI_A0_UART_2xx.Instance usci_A0_UART;
config IMSP430x22xx.usci_B0_I2C  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config USCI_B0_I2C_2xx.Instance usci_B0_I2C;
config IMSP430x22xx.usci_B0_SPI  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config USCI_B0_SPI_2xx.Instance usci_B0_SPI;
config IMSP430x22xx.wdtPlus  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
config WDTPlus.Instance wdtPlus;
Instance Creation
index URL

XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
create(String revision);
// Create an instance-object
ARGUMENTS
revision — a string that identifies revision of the CPU to be created.
DETAILS
A "data sheet" for a CPU allows one to get specific attributes for a CPU programatically; e.g., the memory map of the CPU.
Notice that we don't specify CPU registers when we create a a data-sheet; registers are provided as necessary to the other functions defined in this interface. This allows one to more easily get memory maps for several different setting of the registers, for example.
IMSP430x22xx.getMemoryMap()  // instance
index URL

Get the memory map that corresponds to the values of the specified registers

XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
function getMemoryMap(registers);
ARGUMENTS
registers — a hash of named registers to values at the time an executable is to be loaded (for example)
DETAILS
If a register is not specified and this register can affect the memory map, the register is assumed to be set to its reset value (the value of the register immediately after a CPU reset).
RETURNS
Returns an array of xdc.platform.IPlatform.Memory objects that represent the memory visible to an executable running on the CPU.
IMSP430x22xx.getRegisterSet()  // instance
index URL

The set of valid register names for this CPU

XDCspec declarations sourced in ti/catalog/msp430/IMSP430x22xx.xdc
function getRegisterSet();
DETAILS
This function returns the complete set of register names that may be passed to the getMemoryMap() function. This function is only used to enable one to write a "requires contract" for the getMemoryMap() function.
RETURNS
Returns an array of valid register names (strings) for this device; only names from this array are valid keys for the registers argument to getMemoryMap().
generated on Tue, 24 Aug 2010 15:40:36 GMT