module ti.catalog.msp430.peripherals.communication.USCI_A0_SPI

metaonly module ti.catalog.msp430.peripherals.communication.USCI_A0_SPI_2xx

index URL

Universal Serial Communication Interface A0 SPI 2xx

XDCscript usage
Individual elements

XDCscript usage meta-domain sourced in ti/catalog/msp430/peripherals/communication/USCI_A0_SPI_2xx.xdc

var USCI_A0_SPI_2xx = xdc.useModule('ti.catalog.msp430.peripherals.communication.USCI_A0_SPI_2xx');

module-wide constants & types

values of type USCI_A0_SPI_2xx.UC7BIT_t// Character length. Selects 7-bit or 8-bit character length

const USCI_A0_SPI_2xx.UC7BIT_OFF// 8-bit;

const USCI_A0_SPI_2xx.UC7BIT// 7-bit;

values of type USCI_A0_SPI_2xx.UCADDR_t// Address received in address-bit multiprocessor mode

const USCI_A0_SPI_2xx.UCADDR_OFF// Received character is data;

const USCI_A0_SPI_2xx.UCADDR// Received character is an address;

values of type USCI_A0_SPI_2xx.UCBRKIE_t// Receive break character interrupt-enable

const USCI_A0_SPI_2xx.UCBRKIE_OFF// Received break characters do not set UCAxRXIFG;

const USCI_A0_SPI_2xx.UCBRKIE// Received break characters set UCAxRXIFG;

values of type USCI_A0_SPI_2xx.UCBRK_t// Break detect flag

const USCI_A0_SPI_2xx.UCBRK_OFF// No break condition;

const USCI_A0_SPI_2xx.UCBRK// Break condition occurred;

values of type USCI_A0_SPI_2xx.UCBUSY_t// USCI busy. This bit indicates if a transmit or receive operation is in progress

const USCI_A0_SPI_2xx.UCBUSY_OFF// USCI inactive;

const USCI_A0_SPI_2xx.UCBUSY// USCI transmitting or receiving;

values of type USCI_A0_SPI_2xx.UCCKPH_t// Clock phase select

const USCI_A0_SPI_2xx.UCCKPH_OFF// Data is changed on the first UCLK edge and captured on the following edge;

const USCI_A0_SPI_2xx.UCCKPH// Data is captured on the first UCLK edge and changed on the following edge;

values of type USCI_A0_SPI_2xx.UCCKPL_t// Clock polarity select

const USCI_A0_SPI_2xx.UCCKPL_OFF// Inactive state is low;

const USCI_A0_SPI_2xx.UCCKPL// Inactive state is high;

values of type USCI_A0_SPI_2xx.UCDORM_t// Dormant. Puts USCI into sleep mode

const USCI_A0_SPI_2xx.UCDORM_OFF// Not dormant. All received characters will set UCAxRXIFG;

const USCI_A0_SPI_2xx.UCDORM// Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG;

values of type USCI_A0_SPI_2xx.UCFE_t// Framing error flag

const USCI_A0_SPI_2xx.UCFE_OFF// 0 No error;

const USCI_A0_SPI_2xx.UCFE// Character received with low stop bit;

values of type USCI_A0_SPI_2xx.UCIDLE_t// Idle line detected in idle-line multiprocessor mode

const USCI_A0_SPI_2xx.UCIDLE_OFF// No idle line detected;

const USCI_A0_SPI_2xx.UCIDLE// Idle line detected;

values of type USCI_A0_SPI_2xx.UCLISTEN_t// Listen enable. The UCLISTEN bit selects loopback mode

const USCI_A0_SPI_2xx.UCLISTEN_OFF// Disabled;

const USCI_A0_SPI_2xx.UCLISTEN// Enabled. UCAxTXD is internally fed back to the receiver;

values of type USCI_A0_SPI_2xx.UCMODE_SYNC_t// USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1

const USCI_A0_SPI_2xx.UCMODE_0// 3-Pin SPI;

const USCI_A0_SPI_2xx.UCMODE_1// 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1;

const USCI_A0_SPI_2xx.UCMODE_2// 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0;

const USCI_A0_SPI_2xx.UCMODE_3// I2C Mode;

values of type USCI_A0_SPI_2xx.UCMSB_t// MSB first select. Controls the direction of the receive and transmit shift register

const USCI_A0_SPI_2xx.UCMSB_OFF// LSB first;

const USCI_A0_SPI_2xx.UCMSB// MSB first;

values of type USCI_A0_SPI_2xx.UCMST_t// Master mode select

const USCI_A0_SPI_2xx.UCMST_OFF// Slave mode;

const USCI_A0_SPI_2xx.UCMST// Master mode;

values of type USCI_A0_SPI_2xx.UCOE_t// Overrun error flag

const USCI_A0_SPI_2xx.UCOE_OFF// No error;

const USCI_A0_SPI_2xx.UCOE// Overrun error occurred;

values of type USCI_A0_SPI_2xx.UCPE_t// Parity error flag. When UCPEN = 0, UCPE is read as 0

const USCI_A0_SPI_2xx.UCPE_OFF// No error;

const USCI_A0_SPI_2xx.UCPE// Character received with parity error;

values of type USCI_A0_SPI_2xx.UCRXEIE_t// Receive erroneous-character interrupt-enable

const USCI_A0_SPI_2xx.UCRXEIE_OFF// Erroneous characters rejected and UCAxRXIFG is not set;

const USCI_A0_SPI_2xx.UCRXEIE// Erroneous characters received will set UCAxRXIFG;

values of type USCI_A0_SPI_2xx.UCRXERR_t// Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read

const USCI_A0_SPI_2xx.UCRXERR_OFF// No receive errors detected;

const USCI_A0_SPI_2xx.UCRXERR// Receive error detected;

values of type USCI_A0_SPI_2xx.UCSSEL_SPI_t// USCI clock source select. These bits select the BRCLK source clock

const USCI_A0_SPI_2xx.UCSSEL_0// NA;

const USCI_A0_SPI_2xx.UCSSEL_1// ACLK;

const USCI_A0_SPI_2xx.UCSSEL_2// SMCLK;

values of type USCI_A0_SPI_2xx.UCSWRST_t// Software reset enable

const USCI_A0_SPI_2xx.UCSWRST_OFF// Disabled. USCI reset released for operation;

const USCI_A0_SPI_2xx.UCSWRST// Enabled. USCI logic held in reset state;

values of type USCI_A0_SPI_2xx.UCSYNC_t// Synchronous mode enable

const USCI_A0_SPI_2xx.UCSYNC_OFF// Asynchronous mode;

const USCI_A0_SPI_2xx.UCSYNC// Synchronous Mode;

values of type USCI_A0_SPI_2xx.UCTXADDR_t// Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode

const USCI_A0_SPI_2xx.UCTXADDR_OFF// Next frame transmitted is data;

const USCI_A0_SPI_2xx.UCTXADDR// Next frame transmitted is an address;

values of type USCI_A0_SPI_2xx.UCTXBRK_t// Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer

const USCI_A0_SPI_2xx.UCTXBRK_OFF// Next frame transmitted is not a break;

const USCI_A0_SPI_2xx.UCTXBRK// Next frame transmitted is a break or a break/synch;

var obj = new USCI_A0_SPI_2xx.ForceSetDefaultRegister_t// Force Set Default Register;

obj.register = String ...

obj.regForceSet = Bool ...

var obj = new USCI_A0_SPI_2xx.UCxCTL0_t// ;

obj.UCCKPH// Clock phase select. 0 Data is changed on the first UCLK edge and captured on the following edge. 1 Data is captured on the first UCLK edge and changed on the following edge = IUSCI_SPI.UCCKPH_t ...

obj.UCCKPL// Clock polarity select 0 The inactive state is low 1 The inactive state is high = IUSCI_SPI.UCCKPL_t ...

obj.UCMSB// MSB first select. Controls the direction of the receive and transmit shift register. 0 LSB first 1 MSB first = IUSCI_SPI.UCMSB_t ...

obj.UC7BIT// Character length. Selects 7-bit or 8-bit character length. 0 8-bit data 1 7-bit data = IUSCI_SPI.UC7BIT_t ...

obj.UCMST// Master mode select 0 Slave mode 1 Master mode = IUSCI_SPI.UCMST_t ...

obj.UCMODE// USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00 3-Pin SPI 01 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1 10 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0 11 I2C Mode = IUSCI_SPI.UCMODE_SYNC_t ...

obj.UCSYNC// Synchronous mode enable 0 Asynchronous mode 1 Synchronous Mode = IUSCI_SPI.UCSYNC_t ...

var obj = new USCI_A0_SPI_2xx.UCxCTL1_t// ;

obj.UCSSEL// USCI clock source select. These bits select the BRCLK source clock in master mode. UCxCLK is always used in slave mode. 00 NA 01 ACLK 10 SMCLK 11 SMCLK = IUSCI_SPI.UCSSEL_SPI_t ...

obj.UCSWRST// Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state = IUSCI_SPI.UCSWRST_t ...

var obj = new USCI_A0_SPI_2xx.UCxSTAT_t// ;

obj.UCLISTEN// Listen enable. The UCLISTEN bit selects loopback mode. 0 Disabled 1 Enabled. UCAxTXD is internally fed back to the receiver = IUSCI_SPI.UCLISTEN_t ...

obj.UCFE// Framing error flag. This bit indicates a bus conflict in 4-wire master mode. UCFE is not used in 3-wire master or any slave mode. 0 No error 1 Bus conflict occurred = IUSCI_SPI.UCFE_t ...

obj.UCOE// Overrun error flag. This bit is set when a character is transferred into UCAxRXBUF before the previous character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by software. Otherwise, it will not function correctly. 0 No error 1 Overrun error occurred = IUSCI_SPI.UCOE_t ...

obj.UCBUSY// USCI busy. This bit indicates if a transmit or receive operation is in progress. 0 USCI inactive 1 USCI transmitting or receiving = IUSCI_SPI.UCBUSY_t ...

module-wide functions

USCI_A0_SPI_2xx.addPeripheralsMap// Create a map of all peripherals available on a device(ICpuDataSheet.Instance cds) returns Void

USCI_A0_SPI_2xx.getAll// Find all peripherals of a certain type() returns IPeripheral.Instance[]

USCI_A0_SPI_2xx.getRegisters// Find all registers defined by the peripheral() returns String[]

per-instance config parameters

var params = new USCI_A0_SPI_2xx.Params// Instance config-params object;

params.UCA0BR0// Bit Rate Control Register 0 = UChar 0;

params.UCA0BR1// Bit Rate Control Register 1 = UChar 0;

params.UCA0CTL0// Control Register 0 = IUSCI_A0_SPI.UCxCTL0_t {

UCCKPH: IUSCI_SPI.UCCKPH_OFF,

UCCKPL: IUSCI_SPI.UCCKPL_OFF,

UCMSB: IUSCI.UCMSB_OFF,

UC7BIT: IUSCI.UC7BIT_OFF,

UCMST: IUSCI_SPI.UCMST_OFF,

UCMODE: IUSCI.UCMODE_0,

UCSYNC: IUSCI.UCSYNC

};

params.UCA0CTL1// Control Register 1 = IUSCI_A0_SPI.UCxCTL1_t {

UCSSEL: IUSCI_SPI.UCSSEL_0,

UCSWRST: IUSCI.UCSWRST

};

params.UCA0RXBUF// Receive Buffer Register = UChar 0;

params.UCA0STAT// Status Register = IUSCI_A0_SPI.UCxSTAT_t {

UCLISTEN: IUSCI.UCLISTEN_OFF,

UCFE: IUSCI.UCFE_OFF,

UCOE: IUSCI.UCOE_OFF,

UCBUSY: IUSCI.UCBUSY

};

params.UCA0TXBUF// Transmit Buffer Register = UChar 0;

params.UCLKHz// Stores the UCLK external clock frequency in float = Float 1000000;

params.forceSetDefaultRegister// Determine if each Register needs to be forced set or not = USCI_A0_SPI_2xx.ForceSetDefaultRegister_t[] [

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

params.name// Specific peripheral name given by the device = String undefined;

params.owner// String specifying the entity that manages the peripheral = String undefined;

per-instance creation

var inst = USCI_A0_SPI_2xx.create// Create an instance-object(IClock.Instance clock, IE2.Instance interruptEnableRegister2, params);

per-instance functions

inst.getUCRXIE// () returns Bool

inst.getUCTXIE// () returns Bool

inst.setUCRXIE// (Bool set) returns Bool

inst.setUCTXIE// (Bool set) returns Bool

enum USCI_A0_SPI_2xx.UC7BIT_t

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Character length. Selects 7-bit or 8-bit character length

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UC7BIT_t

const USCI_A0_SPI_2xx.UC7BIT_OFF;

// 8-bit

const USCI_A0_SPI_2xx.UC7BIT;

// 7-bit

enum USCI_A0_SPI_2xx.UCADDR_t

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Address received in address-bit multiprocessor mode

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCADDR_t

const USCI_A0_SPI_2xx.UCADDR_OFF;

// Received character is data

const USCI_A0_SPI_2xx.UCADDR;

// Received character is an address

enum USCI_A0_SPI_2xx.UCBRKIE_t

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Receive break character interrupt-enable

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCBRKIE_t

const USCI_A0_SPI_2xx.UCBRKIE_OFF;

// Received break characters do not set UCAxRXIFG

const USCI_A0_SPI_2xx.UCBRKIE;

// Received break characters set UCAxRXIFG

enum USCI_A0_SPI_2xx.UCBRK_t

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Break detect flag

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCBRK_t

const USCI_A0_SPI_2xx.UCBRK_OFF;

// No break condition

const USCI_A0_SPI_2xx.UCBRK;

// Break condition occurred

enum USCI_A0_SPI_2xx.UCBUSY_t

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USCI busy. This bit indicates if a transmit or receive operation is in progress

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCBUSY_t

const USCI_A0_SPI_2xx.UCBUSY_OFF;

// USCI inactive

const USCI_A0_SPI_2xx.UCBUSY;

// USCI transmitting or receiving

enum USCI_A0_SPI_2xx.UCCKPH_t

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Clock phase select

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCCKPH_t

const USCI_A0_SPI_2xx.UCCKPH_OFF;

// Data is changed on the first UCLK edge and captured on the following edge

const USCI_A0_SPI_2xx.UCCKPH;

// Data is captured on the first UCLK edge and changed on the following edge

enum USCI_A0_SPI_2xx.UCCKPL_t

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Clock polarity select

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCCKPL_t

const USCI_A0_SPI_2xx.UCCKPL_OFF;

// Inactive state is low

const USCI_A0_SPI_2xx.UCCKPL;

// Inactive state is high

enum USCI_A0_SPI_2xx.UCDORM_t

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Dormant. Puts USCI into sleep mode

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCDORM_t

const USCI_A0_SPI_2xx.UCDORM_OFF;

// Not dormant. All received characters will set UCAxRXIFG

const USCI_A0_SPI_2xx.UCDORM;

// Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG

enum USCI_A0_SPI_2xx.UCFE_t

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Framing error flag

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCFE_t

const USCI_A0_SPI_2xx.UCFE_OFF;

// 0 No error

const USCI_A0_SPI_2xx.UCFE;

// Character received with low stop bit

enum USCI_A0_SPI_2xx.UCIDLE_t

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Idle line detected in idle-line multiprocessor mode

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCIDLE_t

const USCI_A0_SPI_2xx.UCIDLE_OFF;

// No idle line detected

const USCI_A0_SPI_2xx.UCIDLE;

// Idle line detected

enum USCI_A0_SPI_2xx.UCLISTEN_t

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Listen enable. The UCLISTEN bit selects loopback mode

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCLISTEN_t

const USCI_A0_SPI_2xx.UCLISTEN_OFF;

// Disabled

const USCI_A0_SPI_2xx.UCLISTEN;

// Enabled. UCAxTXD is internally fed back to the receiver

enum USCI_A0_SPI_2xx.UCMODE_SYNC_t

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USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCMODE_SYNC_t

const USCI_A0_SPI_2xx.UCMODE_0;

// 3-Pin SPI

const USCI_A0_SPI_2xx.UCMODE_1;

// 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1

const USCI_A0_SPI_2xx.UCMODE_2;

// 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0

const USCI_A0_SPI_2xx.UCMODE_3;

// I2C Mode

enum USCI_A0_SPI_2xx.UCMSB_t

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MSB first select. Controls the direction of the receive and transmit shift register

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCMSB_t

const USCI_A0_SPI_2xx.UCMSB_OFF;

// LSB first

const USCI_A0_SPI_2xx.UCMSB;

// MSB first

enum USCI_A0_SPI_2xx.UCMST_t

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Master mode select

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCMST_t

const USCI_A0_SPI_2xx.UCMST_OFF;

// Slave mode

const USCI_A0_SPI_2xx.UCMST;

// Master mode

enum USCI_A0_SPI_2xx.UCOE_t

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Overrun error flag

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCOE_t

const USCI_A0_SPI_2xx.UCOE_OFF;

// No error

const USCI_A0_SPI_2xx.UCOE;

// Overrun error occurred

enum USCI_A0_SPI_2xx.UCPE_t

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Parity error flag. When UCPEN = 0, UCPE is read as 0

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCPE_t

const USCI_A0_SPI_2xx.UCPE_OFF;

// No error

const USCI_A0_SPI_2xx.UCPE;

// Character received with parity error

enum USCI_A0_SPI_2xx.UCRXEIE_t

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Receive erroneous-character interrupt-enable

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCRXEIE_t

const USCI_A0_SPI_2xx.UCRXEIE_OFF;

// Erroneous characters rejected and UCAxRXIFG is not set

const USCI_A0_SPI_2xx.UCRXEIE;

// Erroneous characters received will set UCAxRXIFG

enum USCI_A0_SPI_2xx.UCRXERR_t

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Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCRXERR_t

const USCI_A0_SPI_2xx.UCRXERR_OFF;

// No receive errors detected

const USCI_A0_SPI_2xx.UCRXERR;

// Receive error detected

enum USCI_A0_SPI_2xx.UCSSEL_SPI_t

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USCI clock source select. These bits select the BRCLK source clock

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCSSEL_SPI_t

const USCI_A0_SPI_2xx.UCSSEL_0;

// NA

const USCI_A0_SPI_2xx.UCSSEL_1;

// ACLK

const USCI_A0_SPI_2xx.UCSSEL_2;

// SMCLK

enum USCI_A0_SPI_2xx.UCSWRST_t

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Software reset enable

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCSWRST_t

const USCI_A0_SPI_2xx.UCSWRST_OFF;

// Disabled. USCI reset released for operation

const USCI_A0_SPI_2xx.UCSWRST;

// Enabled. USCI logic held in reset state

enum USCI_A0_SPI_2xx.UCSYNC_t

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Synchronous mode enable

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCSYNC_t

const USCI_A0_SPI_2xx.UCSYNC_OFF;

// Asynchronous mode

const USCI_A0_SPI_2xx.UCSYNC;

// Synchronous Mode

enum USCI_A0_SPI_2xx.UCTXADDR_t

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Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCTXADDR_t

const USCI_A0_SPI_2xx.UCTXADDR_OFF;

// Next frame transmitted is data

const USCI_A0_SPI_2xx.UCTXADDR;

// Next frame transmitted is an address

enum USCI_A0_SPI_2xx.UCTXBRK_t

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Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer

XDCscript usage meta-domain

values of type USCI_A0_SPI_2xx.UCTXBRK_t

const USCI_A0_SPI_2xx.UCTXBRK_OFF;

// Next frame transmitted is not a break

const USCI_A0_SPI_2xx.UCTXBRK;

// Next frame transmitted is a break or a break/synch

struct USCI_A0_SPI_2xx.ForceSetDefaultRegister_t

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Force Set Default Register

XDCscript usage meta-domain

var obj = new USCI_A0_SPI_2xx.ForceSetDefaultRegister_t;

obj.register = String ...

obj.regForceSet = Bool ...

DETAILS

Type to store if each register needs to be forced initialized even if the register is in default state.

SEE

ForceSetDefaultRegister_t

struct USCI_A0_SPI_2xx.UCxCTL0_t

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XDCscript usage meta-domain

var obj = new USCI_A0_SPI_2xx.UCxCTL0_t;

obj.UCCKPH = IUSCI_SPI.UCCKPH_t ...

// Clock phase select. 0 Data is changed on the first UCLK edge and captured on the following edge. 1 Data is captured on the first UCLK edge and changed on the following edge

obj.UCCKPL = IUSCI_SPI.UCCKPL_t ...

// Clock polarity select 0 The inactive state is low 1 The inactive state is high

obj.UCMSB = IUSCI_SPI.UCMSB_t ...

// MSB first select. Controls the direction of the receive and transmit shift register. 0 LSB first 1 MSB first

obj.UC7BIT = IUSCI_SPI.UC7BIT_t ...

// Character length. Selects 7-bit or 8-bit character length. 0 8-bit data 1 7-bit data

obj.UCMST = IUSCI_SPI.UCMST_t ...

// Master mode select 0 Slave mode 1 Master mode

obj.UCMODE = IUSCI_SPI.UCMODE_SYNC_t ...

// USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00 3-Pin SPI 01 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1 10 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0 11 I2C Mode

obj.UCSYNC = IUSCI_SPI.UCSYNC_t ...

// Synchronous mode enable 0 Asynchronous mode 1 Synchronous Mode

struct USCI_A0_SPI_2xx.UCxCTL1_t

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XDCscript usage meta-domain

var obj = new USCI_A0_SPI_2xx.UCxCTL1_t;

obj.UCSSEL = IUSCI_SPI.UCSSEL_SPI_t ...

// USCI clock source select. These bits select the BRCLK source clock in master mode. UCxCLK is always used in slave mode. 00 NA 01 ACLK 10 SMCLK 11 SMCLK

obj.UCSWRST = IUSCI_SPI.UCSWRST_t ...

// Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state

struct USCI_A0_SPI_2xx.UCxSTAT_t

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XDCscript usage meta-domain

var obj = new USCI_A0_SPI_2xx.UCxSTAT_t;

obj.UCLISTEN = IUSCI_SPI.UCLISTEN_t ...

// Listen enable. The UCLISTEN bit selects loopback mode. 0 Disabled 1 Enabled. UCAxTXD is internally fed back to the receiver

obj.UCFE = IUSCI_SPI.UCFE_t ...

// Framing error flag. This bit indicates a bus conflict in 4-wire master mode. UCFE is not used in 3-wire master or any slave mode. 0 No error 1 Bus conflict occurred

obj.UCOE = IUSCI_SPI.UCOE_t ...

// Overrun error flag. This bit is set when a character is transferred into UCAxRXBUF before the previous character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by software. Otherwise, it will not function correctly. 0 No error 1 Overrun error occurred

obj.UCBUSY = IUSCI_SPI.UCBUSY_t ...

// USCI busy. This bit indicates if a transmit or receive operation is in progress. 0 USCI inactive 1 USCI transmitting or receiving

USCI_A0_SPI_2xx.addPeripheralsMap() // module-wide

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Create a map of all peripherals available on a device

XDCscript usage meta-domain

USCI_A0_SPI_2xx.addPeripheralsMap(ICpuDataSheet.Instance cds) returns Void

ARGUMENTS

cds — an xdc.platform.ICpuDataSheet instance

DETAILS

The config parameter peripherals is by default undefined in an xdc.platform.ICpuDataSheet instance. This function gathers all instance configuration parameters that are of the type xdc.platform.IPeripheral into the map peripherals.

USCI_A0_SPI_2xx.getAll() // module-wide

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Find all peripherals of a certain type

XDCscript usage meta-domain

USCI_A0_SPI_2xx.getAll() returns IPeripheral.Instance[]

DETAILS

The type of the peripherals returned is defined by the type of the caller.

RETURNS

Returns an array of IPeripheral instances

USCI_A0_SPI_2xx.getRegisters() // module-wide

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Find all registers defined by the peripheral

XDCscript usage meta-domain

USCI_A0_SPI_2xx.getRegisters() returns String[]

RETURNS

Returns an array of register names

Instance Config Parameters

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XDCscript usage meta-domain

var params = new USCI_A0_SPI_2xx.Params;

// Instance config-params object

params.UCA0BR0 = UChar 0;

// Bit Rate Control Register 0

params.UCA0BR1 = UChar 0;

// Bit Rate Control Register 1

params.UCA0CTL0 = IUSCI_A0_SPI.UCxCTL0_t {

// Control Register 0

UCCKPH: IUSCI_SPI.UCCKPH_OFF,

UCCKPL: IUSCI_SPI.UCCKPL_OFF,

UCMSB: IUSCI.UCMSB_OFF,

UC7BIT: IUSCI.UC7BIT_OFF,

UCMST: IUSCI_SPI.UCMST_OFF,

UCMODE: IUSCI.UCMODE_0,

UCSYNC: IUSCI.UCSYNC

};

params.UCA0CTL1 = IUSCI_A0_SPI.UCxCTL1_t {

// Control Register 1

UCSSEL: IUSCI_SPI.UCSSEL_0,

UCSWRST: IUSCI.UCSWRST

};

params.UCA0RXBUF = UChar 0;

// Receive Buffer Register

params.UCA0STAT = IUSCI_A0_SPI.UCxSTAT_t {

// Status Register

UCLISTEN: IUSCI.UCLISTEN_OFF,

UCFE: IUSCI.UCFE_OFF,

UCOE: IUSCI.UCOE_OFF,

UCBUSY: IUSCI.UCBUSY

};

params.UCA0TXBUF = UChar 0;

// Transmit Buffer Register

params.UCLKHz = Float 1000000;

// Stores the UCLK external clock frequency in float

params.forceSetDefaultRegister = USCI_A0_SPI_2xx.ForceSetDefaultRegister_t[] [

// Determine if each Register needs to be forced set or not

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

params.name = String undefined;

// Specific peripheral name given by the device

params.owner = String undefined;

// String specifying the entity that manages the peripheral

config USCI_A0_SPI_2xx.UCA0BR0 // instance

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Bit Rate Control Register 0

XDCscript usage meta-domain

var params = new USCI_A0_SPI_2xx.Params;

...

params.UCA0BR0 = UChar 0;

config USCI_A0_SPI_2xx.UCA0BR1 // instance

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Bit Rate Control Register 1

XDCscript usage meta-domain

var params = new USCI_A0_SPI_2xx.Params;

...

params.UCA0BR1 = UChar 0;

config USCI_A0_SPI_2xx.UCA0CTL0 // instance

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Control Register 0

XDCscript usage meta-domain

var params = new USCI_A0_SPI_2xx.Params;

...

params.UCA0CTL0 = IUSCI_A0_SPI.UCxCTL0_t {

UCCKPH: IUSCI_SPI.UCCKPH_OFF,

UCCKPL: IUSCI_SPI.UCCKPL_OFF,

UCMSB: IUSCI.UCMSB_OFF,

UC7BIT: IUSCI.UC7BIT_OFF,

UCMST: IUSCI_SPI.UCMST_OFF,

UCMODE: IUSCI.UCMODE_0,

UCSYNC: IUSCI.UCSYNC

};

config USCI_A0_SPI_2xx.UCA0CTL1 // instance

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Control Register 1

XDCscript usage meta-domain

var params = new USCI_A0_SPI_2xx.Params;

...

params.UCA0CTL1 = IUSCI_A0_SPI.UCxCTL1_t {

UCSSEL: IUSCI_SPI.UCSSEL_0,

UCSWRST: IUSCI.UCSWRST

};

config USCI_A0_SPI_2xx.UCA0RXBUF // instance

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Receive Buffer Register

XDCscript usage meta-domain

var params = new USCI_A0_SPI_2xx.Params;

...

params.UCA0RXBUF = UChar 0;

config USCI_A0_SPI_2xx.UCA0STAT // instance

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Status Register

XDCscript usage meta-domain

var params = new USCI_A0_SPI_2xx.Params;

...

params.UCA0STAT = IUSCI_A0_SPI.UCxSTAT_t {

UCLISTEN: IUSCI.UCLISTEN_OFF,

UCFE: IUSCI.UCFE_OFF,

UCOE: IUSCI.UCOE_OFF,

UCBUSY: IUSCI.UCBUSY

};

config USCI_A0_SPI_2xx.UCA0TXBUF // instance

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Transmit Buffer Register

XDCscript usage meta-domain

var params = new USCI_A0_SPI_2xx.Params;

...

params.UCA0TXBUF = UChar 0;

config USCI_A0_SPI_2xx.UCLKHz // instance

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Stores the UCLK external clock frequency in float

XDCscript usage meta-domain

var params = new USCI_A0_SPI_2xx.Params;

...

params.UCLKHz = Float 1000000;

config USCI_A0_SPI_2xx.forceSetDefaultRegister // instance

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Determine if each Register needs to be forced set or not

XDCscript usage meta-domain

var params = new USCI_A0_SPI_2xx.Params;

...

const params.forceSetDefaultRegister = USCI_A0_SPI_2xx.ForceSetDefaultRegister_t[] [

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

config USCI_A0_SPI_2xx.name // instance

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Specific peripheral name given by the device

XDCscript usage meta-domain

var params = new USCI_A0_SPI_2xx.Params;

...

params.name = String undefined;

DETAILS

Devices can have more than one peripheral of the same type. In such cases, device data sheets give different names to the instances of a same peripheral. For example, the name for a timer module could be TimerA3, and a device that has two such timers can name them TA0 and TA1.

config USCI_A0_SPI_2xx.owner // instance

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String specifying the entity that manages the peripheral

XDCscript usage meta-domain

var params = new USCI_A0_SPI_2xx.Params;

...

params.owner = String undefined;

Instance Creation

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XDCscript usage meta-domain

var params = new USCI_A0_SPI_2xx.Params;

// Allocate instance config-params