metaonly interface ti.catalog.msp430.peripherals.communication.IUSCI_SPI
index URL

Universal Serial Communication Interface

XDCspec summary sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
metaonly interface IUSCI_SPI {  ...
// inherits ti.catalog.msp430.peripherals.communication.IUSCI
    // inherits xdc.platform.IPeripheral
instance:  ...
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
package ti.catalog.msp430.peripherals.communication;
 
metaonly interface IUSCI_SPI inherits IUSCI {
module-wide constants & types
    enum UC7BIT_t// Character length. Selects 7-bit or 8-bit character length {
        UC7BIT_OFF// 8-bit,
        UC7BIT// 7-bit
    };
    enum UCADDR_t// Address received in address-bit multiprocessor mode {
        UCADDR_OFF// Received character is data,
        UCADDR// Received character is an address
    };
    enum UCBRKIE_t// Receive break character interrupt-enable {
        UCBRKIE_OFF// Received break characters do not set UCAxRXIFG,
        UCBRKIE// Received break characters set UCAxRXIFG
    };
    enum UCBRK_t// Break detect flag {
        UCBRK_OFF// No break condition,
        UCBRK// Break condition occurred
    };
    enum UCBUSY_t// USCI busy. This bit indicates if a transmit or receive operation is in progress {
        UCBUSY_OFF// USCI inactive,
        UCBUSY// USCI transmitting or receiving
    };
    enum UCCKPH_t// Clock phase select {
        UCCKPH_OFF// Data is changed on the first UCLK edge and captured on the following edge,
        UCCKPH// Data is captured on the first UCLK edge and changed on the following edge
    };
    enum UCCKPL_t// Clock polarity select {
        UCCKPL_OFF// Inactive state is low,
        UCCKPL// Inactive state is high
    };
    enum UCDORM_t// Dormant. Puts USCI into sleep mode {
        UCDORM_OFF// Not dormant. All received characters will set UCAxRXIFG,
        UCDORM// Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG
    };
    enum UCFE_t// Framing error flag {
        UCFE_OFF// 0 No error,
        UCFE// Character received with low stop bit
    };
    enum UCIDLE_t// Idle line detected in idle-line multiprocessor mode {
        UCIDLE_OFF// No idle line detected,
        UCIDLE// Idle line detected
    };
    enum UCLISTEN_t// Listen enable. The UCLISTEN bit selects loopback mode {
        UCLISTEN_OFF// Disabled,
        UCLISTEN// Enabled. UCAxTXD is internally fed back to the receiver
    };
    enum UCMODE_SYNC_t// USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1 {
        UCMODE_0// 3-Pin SPI,
        UCMODE_1// 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1,
        UCMODE_2// 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0,
        UCMODE_3// I2C Mode
    };
    enum UCMSB_t// MSB first select. Controls the direction of the receive and transmit shift register {
        UCMSB_OFF// LSB first,
        UCMSB// MSB first
    };
    enum UCMST_t// Master mode select {
        UCMST_OFF// Slave mode,
        UCMST// Master mode
    };
    enum UCOE_t// Overrun error flag {
        UCOE_OFF// No error,
        UCOE// Overrun error occurred
    };
    enum UCPE_t// Parity error flag. When UCPEN = 0, UCPE is read as 0 {
        UCPE_OFF// No error,
        UCPE// Character received with parity error
    };
    enum UCRXEIE_t// Receive erroneous-character interrupt-enable {
        UCRXEIE_OFF// Erroneous characters rejected and UCAxRXIFG is not set,
        UCRXEIE// Erroneous characters received will set UCAxRXIFG
    };
    enum UCRXERR_t// Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read {
        UCRXERR_OFF// No receive errors detected,
        UCRXERR// Receive error detected
    };
    enum UCSSEL_SPI_t// USCI clock source select. These bits select the BRCLK source clock {
        UCSSEL_0// NA,
        UCSSEL_1// ACLK,
        UCSSEL_2// SMCLK
    };
    enum UCSWRST_t// Software reset enable {
        UCSWRST_OFF// Disabled. USCI reset released for operation,
        UCSWRST// Enabled. USCI logic held in reset state
    };
    enum UCSYNC_t// Synchronous mode enable {
        UCSYNC_OFF// Asynchronous mode,
        UCSYNC// Synchronous Mode
    };
    enum UCTXADDR_t// Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode {
        UCTXADDR_OFF// Next frame transmitted is data,
        UCTXADDR// Next frame transmitted is an address
    };
    enum UCTXBRK_t// Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer {
        UCTXBRK_OFF// Next frame transmitted is not a break,
        UCTXBRK// Next frame transmitted is a break or a break/synch
    };
    typedef IPeripheral.Instance IPeripheralArray// [];
    typedef String StringArray// [];
    metaonly struct ForceSetDefaultRegister_t// Force Set Default Register {
        String register;
        Bool regForceSet;
    };
    metaonly struct UCxCTL0_t//  {
        IUSCI_SPI.UCCKPH_t UCCKPH// Clock phase select. 0 Data is changed on the first UCLK edge and captured on the following edge. 1 Data is captured on the first UCLK edge and changed on the following edge;
        IUSCI_SPI.UCCKPL_t UCCKPL// Clock polarity select 0 The inactive state is low 1 The inactive state is high;
        IUSCI_SPI.UCMSB_t UCMSB// MSB first select. Controls the direction of the receive and transmit shift register. 0 LSB first 1 MSB first;
        IUSCI_SPI.UC7BIT_t UC7BIT// Character length. Selects 7-bit or 8-bit character length. 0 8-bit data 1 7-bit data;
        IUSCI_SPI.UCMST_t UCMST// Master mode select 0 Slave mode 1 Master mode;
        IUSCI_SPI.UCMODE_SYNC_t UCMODE// USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00 3-Pin SPI 01 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1 10 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0 11 I2C Mode;
        IUSCI_SPI.UCSYNC_t UCSYNC// Synchronous mode enable 0 Asynchronous mode 1 Synchronous Mode;
    };
    metaonly struct UCxCTL1_t//  {
        IUSCI_SPI.UCSSEL_SPI_t UCSSEL// USCI clock source select. These bits select the BRCLK source clock in master mode. UCxCLK is always used in slave mode. 00 NA 01 ACLK 10 SMCLK 11 SMCLK;
        IUSCI_SPI.UCSWRST_t UCSWRST// Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state;
    };
    metaonly struct UCxSTAT_t//  {
        IUSCI_SPI.UCLISTEN_t UCLISTEN// Listen enable. The UCLISTEN bit selects loopback mode. 0 Disabled 1 Enabled. UCAxTXD is internally fed back to the receiver;
        IUSCI_SPI.UCFE_t UCFE// Framing error flag. This bit indicates a bus conflict in 4-wire master mode. UCFE is not used in 3-wire master or any slave mode. 0 No error 1 Bus conflict occurred;
        IUSCI_SPI.UCOE_t UCOE// Overrun error flag. This bit is set when a character is transferred into UCAxRXBUF before the previous character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by software. Otherwise, it will not function correctly. 0 No error 1 Overrun error occurred;
        IUSCI_SPI.UCBUSY_t UCBUSY// USCI busy. This bit indicates if a transmit or receive operation is in progress. 0 USCI inactive 1 USCI transmitting or receiving;
    };
module-wide functions
    Void addPeripheralsMap// Create a map of all peripherals available on a device(ICpuDataSheet.Instance cds);
    IPeripheral.IPeripheralArray getAll// Find all peripherals of a certain type();
    IPeripheral.StringArray getRegisters// Find all registers defined by the peripheral();
 
instance:
per-instance config parameters
    config Float UCLKHz// Stores the UCLK external clock frequency in float = 1000000;
    config String name// Specific peripheral name given by the device;
    config String owner// String specifying the entity that manages the peripheral;
per-instance functions
    Bool getUCRXIE// ();
    Bool getUCTXIE// ();
    Bool setUCRXIE// (Bool set);
    Bool setUCTXIE// (Bool set);
}
enum IUSCI_SPI.UC7BIT_t
index URL

Character length. Selects 7-bit or 8-bit character length

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UC7BIT_t {
    UC7BIT_OFF,
    // 8-bit
    UC7BIT
    // 7-bit
};
enum IUSCI_SPI.UCADDR_t
index URL

Address received in address-bit multiprocessor mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCADDR_t {
    UCADDR_OFF,
    // Received character is data
    UCADDR
    // Received character is an address
};
enum IUSCI_SPI.UCBRKIE_t
index URL

Receive break character interrupt-enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCBRKIE_t {
    UCBRKIE_OFF,
    // Received break characters do not set UCAxRXIFG
    UCBRKIE
    // Received break characters set UCAxRXIFG
};
enum IUSCI_SPI.UCBRK_t
index URL

Break detect flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCBRK_t {
    UCBRK_OFF,
    // No break condition
    UCBRK
    // Break condition occurred
};
enum IUSCI_SPI.UCBUSY_t
index URL

USCI busy. This bit indicates if a transmit or receive operation is in progress

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCBUSY_t {
    UCBUSY_OFF,
    // USCI inactive
    UCBUSY
    // USCI transmitting or receiving
};
enum IUSCI_SPI.UCCKPH_t
index URL

Clock phase select

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCCKPH_t {
    UCCKPH_OFF,
    // Data is changed on the first UCLK edge and captured on the following edge
    UCCKPH
    // Data is captured on the first UCLK edge and changed on the following edge
};
enum IUSCI_SPI.UCCKPL_t
index URL

Clock polarity select

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCCKPL_t {
    UCCKPL_OFF,
    // Inactive state is low
    UCCKPL
    // Inactive state is high
};
enum IUSCI_SPI.UCDORM_t
index URL

Dormant. Puts USCI into sleep mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCDORM_t {
    UCDORM_OFF,
    // Not dormant. All received characters will set UCAxRXIFG
    UCDORM
    // Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG
};
enum IUSCI_SPI.UCFE_t
index URL

Framing error flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCFE_t {
    UCFE_OFF,
    // 0 No error
    UCFE
    // Character received with low stop bit
};
enum IUSCI_SPI.UCIDLE_t
index URL

Idle line detected in idle-line multiprocessor mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCIDLE_t {
    UCIDLE_OFF,
    // No idle line detected
    UCIDLE
    // Idle line detected
};
enum IUSCI_SPI.UCLISTEN_t
index URL

Listen enable. The UCLISTEN bit selects loopback mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCLISTEN_t {
    UCLISTEN_OFF,
    // Disabled
    UCLISTEN
    // Enabled. UCAxTXD is internally fed back to the receiver
};
enum IUSCI_SPI.UCMODE_SYNC_t
index URL

USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCMODE_SYNC_t {
    UCMODE_0,
    // 3-Pin SPI
    UCMODE_1,
    // 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
    UCMODE_2,
    // 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
    UCMODE_3
    // I2C Mode
};
enum IUSCI_SPI.UCMSB_t
index URL

MSB first select. Controls the direction of the receive and transmit shift register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCMSB_t {
    UCMSB_OFF,
    // LSB first
    UCMSB
    // MSB first
};
enum IUSCI_SPI.UCMST_t
index URL

Master mode select

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCMST_t {
    UCMST_OFF,
    // Slave mode
    UCMST
    // Master mode
};
enum IUSCI_SPI.UCOE_t
index URL

Overrun error flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCOE_t {
    UCOE_OFF,
    // No error
    UCOE
    // Overrun error occurred
};
enum IUSCI_SPI.UCPE_t
index URL

Parity error flag. When UCPEN = 0, UCPE is read as 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCPE_t {
    UCPE_OFF,
    // No error
    UCPE
    // Character received with parity error
};
enum IUSCI_SPI.UCRXEIE_t
index URL

Receive erroneous-character interrupt-enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCRXEIE_t {
    UCRXEIE_OFF,
    // Erroneous characters rejected and UCAxRXIFG is not set
    UCRXEIE
    // Erroneous characters received will set UCAxRXIFG
};
enum IUSCI_SPI.UCRXERR_t
index URL

Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCRXERR_t {
    UCRXERR_OFF,
    // No receive errors detected
    UCRXERR
    // Receive error detected
};
enum IUSCI_SPI.UCSSEL_SPI_t
index URL

USCI clock source select. These bits select the BRCLK source clock

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCSSEL_SPI_t {
    UCSSEL_0,
    // NA
    UCSSEL_1,
    // ACLK
    UCSSEL_2
    // SMCLK
};
enum IUSCI_SPI.UCSWRST_t
index URL

Software reset enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCSWRST_t {
    UCSWRST_OFF,
    // Disabled. USCI reset released for operation
    UCSWRST
    // Enabled. USCI logic held in reset state
};
enum IUSCI_SPI.UCSYNC_t
index URL

Synchronous mode enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCSYNC_t {
    UCSYNC_OFF,
    // Asynchronous mode
    UCSYNC
    // Synchronous Mode
};
enum IUSCI_SPI.UCTXADDR_t
index URL

Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCTXADDR_t {
    UCTXADDR_OFF,
    // Next frame transmitted is data
    UCTXADDR
    // Next frame transmitted is an address
};
enum IUSCI_SPI.UCTXBRK_t
index URL

Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
enum UCTXBRK_t {
    UCTXBRK_OFF,
    // Next frame transmitted is not a break
    UCTXBRK
    // Next frame transmitted is a break or a break/synch
};
typedef IUSCI_SPI.IPeripheralArray
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
typedef IPeripheral.Instance IPeripheralArray[];
typedef IUSCI_SPI.StringArray
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
typedef String StringArray[];
struct IUSCI_SPI.ForceSetDefaultRegister_t
index URL

Force Set Default Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
metaonly struct ForceSetDefaultRegister_t {
    String register;
    Bool regForceSet;
};
DETAILS
Type to store if each register needs to be forced initialized even if the register is in default state.
SEE
ForceSetDefaultRegister_t
struct IUSCI_SPI.UCxCTL0_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
metaonly struct UCxCTL0_t {
    IUSCI_SPI.UCCKPH_t UCCKPH;
    // Clock phase select. 0 Data is changed on the first UCLK edge and captured on the following edge. 1 Data is captured on the first UCLK edge and changed on the following edge
    IUSCI_SPI.UCCKPL_t UCCKPL;
    // Clock polarity select 0 The inactive state is low 1 The inactive state is high
    IUSCI_SPI.UCMSB_t UCMSB;
    // MSB first select. Controls the direction of the receive and transmit shift register. 0 LSB first 1 MSB first
    IUSCI_SPI.UC7BIT_t UC7BIT;
    // Character length. Selects 7-bit or 8-bit character length. 0 8-bit data 1 7-bit data
    IUSCI_SPI.UCMST_t UCMST;
    // Master mode select 0 Slave mode 1 Master mode
    IUSCI_SPI.UCMODE_SYNC_t UCMODE;
    // USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00 3-Pin SPI 01 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1 10 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0 11 I2C Mode
    IUSCI_SPI.UCSYNC_t UCSYNC;
    // Synchronous mode enable 0 Asynchronous mode 1 Synchronous Mode
};
struct IUSCI_SPI.UCxCTL1_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
metaonly struct UCxCTL1_t {
    IUSCI_SPI.UCSSEL_SPI_t UCSSEL;
    // USCI clock source select. These bits select the BRCLK source clock in master mode. UCxCLK is always used in slave mode. 00 NA 01 ACLK 10 SMCLK 11 SMCLK
    IUSCI_SPI.UCSWRST_t UCSWRST;
    // Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state
};
struct IUSCI_SPI.UCxSTAT_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
metaonly struct UCxSTAT_t {
    IUSCI_SPI.UCLISTEN_t UCLISTEN;
    // Listen enable. The UCLISTEN bit selects loopback mode. 0 Disabled 1 Enabled. UCAxTXD is internally fed back to the receiver
    IUSCI_SPI.UCFE_t UCFE;
    // Framing error flag. This bit indicates a bus conflict in 4-wire master mode. UCFE is not used in 3-wire master or any slave mode. 0 No error 1 Bus conflict occurred
    IUSCI_SPI.UCOE_t UCOE;
    // Overrun error flag. This bit is set when a character is transferred into UCAxRXBUF before the previous character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by software. Otherwise, it will not function correctly. 0 No error 1 Overrun error occurred
    IUSCI_SPI.UCBUSY_t UCBUSY;
    // USCI busy. This bit indicates if a transmit or receive operation is in progress. 0 USCI inactive 1 USCI transmitting or receiving
};
IUSCI_SPI.addPeripheralsMap()  // module-wide
index URL

Create a map of all peripherals available on a device

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
Void addPeripheralsMap(ICpuDataSheet.Instance cds);
ARGUMENTS
cds — an xdc.platform.ICpuDataSheet instance
DETAILS
The config parameter peripherals is by default undefined in an xdc.platform.ICpuDataSheet instance. This function gathers all instance configuration parameters that are of the type xdc.platform.IPeripheral into the map peripherals.
IUSCI_SPI.getAll()  // module-wide
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Find all peripherals of a certain type

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
IPeripheral.IPeripheralArray getAll();
DETAILS
The type of the peripherals returned is defined by the type of the caller.
RETURNS
Returns an array of IPeripheral instances
IUSCI_SPI.getRegisters()  // module-wide
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Find all registers defined by the peripheral

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
IPeripheral.StringArray getRegisters();
RETURNS
Returns an array of register names
config IUSCI_SPI.UCLKHz  // instance
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Stores the UCLK external clock frequency in float

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
config Float UCLKHz = 1000000;
config IUSCI_SPI.name  // instance
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Specific peripheral name given by the device

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
config String name;
DETAILS
Devices can have more than one peripheral of the same type. In such cases, device data sheets give different names to the instances of a same peripheral. For example, the name for a timer module could be TimerA3, and a device that has two such timers can name them TA0 and TA1.
config IUSCI_SPI.owner  // instance
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String specifying the entity that manages the peripheral

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
config String owner;
IUSCI_SPI.getUCRXIE()  // instance
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XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
Bool getUCRXIE();
IUSCI_SPI.getUCTXIE()  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
Bool getUCTXIE();
IUSCI_SPI.setUCRXIE()  // instance
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XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
Bool setUCRXIE(Bool set);
IUSCI_SPI.setUCTXIE()  // instance
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XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_SPI.xdc
Bool setUCTXIE(Bool set);
generated on Tue, 24 Aug 2010 15:40:43 GMT