enum IUSCI_I2C.UC7BIT_t |
|
Character length. Selects 7-bit or 8-bit character length
enum UC7BIT_t {
UC7BIT_OFF,
// 8-bit
UC7BIT
// 7-bit
};
enum IUSCI_I2C.UCA10_t |
|
Own addressing mode select
enum UCA10_t {
UCA10_OFF,
// Own address is a 7-bit address
UCA10
// Own address is a 10-bit address
};
enum IUSCI_I2C.UCADDR_t |
|
Address received in address-bit multiprocessor mode
enum UCADDR_t {
UCADDR_OFF,
// Received character is data
UCADDR
// Received character is an address
};
enum IUSCI_I2C.UCALIFG_t |
|
Arbitration lost interrupt flag
enum UCALIFG_t {
UCALIFG_OFF,
// No interrupt pending
UCALIFG
// Interrupt pending
};
enum IUSCI_I2C.UCBBUSY_t |
|
Bus busy
enum UCBBUSY_t {
UCBBUSY_OFF,
// Bus inactive
UCBBUSY
// Bus busy
};
enum IUSCI_I2C.UCBRKIE_t |
|
Receive break character interrupt-enable
enum UCBRKIE_t {
UCBRKIE_OFF,
// Received break characters do not set UCAxRXIFG
UCBRKIE
// Received break characters set UCAxRXIFG
};
enum IUSCI_I2C.UCBRK_t |
|
Break detect flag
enum UCBRK_t {
UCBRK_OFF,
// No break condition
UCBRK
// Break condition occurred
};
enum IUSCI_I2C.UCBUSY_t |
|
USCI busy. This bit indicates if a transmit or receive operation is in progress
enum UCBUSY_t {
UCBUSY_OFF,
// USCI inactive
UCBUSY
// USCI transmitting or receiving
};
enum IUSCI_I2C.UCDORM_t |
|
Dormant. Puts USCI into sleep mode
enum UCDORM_t {
UCDORM_OFF,
// Not dormant. All received characters will set UCAxRXIFG
UCDORM
// Dormant. Only characters that are preceded by an idle-line or with
address bit set will set UCAxRXIFG. In UART mode with automatic baud
rate detection only the combination of a break and synch field will set
UCAxRXIFG
};
enum IUSCI_I2C.UCFE_t |
|
Framing error flag
enum UCFE_t {
UCFE_OFF,
// 0 No error
UCFE
// Character received with low stop bit
};
enum IUSCI_I2C.UCGCEN_t |
|
General call response enable
enum UCGCEN_t {
UCGCEN_OFF,
// Do not respond to a general call
UCGCEN
// Respond to a general call
};
enum IUSCI_I2C.UCGC_t |
|
General call address received
enum UCGC_t {
UCGC_OFF,
// No general call address received
UCGC
// General call address received
};
enum IUSCI_I2C.UCIDLE_t |
|
Idle line detected in idle-line multiprocessor mode
enum UCIDLE_t {
UCIDLE_OFF,
// No idle line detected
UCIDLE
// Idle line detected
};
enum IUSCI_I2C.UCLISTEN_t |
|
Listen enable. The UCLISTEN bit selects loopback mode
enum UCLISTEN_t {
UCLISTEN_OFF,
// Disabled
UCLISTEN
// Enabled. UCAxTXD is internally fed back to the receiver
};
enum IUSCI_I2C.UCMM_t |
|
Multi-master environment select
enum UCMM_t {
UCMM_OFF,
// Single master environment. There is no other master in the system. The address compare unit is disabled
UCMM
// Multi master environment
};
enum IUSCI_I2C.UCMODE_SYNC_t |
|
USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1
enum UCMODE_SYNC_t {
UCMODE_0,
// 3-Pin SPI
UCMODE_1,
// 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
UCMODE_2,
// 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
UCMODE_3
// I2C Mode
};
enum IUSCI_I2C.UCMSB_t |
|
MSB first select. Controls the direction of the receive and transmit shift register
enum UCMSB_t {
UCMSB_OFF,
// LSB first
UCMSB
// MSB first
};
enum IUSCI_I2C.UCMST_t |
|
Master mode select
enum UCMST_t {
UCMST_OFF,
// Slave mode
UCMST
// Master mode
};
enum IUSCI_I2C.UCNACKIFG_t |
|
Not-acknowledge received interrupt flag
enum UCNACKIFG_t {
UCNACKIFG_OFF,
// No interrupt pending
UCNACKIFG
// Interrupt pending
};
enum IUSCI_I2C.UCOE_t |
|
Overrun error flag
enum UCOE_t {
UCOE_OFF,
// No error
UCOE
// Overrun error occurred
};
enum IUSCI_I2C.UCPE_t |
|
Parity error flag. When UCPEN = 0, UCPE is read as 0
enum UCPE_t {
UCPE_OFF,
// No error
UCPE
// Character received with parity error
};
enum IUSCI_I2C.UCRXEIE_t |
|
Receive erroneous-character interrupt-enable
enum UCRXEIE_t {
UCRXEIE_OFF,
// Erroneous characters rejected and UCAxRXIFG is not set
UCRXEIE
// Erroneous characters received will set UCAxRXIFG
};
enum IUSCI_I2C.UCRXERR_t |
|
Bit 2 Receive error flag. This bit indicates a character was received with error(s).
When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also
set. UCRXERR is cleared when UCAxRXBUF is read
enum UCRXERR_t {
UCRXERR_OFF,
// No receive errors detected
UCRXERR
// Receive error detected
};
enum IUSCI_I2C.UCSCLLOW_t |
|
SCL low
enum UCSCLLOW_t {
UCSCLLOW_OFF,
// SCL is not held low
UCSCLLOW
// SCL is held low
};
enum IUSCI_I2C.UCSLA10_t |
|
Slave addressing mode select
enum UCSLA10_t {
UCSLA10_OFF,
// Address slave with 7-bit address
UCSLA10
// Address slave with 10-bit address
};
enum IUSCI_I2C.UCSSEL_I2C_t |
|
USCI clock source select. These bits select the BRCLK source clock
enum UCSSEL_I2C_t {
UCSSEL_0,
// UCLK
UCSSEL_1,
// ACLK
UCSSEL_2
// SMCLK
};
enum IUSCI_I2C.UCSTPIFG_t |
|
Stop condition interrupt flag
enum UCSTPIFG_t {
UCSTPIFG_OFF,
// No interrupt pending
UCSTPIFG
// Interrupt pending
};
enum IUSCI_I2C.UCSTTIFG_t |
|
Start condition interrupt flag
enum UCSTTIFG_t {
UCSTTIFG_OFF,
// No interrupt pending
UCSTTIFG
// Interrupt pending
};
enum IUSCI_I2C.UCSWRST_t |
|
Software reset enable
enum UCSWRST_t {
UCSWRST_OFF,
// Disabled. USCI reset released for operation
UCSWRST
// Enabled. USCI logic held in reset state
};
enum IUSCI_I2C.UCSYNC_t |
|
Synchronous mode enable
enum UCSYNC_t {
UCSYNC_OFF,
// Asynchronous mode
UCSYNC
// Synchronous Mode
};
enum IUSCI_I2C.UCTR_t |
|
Transmitter/Receiver
enum UCTR_t {
UCTR_OFF,
// Receiver
UCTR
// Transmitter
};
enum IUSCI_I2C.UCTXADDR_t |
|
Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode
enum UCTXADDR_t {
UCTXADDR_OFF,
// Next frame transmitted is data
UCTXADDR
// Next frame transmitted is an address
};
enum IUSCI_I2C.UCTXBRK_t |
|
Transmit break. Transmits a break with the next write to the transmit buffer.
In UART mode with automatic baud rate detection 055h must be written
into UCAxTXBUF to generate the required break/synch fields. Otherwise
0h must be written into the transmit buffer
enum UCTXBRK_t {
UCTXBRK_OFF,
// Next frame transmitted is not a break
UCTXBRK
// Next frame transmitted is a break or a break/synch
};
enum IUSCI_I2C.UCTXNACK_t |
|
Transmit a NACK
enum UCTXNACK_t {
UCTXNACK_OFF,
// Acknowledge normally
UCTXNACK
// Generate NACK
};
enum IUSCI_I2C.UCTXSTP_t |
|
Transmit STOP condition in master mode
enum UCTXSTP_t {
UCTXSTP_OFF,
// No STOP generated
UCTXSTP
// Generate STOP
};
enum IUSCI_I2C.UCTXSTT_t |
|
Transmit START condition in master mode
enum UCTXSTT_t {
UCTXSTT_OFF,
// Do not generate START condition
UCTXSTT
// Generate START condition
};
typedef IUSCI_I2C.IPeripheralArray |
|
typedef IUSCI_I2C.StringArray |
|
typedef String StringArray[];
struct IUSCI_I2C.ForceSetDefaultRegister_t |
|
Force Set Default Register
metaonly struct ForceSetDefaultRegister_t {
String register;
Bool regForceSet;
};
DETAILS
Type to store if each register needs to be forced initialized
even if the register is in default state.
SEE
struct IUSCI_I2C.UCBxI2COA_t |
|
metaonly struct UCBxI2COA_t {
// General call response enable
0 Do not respond to a general call
1 Respond to a general call
UChar I2COA;
// I2C own address. The I2COAx bits contain the local address of the USCI_Bx
I2C controller. The address is right-justified. In 7-bit addressing mode Bit 6 is
the MSB, Bits 9-7 are ignored. In 10-bit addressing mode Bit 9 is the MSB
};
struct IUSCI_I2C.UCxCTL0_t |
|
metaonly struct UCxCTL0_t {
// Own addressing mode select
0 Own address is a 7-bit address
1 Own address is a 10-bit address
// Slave addressing mode select
0 Address slave with 7-bit address
1 Address slave with 10-bit address
// Multi-master environment select
0 Single master environment. There is no other master in the system.
The address compare unit is disabled.
1 Multi master environment
// Master mode select. When a master looses arbitration in a multi-master
environment (UCMM = 1) the UCMST bit is automatically cleared and the
module acts as slave.
0 Slave mode
1 Master mode
// USCI Mode. The UCMODEx bits select the synchronous mode when
UCSYNC = 1.
00 3-pin SPI
01 4-pin SPI (master/slave enabled if STE = 1)
10 4-pin SPI (master/slave enabled if STE = 0)
11 I2C mode
// Synchronous mode enable
0 Asynchronous mode
1 Synchronous mode
};
struct IUSCI_I2C.UCxCTL1_t |
|
metaonly struct UCxCTL1_t {
// USCI clock source select. These bits select the BRCLK source clock.
00 UCLKI
01 ACLK
10 SMCLK
11 SMCLK
// Transmitter/Receiver
0 Receiver
1 Transmitter
// Transmit a NACK. UCTXNACK is automatically cleared after a NACK is
transmitted.
0 Acknowledge normally
1 Generate NACK
// Transmit STOP condition in master mode. Ignored in slave mode. In
master receiver mode the STOP condition is preceded by a NACK.
UCTXSTP is automatically cleared after STOP is generated.
0 No STOP generated
1 Generate STOP
// Transmit START condition in master mode. Ignored in slave mode. In
master receiver mode a repeated START condition is preceded by a
NACK. UCTXSTT is automatically cleared after START condition and
address information is transmitted.
Ignored in slave mode.
0 Do not generate START condition
1 Generate START condition
// Software reset enable
0 Disabled. USCI reset released for operation.
1 Enabled. USCI logic held in reset state
};
struct IUSCI_I2C.UCxSTAT_t |
|
metaonly struct UCxSTAT_t {
// SCL low
0 SCL is not held low
1 SCL is held low
// General call address received. UCGC is automatically cleared when a
START condition is received.
0 No general call address received
1 General call address received
// Bus busy
0 Bus inactive
1 Bus busy
// Not-acknowledge received interrupt flag. UCNACKIFG is automatically
cleared when a START condition is received.
0 No interrupt pending
1 Interrupt pending
// Stop condition interrupt flag. UCSTPIFG is automatically cleared when a
START condition is received.
0 No interrupt pending
1 Interrupt pending
// Start condition interrupt flag. UCSTTIFG is automatically cleared if a STOP
condition is received.
0 No interrupt pending
1 Interrupt pending
// Arbitration lost interrupt flag
0 No interrupt pending
1 Interrupt pending
};
IUSCI_I2C.addPeripheralsMap() // module-wide |
|
Create a map of all peripherals available on a device
ARGUMENTS
DETAILS
The config parameter
peripherals is by default undefined in an
xdc.platform.ICpuDataSheet instance. This function gathers
all instance configuration parameters that are of the type
xdc.platform.IPeripheral into the map
peripherals.
IUSCI_I2C.getAll() // module-wide |
|
Find all peripherals of a certain type
DETAILS
The type of the peripherals returned is defined by the type of the
caller.
RETURNS
Returns an array of IPeripheral instances
IUSCI_I2C.getRegisters() // module-wide |
|
Find all registers defined by the peripheral
RETURNS
Returns an array of register names
config IUSCI_I2C.UCLKHz // instance |
|
Stores the UCLK external clock frequency in float
config Float UCLKHz = 1000000;
config IUSCI_I2C.name // instance |
|
Specific peripheral name given by the device
DETAILS
Devices can have more than one peripheral of the same type. In such
cases, device data sheets give different names to the instances of a
same peripheral. For example, the name for a timer module could be
TimerA3, and a device that has two such timers can name them TA0
and TA1.
config IUSCI_I2C.owner // instance |
|
String specifying the entity that manages the peripheral
IUSCI_I2C.getUCRXIE() // instance |
|
IUSCI_I2C.getUCTXIE() // instance |
|
IUSCI_I2C.setUCRXIE() // instance |
|
Bool setUCRXIE(Bool set);
IUSCI_I2C.setUCTXIE() // instance |
|
Bool setUCTXIE(Bool set);