enum IUSCI_B0_SPI.UC7BIT_t |
|
Character length. Selects 7-bit or 8-bit character length
enum UC7BIT_t {
UC7BIT_OFF,
// 8-bit
UC7BIT
// 7-bit
};
enum IUSCI_B0_SPI.UCADDR_t |
|
Address received in address-bit multiprocessor mode
enum UCADDR_t {
UCADDR_OFF,
// Received character is data
UCADDR
// Received character is an address
};
enum IUSCI_B0_SPI.UCBRKIE_t |
|
Receive break character interrupt-enable
enum UCBRKIE_t {
UCBRKIE_OFF,
// Received break characters do not set UCAxRXIFG
UCBRKIE
// Received break characters set UCAxRXIFG
};
enum IUSCI_B0_SPI.UCBRK_t |
|
Break detect flag
enum UCBRK_t {
UCBRK_OFF,
// No break condition
UCBRK
// Break condition occurred
};
enum IUSCI_B0_SPI.UCBUSY_t |
|
USCI busy. This bit indicates if a transmit or receive operation is in progress
enum UCBUSY_t {
UCBUSY_OFF,
// USCI inactive
UCBUSY
// USCI transmitting or receiving
};
enum IUSCI_B0_SPI.UCCKPH_t |
|
Clock phase select
enum UCCKPH_t {
UCCKPH_OFF,
// Data is changed on the first UCLK edge and captured on the following edge
UCCKPH
// Data is captured on the first UCLK edge and changed on the following edge
};
enum IUSCI_B0_SPI.UCCKPL_t |
|
Clock polarity select
enum UCCKPL_t {
UCCKPL_OFF,
// Inactive state is low
UCCKPL
// Inactive state is high
};
enum IUSCI_B0_SPI.UCDORM_t |
|
Dormant. Puts USCI into sleep mode
enum UCDORM_t {
UCDORM_OFF,
// Not dormant. All received characters will set UCAxRXIFG
UCDORM
// Dormant. Only characters that are preceded by an idle-line or with
address bit set will set UCAxRXIFG. In UART mode with automatic baud
rate detection only the combination of a break and synch field will set
UCAxRXIFG
};
enum IUSCI_B0_SPI.UCFE_t |
|
Framing error flag
enum UCFE_t {
UCFE_OFF,
// 0 No error
UCFE
// Character received with low stop bit
};
enum IUSCI_B0_SPI.UCIDLE_t |
|
Idle line detected in idle-line multiprocessor mode
enum UCIDLE_t {
UCIDLE_OFF,
// No idle line detected
UCIDLE
// Idle line detected
};
enum IUSCI_B0_SPI.UCLISTEN_t |
|
Listen enable. The UCLISTEN bit selects loopback mode
enum UCLISTEN_t {
UCLISTEN_OFF,
// Disabled
UCLISTEN
// Enabled. UCAxTXD is internally fed back to the receiver
};
enum IUSCI_B0_SPI.UCMODE_SYNC_t |
|
USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1
enum UCMODE_SYNC_t {
UCMODE_0,
// 3-Pin SPI
UCMODE_1,
// 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
UCMODE_2,
// 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
UCMODE_3
// I2C Mode
};
enum IUSCI_B0_SPI.UCMSB_t |
|
MSB first select. Controls the direction of the receive and transmit shift register
enum UCMSB_t {
UCMSB_OFF,
// LSB first
UCMSB
// MSB first
};
enum IUSCI_B0_SPI.UCMST_t |
|
Master mode select
enum UCMST_t {
UCMST_OFF,
// Slave mode
UCMST
// Master mode
};
enum IUSCI_B0_SPI.UCOE_t |
|
Overrun error flag
enum UCOE_t {
UCOE_OFF,
// No error
UCOE
// Overrun error occurred
};
enum IUSCI_B0_SPI.UCPE_t |
|
Parity error flag. When UCPEN = 0, UCPE is read as 0
enum UCPE_t {
UCPE_OFF,
// No error
UCPE
// Character received with parity error
};
enum IUSCI_B0_SPI.UCRXEIE_t |
|
Receive erroneous-character interrupt-enable
enum UCRXEIE_t {
UCRXEIE_OFF,
// Erroneous characters rejected and UCAxRXIFG is not set
UCRXEIE
// Erroneous characters received will set UCAxRXIFG
};
enum IUSCI_B0_SPI.UCRXERR_t |
|
Bit 2 Receive error flag. This bit indicates a character was received with error(s).
When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also
set. UCRXERR is cleared when UCAxRXBUF is read
enum UCRXERR_t {
UCRXERR_OFF,
// No receive errors detected
UCRXERR
// Receive error detected
};
enum IUSCI_B0_SPI.UCSSEL_SPI_t |
|
USCI clock source select. These bits select the BRCLK source clock
enum UCSSEL_SPI_t {
UCSSEL_0,
// NA
UCSSEL_1,
// ACLK
UCSSEL_2
// SMCLK
};
enum IUSCI_B0_SPI.UCSWRST_t |
|
Software reset enable
enum UCSWRST_t {
UCSWRST_OFF,
// Disabled. USCI reset released for operation
UCSWRST
// Enabled. USCI logic held in reset state
};
enum IUSCI_B0_SPI.UCSYNC_t |
|
Synchronous mode enable
enum UCSYNC_t {
UCSYNC_OFF,
// Asynchronous mode
UCSYNC
// Synchronous Mode
};
enum IUSCI_B0_SPI.UCTXADDR_t |
|
Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode
enum UCTXADDR_t {
UCTXADDR_OFF,
// Next frame transmitted is data
UCTXADDR
// Next frame transmitted is an address
};
enum IUSCI_B0_SPI.UCTXBRK_t |
|
Transmit break. Transmits a break with the next write to the transmit buffer.
In UART mode with automatic baud rate detection 055h must be written
into UCAxTXBUF to generate the required break/synch fields. Otherwise
0h must be written into the transmit buffer
enum UCTXBRK_t {
UCTXBRK_OFF,
// Next frame transmitted is not a break
UCTXBRK
// Next frame transmitted is a break or a break/synch
};
typedef IUSCI_B0_SPI.IPeripheralArray |
|
typedef IUSCI_B0_SPI.StringArray |
|
typedef String StringArray[];
struct IUSCI_B0_SPI.ForceSetDefaultRegister_t |
|
Force Set Default Register
metaonly struct ForceSetDefaultRegister_t {
String register;
Bool regForceSet;
};
DETAILS
Type to store if each register needs to be forced initialized
even if the register is in default state.
SEE
struct IUSCI_B0_SPI.UCxCTL0_t |
|
metaonly struct UCxCTL0_t {
// Clock phase select.
0 Data is changed on the first UCLK edge and captured on the
following edge.
1 Data is captured on the first UCLK edge and changed on the
following edge
// Clock polarity select
0 The inactive state is low
1 The inactive state is high
// MSB first select. Controls the direction of the receive and transmit shift
register.
0 LSB first
1 MSB first
// Character length. Selects 7-bit or 8-bit character length.
0 8-bit data
1 7-bit data
// Master mode select
0 Slave mode
1 Master mode
// USCI mode. The UCMODEx bits select the synchronous mode when
UCSYNC = 1.
00 3-Pin SPI
01 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
10 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
11 I2C Mode
// Synchronous mode enable
0 Asynchronous mode
1 Synchronous Mode
};
struct IUSCI_B0_SPI.UCxCTL1_t |
|
metaonly struct UCxCTL1_t {
// USCI clock source select. These bits select the BRCLK source clock in
master mode. UCxCLK is always used in slave mode.
00 NA
01 ACLK
10 SMCLK
11 SMCLK
// Software reset enable
0 Disabled. USCI reset released for operation.
1 Enabled. USCI logic held in reset state
};
struct IUSCI_B0_SPI.UCxSTAT_t |
|
metaonly struct UCxSTAT_t {
// Listen enable. The UCLISTEN bit selects loopback mode.
0 Disabled
1 Enabled. UCAxTXD is internally fed back to the receiver
// Framing error flag. This bit indicates a bus conflict in 4-wire master mode.
UCFE is not used in 3-wire master or any slave mode.
0 No error
1 Bus conflict occurred
// Overrun error flag. This bit is set when a character is transferred into
UCAxRXBUF before the previous character was read. UCOE is cleared
automatically when UCxRXBUF is read, and must not be cleared by
software. Otherwise, it will not function correctly.
0 No error
1 Overrun error occurred
// USCI busy. This bit indicates if a transmit or receive operation is in
progress.
0 USCI inactive
1 USCI transmitting or receiving
};
IUSCI_B0_SPI.addPeripheralsMap() // module-wide |
|
Create a map of all peripherals available on a device
ARGUMENTS
DETAILS
The config parameter
peripherals is by default undefined in an
xdc.platform.ICpuDataSheet instance. This function gathers
all instance configuration parameters that are of the type
xdc.platform.IPeripheral into the map
peripherals.
IUSCI_B0_SPI.getAll() // module-wide |
|
Find all peripherals of a certain type
DETAILS
The type of the peripherals returned is defined by the type of the
caller.
RETURNS
Returns an array of IPeripheral instances
IUSCI_B0_SPI.getRegisters() // module-wide |
|
Find all registers defined by the peripheral
RETURNS
Returns an array of register names
config IUSCI_B0_SPI.UCB0BR0 // instance |
|
Bit Rate Control Register 0
config UChar UCB0BR0 = 0;
config IUSCI_B0_SPI.UCB0BR1 // instance |
|
Bit Rate Control Register 1
config UChar UCB0BR1 = 0;
config IUSCI_B0_SPI.UCB0CTL0 // instance |
|
Control Register 0
config IUSCI_B0_SPI.UCB0CTL1 // instance |
|
Control Register 1
config IUSCI_B0_SPI.UCB0RXBUF // instance |
|
Receive Buffer Register
config UChar UCB0RXBUF = 0;
config IUSCI_B0_SPI.UCB0STAT // instance |
|
Status Register
config IUSCI_B0_SPI.UCB0TXBUF // instance |
|
Transmit Buffer Register
config UChar UCB0TXBUF = 0;
config IUSCI_B0_SPI.UCLKHz // instance |
|
Stores the UCLK external clock frequency in float
config Float UCLKHz = 1000000;
config IUSCI_B0_SPI.name // instance |
|
Specific peripheral name given by the device
DETAILS
Devices can have more than one peripheral of the same type. In such
cases, device data sheets give different names to the instances of a
same peripheral. For example, the name for a timer module could be
TimerA3, and a device that has two such timers can name them TA0
and TA1.
config IUSCI_B0_SPI.owner // instance |
|
String specifying the entity that manages the peripheral
IUSCI_B0_SPI.getUCRXIE() // instance |
|
IUSCI_B0_SPI.getUCTXIE() // instance |
|
IUSCI_B0_SPI.setUCRXIE() // instance |
|
Bool setUCRXIE(Bool set);
IUSCI_B0_SPI.setUCTXIE() // instance |
|
Bool setUCTXIE(Bool set);