1 /*!
2 * Universal Serial Communication Interface
3 */
4 metaonly interface IUSCI_I2C inherits IUSCI {
5
6
7
8
9
10 /*! Own addressing mode select */
11 enum UCA10_t {
12 UCA10_OFF = 0x00, /*! Own address is a 7-bit address */
13 UCA10 = 0x80 /*! Own address is a 10-bit address */
14 };
15
16 /*! Slave addressing mode select */
17 enum UCSLA10_t {
18 UCSLA10_OFF = 0x00, /*! Address slave with 7-bit address */
19 UCSLA10 = 0x40 /*! Address slave with 10-bit address */
20 };
21
22 /*! Multi-master environment select */
23 enum UCMM_t {
24 UCMM_OFF = 0x00, /*! Single master environment. There is no other master in the system. The address compare unit is disabled. */
25 UCMM = 0x20 /*! Multi master environment */
26 };
27
28 /*! Master mode select */
29 enum UCMST_t {
30 UCMST_OFF = 0x00, /*! Slave mode */
31 UCMST = 0x40 /*! Master mode */
32 };
33
34 /*! USCI clock source select. These bits select the BRCLK source clock. */
35 enum UCSSEL_I2C_t {
36 UCSSEL_0 = 0x00, /*! UCLK */
37 UCSSEL_1 = 0x01, /*! ACLK */
38 UCSSEL_2 = 0x02 /*! SMCLK */
39
40 };
41
42 /*! Transmitter/Receiver */
43 enum UCTR_t {
44 UCTR_OFF = 0x00, /*! Receiver */
45 UCTR = 0x10 /*! Transmitter */
46 };
47
48 /*! Transmit a NACK */
49 enum UCTXNACK_t {
50 UCTXNACK_OFF = 0x00, /*! Acknowledge normally */
51 UCTXNACK = 0x08 /*! Generate NACK */
52 };
53
54 /*! Transmit STOP condition in master mode */
55 enum UCTXSTP_t {
56 UCTXSTP_OFF = 0x00, /*! No STOP generated */
57 UCTXSTP = 0x10 /*! Generate STOP */
58 };
59
60 /*! Transmit START condition in master mode */
61 enum UCTXSTT_t {
62 UCTXSTT_OFF = 0x00, /*! Do not generate START condition */
63 UCTXSTT = 0x10 /*! Generate START condition */
64 };
65
66 /*! SCL low */
67 enum UCSCLLOW_t {
68 UCSCLLOW_OFF = 0x00, /*! SCL is not held low */
69 UCSCLLOW = 0x10 /*! SCL is held low */
70 };
71
72 /*! General call address received */
73 enum UCGC_t {
74 UCGC_OFF = 0x00, /*! No general call address received */
75 UCGC = 0x10 /*! General call address received */
76 };
77
78 /*! Bus busy */
79 enum UCBBUSY_t {
80 UCBBUSY_OFF = 0x00, /*! Bus inactive */
81 UCBBUSY = 0x10 /*! Bus busy */
82 };
83
84 /*! Not-acknowledge received interrupt flag */
85 enum UCNACKIFG_t {
86 UCNACKIFG_OFF = 0x00, /*! No interrupt pending */
87 UCNACKIFG = 0x10 /*! Interrupt pending */
88 };
89
90 /*! Stop condition interrupt flag */
91 enum UCSTPIFG_t {
92 UCSTPIFG_OFF = 0x00, /*! No interrupt pending */
93 UCSTPIFG = 0x10 /*! Interrupt pending */
94 };
95
96 /*! Start condition interrupt flag */
97 enum UCSTTIFG_t {
98 UCSTTIFG_OFF = 0x00, /*! No interrupt pending */
99 UCSTTIFG = 0x10 /*! Interrupt pending */
100 };
101
102 /*! Arbitration lost interrupt flag */
103 enum UCALIFG_t {
104 UCALIFG_OFF = 0x00, /*! No interrupt pending */
105 UCALIFG = 0x10 /*! Interrupt pending */
106 };
107
108 /*! General call response enable */
109 enum UCGCEN_t {
110 UCGCEN_OFF = 0x00, /*! Do not respond to a general call */
111 UCGCEN = 0x80 /*! Respond to a general call */
112 };
113
114 struct UCxCTL0_t {
115 UCA10_t UCA10; /*! Own addressing mode select
116 * 0 Own address is a 7-bit address
117 * 1 Own address is a 10-bit address */
118 UCSLA10_t UCSLA10; /*! Slave addressing mode select
119 * 0 Address slave with 7-bit address
120 * 1 Address slave with 10-bit address */
121 UCMM_t UCMM; /*! Multi-master environment select
122 * 0 Single master environment. There is no other master in the system.
123 * The address compare unit is disabled.
124 * 1 Multi master environment */
125 UCMST_t UCMST; /*! Master mode select. When a master looses arbitration in a multi-master
126 *environment (UCMM = 1) the UCMST bit is automatically cleared and the
127 *module acts as slave.
128 * 0 Slave mode
129 * 1 Master mode */
130 UCMODE_SYNC_t UCMODE; /*! USCI Mode. The UCMODEx bits select the synchronous mode when
131 *UCSYNC = 1.
132 * 00 3-pin SPI
133 * 01 4-pin SPI (master/slave enabled if STE = 1)
134 * 10 4-pin SPI (master/slave enabled if STE = 0)
135 * 11 I2C mode */
136 UCSYNC_t UCSYNC; /*! Synchronous mode enable
137 * 0 Asynchronous mode
138 * 1 Synchronous mode */
139 }
140
141 struct UCxCTL1_t {
142 UCSSEL_I2C_t UCSSEL; /*! USCI clock source select. These bits select the BRCLK source clock.
143 * 00 UCLKI
144 * 01 ACLK
145 * 10 SMCLK
146 * 11 SMCLK */
147 UCTR_t UCTR; /*! Transmitter/Receiver
148 * 0 Receiver
149 * 1 Transmitter */
150 UCTXNACK_t UCTXNACK; /*! Transmit a NACK. UCTXNACK is automatically cleared after a NACK is
151 *transmitted.
152 * 0 Acknowledge normally
153 * 1 Generate NACK */
154 UCTXSTP_t UCTXSTP; /*! Transmit STOP condition in master mode. Ignored in slave mode. In
155 *master receiver mode the STOP condition is preceded by a NACK.
156 *UCTXSTP is automatically cleared after STOP is generated.
157 * 0 No STOP generated
158 * 1 Generate STOP */
159 UCTXSTT_t UCTXSTT; /*! Transmit START condition in master mode. Ignored in slave mode. In
160 *master receiver mode a repeated START condition is preceded by a
161 *NACK. UCTXSTT is automatically cleared after START condition and
162 *address information is transmitted.
163 *Ignored in slave mode.
164 * 0 Do not generate START condition
165 * 1 Generate START condition */
166 UCSWRST_t UCSWRST; /*! Software reset enable
167 * 0 Disabled. USCI reset released for operation.
168 * 1 Enabled. USCI logic held in reset state. */
169 }
170
171 struct UCxSTAT_t {
172 UCSCLLOW_t UCSCLLOW; /*! SCL low
173 * 0 SCL is not held low
174 * 1 SCL is held low */
175 UCGC_t UCGC; /*! General call address received. UCGC is automatically cleared when a
176 *START condition is received.
177 * 0 No general call address received
178 * 1 General call address received */
179 UCBBUSY_t UCBBUSY; /*! Bus busy
180 * 0 Bus inactive
181 * 1 Bus busy */
182 UCNACKIFG_t UCNACKIFG; /*! Not-acknowledge received interrupt flag. UCNACKIFG is automatically
183 *cleared when a START condition is received.
184 * 0 No interrupt pending
185 * 1 Interrupt pending */
186 UCSTPIFG_t UCSTPIFG; /*! Stop condition interrupt flag. UCSTPIFG is automatically cleared when a
187 *START condition is received.
188 * 0 No interrupt pending
189 * 1 Interrupt pending */
190 UCSTTIFG_t UCSTTIFG; /*! Start condition interrupt flag. UCSTTIFG is automatically cleared if a STOP
191 *condition is received.
192 * 0 No interrupt pending
193 * 1 Interrupt pending */
194 UCALIFG_t UCALIFG; /*! Arbitration lost interrupt flag
195 * 0 No interrupt pending
196 * 1 Interrupt pending */
197 }
198
199 struct UCBxI2COA_t {
200 UCGCEN_t UCGCEN; /*! General call response enable
201 * 0 Do not respond to a general call
202 * 1 Respond to a general call */
203 UChar I2COA; /*! I2C own address. The I2COAx bits contain the local address of the USCI_Bx
204 *I2C controller. The address is right-justified. In 7-bit addressing mode Bit 6 is
205 *the MSB, Bits 9-7 are ignored. In 10-bit addressing mode Bit 9 is the MSB. */
206 }
207 }