module ti.catalog.msp430.peripherals.communication.USCI_A0_UART

metaonly module ti.catalog.msp430.peripherals.communication.USCI_A0_UART_2xx

index URL

Universal Serial Communication Interface A0 UART 2xx

XDCscript usage
Individual elements

XDCscript usage meta-domain sourced in ti/catalog/msp430/peripherals/communication/USCI_A0_UART_2xx.xdc

var USCI_A0_UART_2xx = xdc.useModule('ti.catalog.msp430.peripherals.communication.USCI_A0_UART_2xx');

module-wide constants & types

values of type USCI_A0_UART_2xx.UC7BIT_t// Character length. Selects 7-bit or 8-bit character length

const USCI_A0_UART_2xx.UC7BIT_OFF// 8-bit;

const USCI_A0_UART_2xx.UC7BIT// 7-bit;

values of type USCI_A0_UART_2xx.UCABDEN_t// Automatic baud rate detect enable

const USCI_A0_UART_2xx.UCABDEN_OFF// Baud rate detection disabled. Length of break and synch field is not measured;

const USCI_A0_UART_2xx.UCABDEN// Baud rate detection enabled. Length of break and synch field is measured and baud rate settings are changed accordingly;

values of type USCI_A0_UART_2xx.UCADDR_t// Address received in address-bit multiprocessor mode

const USCI_A0_UART_2xx.UCADDR_OFF// Received character is data;

const USCI_A0_UART_2xx.UCADDR// Received character is an address;

values of type USCI_A0_UART_2xx.UCBRF_t// First modulation stage select

const USCI_A0_UART_2xx.UCBRF_0// First stage 0;

const USCI_A0_UART_2xx.UCBRF_1// First stage 1;

const USCI_A0_UART_2xx.UCBRF_2// First stage 2;

const USCI_A0_UART_2xx.UCBRF_3// First stage 3;

const USCI_A0_UART_2xx.UCBRF_4// First stage 4;

const USCI_A0_UART_2xx.UCBRF_5// First stage 5;

const USCI_A0_UART_2xx.UCBRF_6// First stage 6;

const USCI_A0_UART_2xx.UCBRF_7// First stage 7;

const USCI_A0_UART_2xx.UCBRF_8// First stage 8;

const USCI_A0_UART_2xx.UCBRF_9// First stage 9;

const USCI_A0_UART_2xx.UCBRF_10// First stage 10;

const USCI_A0_UART_2xx.UCBRF_11// First stage 11;

const USCI_A0_UART_2xx.UCBRF_12// First stage 12;

const USCI_A0_UART_2xx.UCBRF_13// First stage 13;

const USCI_A0_UART_2xx.UCBRF_14// First stage 14;

const USCI_A0_UART_2xx.UCBRF_15// First stage 15;

values of type USCI_A0_UART_2xx.UCBRKIE_t// Receive break character interrupt-enable

const USCI_A0_UART_2xx.UCBRKIE_OFF// Received break characters do not set UCAxRXIFG;

const USCI_A0_UART_2xx.UCBRKIE// Received break characters set UCAxRXIFG;

values of type USCI_A0_UART_2xx.UCBRK_t// Break detect flag

const USCI_A0_UART_2xx.UCBRK_OFF// No break condition;

const USCI_A0_UART_2xx.UCBRK// Break condition occurred;

values of type USCI_A0_UART_2xx.UCBRS_t// Second modulation stage select

const USCI_A0_UART_2xx.UCBRS_0// Second stage 0;

const USCI_A0_UART_2xx.UCBRS_1// Second stage 1;

const USCI_A0_UART_2xx.UCBRS_2// Second stage 2;

const USCI_A0_UART_2xx.UCBRS_3// Second stage 3;

const USCI_A0_UART_2xx.UCBRS_4// Second stage 4;

const USCI_A0_UART_2xx.UCBRS_5// Second stage 5;

const USCI_A0_UART_2xx.UCBRS_6// Second stage 6;

const USCI_A0_UART_2xx.UCBRS_7// Second stage 7;

values of type USCI_A0_UART_2xx.UCBTOE_t// Break time out error

const USCI_A0_UART_2xx.UCBTOE_OFF// No error;

const USCI_A0_UART_2xx.UCBTOE// Length of break field exceeded 22 bit times;

values of type USCI_A0_UART_2xx.UCBUSY_t// USCI busy. This bit indicates if a transmit or receive operation is in progress

const USCI_A0_UART_2xx.UCBUSY_OFF// USCI inactive;

const USCI_A0_UART_2xx.UCBUSY// USCI transmitting or receiving;

values of type USCI_A0_UART_2xx.UCDELIM0_t// Break/synch delimiter length bit 0

const USCI_A0_UART_2xx.UCDELIM0_OFF// Break Sync Delimiter bit 0 Off;

const USCI_A0_UART_2xx.UCDELIM0// Break Sync Delimiter bit 0 On;

values of type USCI_A0_UART_2xx.UCDELIM1_t// Break/synch delimiter length bit 1

const USCI_A0_UART_2xx.UCDELIM1_OFF// Break Sync Delimiter bit 1 Off;

const USCI_A0_UART_2xx.UCDELIM1// Break Sync Delimiter bit 1 On;

values of type USCI_A0_UART_2xx.UCDORM_t// Dormant. Puts USCI into sleep mode

const USCI_A0_UART_2xx.UCDORM_OFF// Not dormant. All received characters will set UCAxRXIFG;

const USCI_A0_UART_2xx.UCDORM// Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG;

values of type USCI_A0_UART_2xx.UCFE_t// Framing error flag

const USCI_A0_UART_2xx.UCFE_OFF// 0 No error;

const USCI_A0_UART_2xx.UCFE// Character received with low stop bit;

values of type USCI_A0_UART_2xx.UCIDLE_t// Idle line detected in idle-line multiprocessor mode

const USCI_A0_UART_2xx.UCIDLE_OFF// No idle line detected;

const USCI_A0_UART_2xx.UCIDLE// Idle line detected;

values of type USCI_A0_UART_2xx.UCIREN_t// IrDA encoder/decoder enable

const USCI_A0_UART_2xx.UCIREN_OFF// IrDA encoder/decoder disabled;

const USCI_A0_UART_2xx.UCIREN// IrDA encoder/decoder enabled;

values of type USCI_A0_UART_2xx.UCIRRXFE_t// IrDA receive filter enabled

const USCI_A0_UART_2xx.UCIRRXFE_OFF// Receive filter disabled;

const USCI_A0_UART_2xx.UCIRRXFE// Receive filter enabled;

values of type USCI_A0_UART_2xx.UCIRRXFL0_t// IRDA Receive Filter Length Bit 0

const USCI_A0_UART_2xx.UCIRRXFL0_OFF// Bit 0 OFF;

const USCI_A0_UART_2xx.UCIRRXFL0// Bit 0 ON;

values of type USCI_A0_UART_2xx.UCIRRXFL1_t// IRDA Receive Filter Length Bit 1

const USCI_A0_UART_2xx.UCIRRXFL1_OFF// Bit 1 OFF;

const USCI_A0_UART_2xx.UCIRRXFL1// Bit 1 ON;

values of type USCI_A0_UART_2xx.UCIRRXFL2_t// IRDA Receive Filter Length Bit 2

const USCI_A0_UART_2xx.UCIRRXFL2_OFF// Bit 2 OFF;

const USCI_A0_UART_2xx.UCIRRXFL2// Bit 2 ON;

values of type USCI_A0_UART_2xx.UCIRRXFL3_t// IRDA Receive Filter Length Bit 3

const USCI_A0_UART_2xx.UCIRRXFL3_OFF// Bit 3 OFF;

const USCI_A0_UART_2xx.UCIRRXFL3// Bit 3 ON;

values of type USCI_A0_UART_2xx.UCIRRXFL4_t// IRDA Receive Filter Length Bit 4

const USCI_A0_UART_2xx.UCIRRXFL4_OFF// Bit 4 OFF;

const USCI_A0_UART_2xx.UCIRRXFL4// Bit 4 ON;

values of type USCI_A0_UART_2xx.UCIRRXFL5_t// IRDA Receive Filter Length Bit 5

const USCI_A0_UART_2xx.UCIRRXFL5_OFF// Bit 5 OFF;

const USCI_A0_UART_2xx.UCIRRXFL5// Bit 5 ON;

values of type USCI_A0_UART_2xx.UCIRRXPL_t// IrDA receive input UCAxRXD polarity

const USCI_A0_UART_2xx.UCIRRXPL_OFF// IrDA transceiver delivers a high pulse when a light pulse is seen;

const USCI_A0_UART_2xx.UCIRRXPL// IrDA transceiver delivers a low pulse when a light pulse is seen;

values of type USCI_A0_UART_2xx.UCIRTXCLK_t// IrDA transmit pulse clock select

const USCI_A0_UART_2xx.UCIRTXCLK_OFF// BRCLK;

const USCI_A0_UART_2xx.UCIRTXCLK// BITCLK16 when UCOS16 = 1. Otherwise, BRCLK;

values of type USCI_A0_UART_2xx.UCIRTXPL0_t// IRDA Transmit Pulse Length Bit 0

const USCI_A0_UART_2xx.UCIRTXPL0_OFF// Bit 0 OFF;

const USCI_A0_UART_2xx.UCIRTXPL0// Bit 0 ON;

values of type USCI_A0_UART_2xx.UCIRTXPL1_t// IRDA Transmit Pulse Length Bit 1

const USCI_A0_UART_2xx.UCIRTXPL1_OFF// Bit 1 OFF;

const USCI_A0_UART_2xx.UCIRTXPL1// Bit 1 ON;

values of type USCI_A0_UART_2xx.UCIRTXPL2_t// IRDA Transmit Pulse Length Bit 2

const USCI_A0_UART_2xx.UCIRTXPL2_OFF// Bit 2 OFF;

const USCI_A0_UART_2xx.UCIRTXPL2// Bit 2 ON;

values of type USCI_A0_UART_2xx.UCIRTXPL3_t// IRDA Transmit Pulse Length Bit 3

const USCI_A0_UART_2xx.UCIRTXPL3_OFF// Bit 3 OFF;

const USCI_A0_UART_2xx.UCIRTXPL3// Bit 3 ON;

values of type USCI_A0_UART_2xx.UCIRTXPL4_t// IRDA Transmit Pulse Length Bit 4

const USCI_A0_UART_2xx.UCIRTXPL4_OFF// Bit 4 OFF;

const USCI_A0_UART_2xx.UCIRTXPL4// Bit 4 ON;

values of type USCI_A0_UART_2xx.UCIRTXPL5_t// IRDA Transmit Pulse Length Bit 5

const USCI_A0_UART_2xx.UCIRTXPL5_OFF// Bit 5 OFF;

const USCI_A0_UART_2xx.UCIRTXPL5// Bit 5 ON;

values of type USCI_A0_UART_2xx.UCLISTEN_t// Listen enable. The UCLISTEN bit selects loopback mode

const USCI_A0_UART_2xx.UCLISTEN_OFF// Disabled;

const USCI_A0_UART_2xx.UCLISTEN// Enabled. UCAxTXD is internally fed back to the receiver;

values of type USCI_A0_UART_2xx.UCMODE_ASYNC_t// USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0

const USCI_A0_UART_2xx.UCMODE_0// UART Mode;

const USCI_A0_UART_2xx.UCMODE_1// Idle-Line Multiprocessor Mode;

const USCI_A0_UART_2xx.UCMODE_2// Address-Bit Multiprocessor Mode;

const USCI_A0_UART_2xx.UCMODE_3// UART Mode with automatic baud rate detection;

values of type USCI_A0_UART_2xx.UCMODE_SYNC_t// USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1

const USCI_A0_UART_2xx.UCMODE_0// 3-Pin SPI;

const USCI_A0_UART_2xx.UCMODE_1// 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1;

const USCI_A0_UART_2xx.UCMODE_2// 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0;

const USCI_A0_UART_2xx.UCMODE_3// I2C Mode;

values of type USCI_A0_UART_2xx.UCMSB_t// MSB first select. Controls the direction of the receive and transmit shift register

const USCI_A0_UART_2xx.UCMSB_OFF// LSB first;

const USCI_A0_UART_2xx.UCMSB// MSB first;

values of type USCI_A0_UART_2xx.UCOE_t// Overrun error flag

const USCI_A0_UART_2xx.UCOE_OFF// No error;

const USCI_A0_UART_2xx.UCOE// Overrun error occurred;

values of type USCI_A0_UART_2xx.UCOS16_t// Oversampling mode enabled

const USCI_A0_UART_2xx.UCOS16_OFF// Disabled;

const USCI_A0_UART_2xx.UCOS16// Enabled;

values of type USCI_A0_UART_2xx.UCPAR_t// Parity select. UCPAR is not used when parity is disabled

const USCI_A0_UART_2xx.UCPAR_OFF// Odd parity;

const USCI_A0_UART_2xx.UCPAR// Even parity;

values of type USCI_A0_UART_2xx.UCPEN_t// Parity enable

const USCI_A0_UART_2xx.UCPEN_OFF// Parity Disabled;

const USCI_A0_UART_2xx.UCPEN// Parity Enabled;

values of type USCI_A0_UART_2xx.UCPE_t// Parity error flag. When UCPEN = 0, UCPE is read as 0

const USCI_A0_UART_2xx.UCPE_OFF// No error;

const USCI_A0_UART_2xx.UCPE// Character received with parity error;

values of type USCI_A0_UART_2xx.UCRXEIE_t// Receive erroneous-character interrupt-enable

const USCI_A0_UART_2xx.UCRXEIE_OFF// Erroneous characters rejected and UCAxRXIFG is not set;

const USCI_A0_UART_2xx.UCRXEIE// Erroneous characters received will set UCAxRXIFG;

values of type USCI_A0_UART_2xx.UCRXERR_t// Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read

const USCI_A0_UART_2xx.UCRXERR_OFF// No receive errors detected;

const USCI_A0_UART_2xx.UCRXERR// Receive error detected;

values of type USCI_A0_UART_2xx.UCSPB_t// Stop bit select. Number of stop bits

const USCI_A0_UART_2xx.UCSPB_OFF// One stop bit;

const USCI_A0_UART_2xx.UCSPB// Two stop bits;

values of type USCI_A0_UART_2xx.UCSSEL_UART_t// USCI clock source select. These bits select the BRCLK source clock

const USCI_A0_UART_2xx.UCSSEL_0// UCLK;

const USCI_A0_UART_2xx.UCSSEL_1// ACLK;

const USCI_A0_UART_2xx.UCSSEL_2// SMCLK;

values of type USCI_A0_UART_2xx.UCSTOE_t// Synch field time out error

const USCI_A0_UART_2xx.UCSTOE_OFF// No error;

const USCI_A0_UART_2xx.UCSTOE// Length of synch field exceeded measurable time;

values of type USCI_A0_UART_2xx.UCSWRST_t// Software reset enable

const USCI_A0_UART_2xx.UCSWRST_OFF// Disabled. USCI reset released for operation;

const USCI_A0_UART_2xx.UCSWRST// Enabled. USCI logic held in reset state;

values of type USCI_A0_UART_2xx.UCSYNC_t// Synchronous mode enable

const USCI_A0_UART_2xx.UCSYNC_OFF// Asynchronous mode;

const USCI_A0_UART_2xx.UCSYNC// Synchronous Mode;

values of type USCI_A0_UART_2xx.UCTXADDR_t// Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode

const USCI_A0_UART_2xx.UCTXADDR_OFF// Next frame transmitted is data;

const USCI_A0_UART_2xx.UCTXADDR// Next frame transmitted is an address;

values of type USCI_A0_UART_2xx.UCTXBRK_t// Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer

const USCI_A0_UART_2xx.UCTXBRK_OFF// Next frame transmitted is not a break;

const USCI_A0_UART_2xx.UCTXBRK// Next frame transmitted is a break or a break/synch;

var obj = new USCI_A0_UART_2xx.ForceSetDefaultRegister_t// Force Set Default Register;

obj.register = String ...

obj.regForceSet = Bool ...

var obj = new USCI_A0_UART_2xx.UCxABCTL_t// ;

obj.UCDELIM1// Break/synch delimiter length 00 1 bit time 01 2 bit times 10 3 bit times 11 4 bit times = IUSCI_UART.UCDELIM1_t ...

obj.UCDELIM0// Break/synch delimiter length 00 1 bit time 01 2 bit times 10 3 bit times 11 4 bit times = IUSCI_UART.UCDELIM0_t ...

obj.UCSTOE// Synch field time out error 0 No error 1 Length of synch field exceeded measurable time = IUSCI_UART.UCSTOE_t ...

obj.UCBTOE// Break time out error 0 No error 1 Length of break field exceeded 22 bit times = IUSCI_UART.UCBTOE_t ...

obj.UCABDEN// Automatic baud rate detect enable 0 Baud rate detection disabled. Length of break and synch field is not measured. 1 Baud rate detection enabled. Length of break and synch field is measured and baud rate settings are changed accordingly = IUSCI_UART.UCABDEN_t ...

var obj = new USCI_A0_UART_2xx.UCxCTL0_t// ;

obj.UCPEN// Parity enable 0 Parity disabled. 1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation = IUSCI_UART.UCPEN_t ...

obj.UCPAR// Parity select. UCPAR is not used when parity is disabled. 0 Odd parity 1 Even parity = IUSCI_UART.UCPAR_t ...

obj.UCMSB// MSB first select. Controls the direction of the receive and transmit shift register. 0 LSB first 1 MSB first = IUSCI_UART.UCMSB_t ...

obj.UC7BIT// Character length. Selects 7-bit or 8-bit character length. 0 8-bit data 1 7-bit data = IUSCI_UART.UC7BIT_t ...

obj.UCSPB// Stop bit select. Number of stop bits. 0 One stop bit 1 Two stop bits = IUSCI_UART.UCSPB_t ...

obj.UCMODE// USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0. 00 UART Mode. 01 Idle-Line Multiprocessor Mode. 10 Address-Bit Multiprocessor Mode. 11 UART Mode with automatic baud rate detection = IUSCI_UART.UCMODE_ASYNC_t ...

obj.UCSYNC// Synchronous mode enable 0 Asynchronous mode 1 Synchronous Mode = IUSCI_UART.UCSYNC_t ...

var obj = new USCI_A0_UART_2xx.UCxCTL1_t// ;

obj.UCSSEL// USCI clock source select. These bits select the BRCLK source clock. 00 UCLK 01 ACLK 10 SMCLK 11 SMCLK = IUSCI_UART.UCSSEL_UART_t ...

obj.UCRXEIE// Receive erroneous-character interrupt-enable 0 Erroneous characters rejected and UCAxRXIFG is not set 1 Erroneous characters received will set UCAxRXIFG = IUSCI_UART.UCRXEIE_t ...

obj.UCBRKIE// Receive break character interrupt-enable 0 Received break characters do not set UCAxRXIFG. 1 Received break characters set UCAxRXIFG = IUSCI_UART.UCBRKIE_t ...

obj.UCDORM// Dormant. Puts USCI into sleep mode. 0 Not dormant. All received characters will set UCAxRXIFG. 1 Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG = IUSCI_UART.UCDORM_t ...

obj.UCTXADDR// Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode. 0 Next frame transmitted is data 1 Next frame transmitted is an address = IUSCI_UART.UCTXADDR_t ...

obj.UCTXBRK// Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer. 0 Next frame transmitted is not a break 1 Next frame transmitted is a break or a break/synch = IUSCI_UART.UCTXBRK_t ...

obj.UCSWRST// Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state = IUSCI_UART.UCSWRST_t ...

var obj = new USCI_A0_UART_2xx.UCxIRRCTL_t// ;

obj.UCIRRXFL5// IRDA Receive Filter Length Bit 5 = IUSCI_UART.UCIRRXFL5_t ...

obj.UCIRRXFL4// IRDA Receive Filter Length Bit 4 = IUSCI_UART.UCIRRXFL4_t ...

obj.UCIRRXFL3// IRDA Receive Filter Length Bit 3 = IUSCI_UART.UCIRRXFL3_t ...

obj.UCIRRXFL2// IRDA Receive Filter Length Bit 2 = IUSCI_UART.UCIRRXFL2_t ...

obj.UCIRRXFL1// IRDA Receive Filter Length Bit 1 = IUSCI_UART.UCIRRXFL1_t ...

obj.UCIRRXFL0// IRDA Receive Filter Length Bit 0 = IUSCI_UART.UCIRRXFL0_t ...

obj.UCIRRXPL// IrDA receive input UCAxRXD polarity 0 IrDA transceiver delivers a high pulse when a light pulse is seen 1 IrDA transceiver delivers a low pulse when a light pulse is seen = IUSCI_UART.UCIRRXPL_t ...

obj.UCIRRXFE// IrDA receive filter enabled 0 Receive filter disabled 1 Receive filter enabled = IUSCI_UART.UCIRRXFE_t ...

var obj = new USCI_A0_UART_2xx.UCxIRTCTL_t// ;

obj.UCIRTXPL5// IRDA Transmit Pulse Length Bit 5 = IUSCI_UART.UCIRTXPL5_t ...

obj.UCIRTXPL4// IRDA Transmit Pulse Length Bit 4 = IUSCI_UART.UCIRTXPL4_t ...

obj.UCIRTXPL3// IRDA Transmit Pulse Length Bit 3 = IUSCI_UART.UCIRTXPL3_t ...

obj.UCIRTXPL2// IRDA Transmit Pulse Length Bit 2 = IUSCI_UART.UCIRTXPL2_t ...

obj.UCIRTXPL1// IRDA Transmit Pulse Length Bit 1 = IUSCI_UART.UCIRTXPL1_t ...

obj.UCIRTXPL0// IRDA Transmit Pulse Length Bit 0 = IUSCI_UART.UCIRTXPL0_t ...

obj.UCIRTXCLK// IrDA transmit pulse clock select 0 BRCLK 1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK = IUSCI_UART.UCIRTXCLK_t ...

obj.UCIREN// IrDA encoder/decoder enable. 0 IrDA encoder/decoder disabled 1 IrDA encoder/decoder enabled = IUSCI_UART.UCIREN_t ...

var obj = new USCI_A0_UART_2xx.UCxMCTL_t// ;

obj.UCBRF// First modulation stage select. These bits determine the modulation pattern for BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0 = IUSCI_UART.UCBRF_t ...

obj.UCBRS// Second modulation stage select. These bits determine the modulation pattern for BITCLK = IUSCI_UART.UCBRS_t ...

obj.UCOS16// Oversampling mode enabled 0 Disabled 1 Enabled = IUSCI_UART.UCOS16_t ...

var obj = new USCI_A0_UART_2xx.UCxSTAT_t// ;

obj.UCLISTEN// Listen enable. The UCLISTEN bit selects loopback mode. 0 Disabled 1 Enabled. UCAxTXD is internally fed back to the receiver = IUSCI_UART.UCLISTEN_t ...

obj.UCFE// Framing error flag 0 No error 1 Character received with low stop bit = IUSCI_UART.UCFE_t ...

obj.UCOE// Overrun error flag. This bit is set when a character is transferred into UCAxRXBUF before the previous character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by software. Otherwise, it will not function correctly. 0 No error 1 Overrun error occurred = IUSCI_UART.UCOE_t ...

obj.UCPE// Parity error flag. When UCPEN = 0, UCPE is read as 0. 0 No error 1 Character received with parity error = IUSCI_UART.UCPE_t ...

obj.UCBRK// Break detect flag 0 No break condition 1 Break condition occurred = IUSCI_UART.UCBRK_t ...

obj.UCRXERR// Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read. 0 No receive errors detected 1 Receive error detected = IUSCI_UART.UCRXERR_t ...

obj.UCADDR// Address received in address-bit multiprocessor mode. 0 Received character is data 1 Received character is an address = IUSCI_UART.UCADDR_t ...

obj.UCIDLE// Idle line detected in idle-line multiprocessor mode. 0 No idle line detected 1 Idle line detected = IUSCI_UART.UCIDLE_t ...

obj.UCBUSY// USCI busy. This bit indicates if a transmit or receive operation is in progress. 0 USCI inactive 1 USCI transmitting or receiving = IUSCI_UART.UCBUSY_t ...

module-wide functions

USCI_A0_UART_2xx.addPeripheralsMap// Create a map of all peripherals available on a device(ICpuDataSheet.Instance cds) returns Void

USCI_A0_UART_2xx.getAll// Find all peripherals of a certain type() returns IPeripheral.Instance[]

USCI_A0_UART_2xx.getRegisters// Find all registers defined by the peripheral() returns String[]

per-instance config parameters

var params = new USCI_A0_UART_2xx.Params// Instance config-params object;

params.UCA0ABCTL// Auto Baud Rate Control Register = IUSCI_A0_UART.UCxABCTL_t {

UCDELIM1: IUSCI_UART.UCDELIM1_OFF,

UCDELIM0: IUSCI_UART.UCDELIM0_OFF,

UCSTOE: IUSCI_UART.UCSTOE_OFF,

UCBTOE: IUSCI_UART.UCBTOE_OFF,

UCABDEN: IUSCI_UART.UCABDEN_OFF

};

params.UCA0BR0// Baud rate control register 0 = UChar 0;

params.UCA0BR1// Baud rate control register 1 = UChar 0;

params.UCA0CTL0// Control Register 0 = IUSCI_A0_UART.UCxCTL0_t {

UCPEN: IUSCI_UART.UCPEN_OFF,

UCPAR: IUSCI_UART.UCPAR_OFF,

UCMSB: IUSCI.UCMSB_OFF,

UC7BIT: IUSCI.UC7BIT_OFF,

UCSPB: IUSCI_UART.UCSPB_OFF,

UCMODE: IUSCI_UART.UCMODE_0,

UCSYNC: IUSCI.UCSYNC_OFF

};

params.UCA0CTL1// Control Register 1 = IUSCI_A0_UART.UCxCTL1_t {

UCSSEL: IUSCI_UART.UCSSEL_0,

UCRXEIE: IUSCI.UCRXEIE_OFF,

UCBRKIE: IUSCI.UCBRKIE_OFF,

UCDORM: IUSCI.UCDORM_OFF,

UCTXADDR: IUSCI.UCTXADDR_OFF,

UCTXBRK: IUSCI.UCTXBRK_OFF,

UCSWRST: IUSCI.UCSWRST

};

params.UCA0IRRCTL// IrDA Receive Control Register = IUSCI_A0_UART.UCxIRRCTL_t {

UCIRRXFL5: IUSCI_UART.UCIRRXFL5_OFF,

UCIRRXFL4: IUSCI_UART.UCIRRXFL4_OFF,

UCIRRXFL3: IUSCI_UART.UCIRRXFL3_OFF,

UCIRRXFL2: IUSCI_UART.UCIRRXFL2_OFF,

UCIRRXFL1: IUSCI_UART.UCIRRXFL1_OFF,

UCIRRXFL0: IUSCI_UART.UCIRRXFL0_OFF,

UCIRRXPL: IUSCI_UART.UCIRRXPL_OFF,

UCIRRXFE: IUSCI_UART.UCIRRXFE_OFF

};

params.UCA0IRTCTL// IrDA Transmit Control Register = IUSCI_A0_UART.UCxIRTCTL_t {

UCIRTXPL5: IUSCI_UART.UCIRTXPL5_OFF,

UCIRTXPL4: IUSCI_UART.UCIRTXPL4_OFF,

UCIRTXPL3: IUSCI_UART.UCIRTXPL3_OFF,

UCIRTXPL2: IUSCI_UART.UCIRTXPL2_OFF,

UCIRTXPL1: IUSCI_UART.UCIRTXPL1_OFF,

UCIRTXPL0: IUSCI_UART.UCIRTXPL0_OFF,

UCIRTXCLK: IUSCI_UART.UCIRTXCLK_OFF,

UCIREN: IUSCI_UART.UCIREN_OFF

};

params.UCA0MCTL// Modulation Control Register = IUSCI_A0_UART.UCxMCTL_t {

UCBRF: IUSCI_UART.UCBRF_0,

UCBRS: IUSCI_UART.UCBRS_0,

UCOS16: IUSCI_UART.UCOS16_OFF

};

params.UCA0RXBUF// Receive Buffer Register = UChar 0;

params.UCA0STAT// Status Register = IUSCI_A0_UART.UCxSTAT_t {

UCLISTEN: IUSCI.UCLISTEN_OFF,

UCFE: IUSCI.UCFE_OFF,

UCOE: IUSCI.UCOE_OFF,

UCPE: IUSCI.UCPE_OFF,

UCBRK: IUSCI.UCBRK_OFF,

UCRXERR: IUSCI.UCRXERR_OFF,

UCADDR: IUSCI.UCADDR_OFF,

UCIDLE: IUSCI.UCIDLE_OFF,

UCBUSY: IUSCI.UCBUSY

};

params.UCA0TXBUF// Transmit Buffer Register = UChar 0;

params.UCLKHz// Stores the UCLK external clock frequency in float = Float 1000000;

params.forceSetDefaultRegister// Determine if each Register needs to be forced set or not = USCI_A0_UART_2xx.ForceSetDefaultRegister_t[] [

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

params.name// Specific peripheral name given by the device = String undefined;

params.owner// String specifying the entity that manages the peripheral = String undefined;

per-instance creation

var inst = USCI_A0_UART_2xx.create// Create an instance-object(IClock.Instance clock, IE2.Instance interruptEnableRegister2, params);

per-instance functions

inst.getUCRXIE// () returns Bool

inst.getUCTXIE// () returns Bool

inst.setUCRXIE// (Bool set) returns Bool

inst.setUCTXIE// (Bool set) returns Bool

enum USCI_A0_UART_2xx.UC7BIT_t

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Character length. Selects 7-bit or 8-bit character length

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UC7BIT_t

const USCI_A0_UART_2xx.UC7BIT_OFF;

// 8-bit

const USCI_A0_UART_2xx.UC7BIT;

// 7-bit

enum USCI_A0_UART_2xx.UCABDEN_t

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Automatic baud rate detect enable

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCABDEN_t

const USCI_A0_UART_2xx.UCABDEN_OFF;

// Baud rate detection disabled. Length of break and synch field is not measured

const USCI_A0_UART_2xx.UCABDEN;

// Baud rate detection enabled. Length of break and synch field is measured and baud rate settings are changed accordingly

enum USCI_A0_UART_2xx.UCADDR_t

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Address received in address-bit multiprocessor mode

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCADDR_t

const USCI_A0_UART_2xx.UCADDR_OFF;

// Received character is data

const USCI_A0_UART_2xx.UCADDR;

// Received character is an address

enum USCI_A0_UART_2xx.UCBRF_t

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First modulation stage select

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCBRF_t

const USCI_A0_UART_2xx.UCBRF_0;

// First stage 0

const USCI_A0_UART_2xx.UCBRF_1;

// First stage 1

const USCI_A0_UART_2xx.UCBRF_2;

// First stage 2

const USCI_A0_UART_2xx.UCBRF_3;

// First stage 3

const USCI_A0_UART_2xx.UCBRF_4;

// First stage 4

const USCI_A0_UART_2xx.UCBRF_5;

// First stage 5

const USCI_A0_UART_2xx.UCBRF_6;

// First stage 6

const USCI_A0_UART_2xx.UCBRF_7;

// First stage 7

const USCI_A0_UART_2xx.UCBRF_8;

// First stage 8

const USCI_A0_UART_2xx.UCBRF_9;

// First stage 9

const USCI_A0_UART_2xx.UCBRF_10;

// First stage 10

const USCI_A0_UART_2xx.UCBRF_11;

// First stage 11

const USCI_A0_UART_2xx.UCBRF_12;

// First stage 12

const USCI_A0_UART_2xx.UCBRF_13;

// First stage 13

const USCI_A0_UART_2xx.UCBRF_14;

// First stage 14

const USCI_A0_UART_2xx.UCBRF_15;

// First stage 15

enum USCI_A0_UART_2xx.UCBRKIE_t

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Receive break character interrupt-enable

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCBRKIE_t

const USCI_A0_UART_2xx.UCBRKIE_OFF;

// Received break characters do not set UCAxRXIFG

const USCI_A0_UART_2xx.UCBRKIE;

// Received break characters set UCAxRXIFG

enum USCI_A0_UART_2xx.UCBRK_t

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Break detect flag

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCBRK_t

const USCI_A0_UART_2xx.UCBRK_OFF;

// No break condition

const USCI_A0_UART_2xx.UCBRK;

// Break condition occurred

enum USCI_A0_UART_2xx.UCBRS_t

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Second modulation stage select

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCBRS_t

const USCI_A0_UART_2xx.UCBRS_0;

// Second stage 0

const USCI_A0_UART_2xx.UCBRS_1;

// Second stage 1

const USCI_A0_UART_2xx.UCBRS_2;

// Second stage 2

const USCI_A0_UART_2xx.UCBRS_3;

// Second stage 3

const USCI_A0_UART_2xx.UCBRS_4;

// Second stage 4

const USCI_A0_UART_2xx.UCBRS_5;

// Second stage 5

const USCI_A0_UART_2xx.UCBRS_6;

// Second stage 6

const USCI_A0_UART_2xx.UCBRS_7;

// Second stage 7

enum USCI_A0_UART_2xx.UCBTOE_t

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Break time out error

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCBTOE_t

const USCI_A0_UART_2xx.UCBTOE_OFF;

// No error

const USCI_A0_UART_2xx.UCBTOE;

// Length of break field exceeded 22 bit times

enum USCI_A0_UART_2xx.UCBUSY_t

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USCI busy. This bit indicates if a transmit or receive operation is in progress

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCBUSY_t

const USCI_A0_UART_2xx.UCBUSY_OFF;

// USCI inactive

const USCI_A0_UART_2xx.UCBUSY;

// USCI transmitting or receiving

enum USCI_A0_UART_2xx.UCDELIM0_t

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Break/synch delimiter length bit 0

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCDELIM0_t

const USCI_A0_UART_2xx.UCDELIM0_OFF;

// Break Sync Delimiter bit 0 Off

const USCI_A0_UART_2xx.UCDELIM0;

// Break Sync Delimiter bit 0 On

enum USCI_A0_UART_2xx.UCDELIM1_t

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Break/synch delimiter length bit 1

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCDELIM1_t

const USCI_A0_UART_2xx.UCDELIM1_OFF;

// Break Sync Delimiter bit 1 Off

const USCI_A0_UART_2xx.UCDELIM1;

// Break Sync Delimiter bit 1 On

enum USCI_A0_UART_2xx.UCDORM_t

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Dormant. Puts USCI into sleep mode

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCDORM_t

const USCI_A0_UART_2xx.UCDORM_OFF;

// Not dormant. All received characters will set UCAxRXIFG

const USCI_A0_UART_2xx.UCDORM;

// Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG

enum USCI_A0_UART_2xx.UCFE_t

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Framing error flag

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCFE_t

const USCI_A0_UART_2xx.UCFE_OFF;

// 0 No error

const USCI_A0_UART_2xx.UCFE;

// Character received with low stop bit

enum USCI_A0_UART_2xx.UCIDLE_t

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Idle line detected in idle-line multiprocessor mode

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIDLE_t

const USCI_A0_UART_2xx.UCIDLE_OFF;

// No idle line detected

const USCI_A0_UART_2xx.UCIDLE;

// Idle line detected

enum USCI_A0_UART_2xx.UCIREN_t

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IrDA encoder/decoder enable

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIREN_t

const USCI_A0_UART_2xx.UCIREN_OFF;

// IrDA encoder/decoder disabled

const USCI_A0_UART_2xx.UCIREN;

// IrDA encoder/decoder enabled

enum USCI_A0_UART_2xx.UCIRRXFE_t

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IrDA receive filter enabled

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRRXFE_t

const USCI_A0_UART_2xx.UCIRRXFE_OFF;

// Receive filter disabled

const USCI_A0_UART_2xx.UCIRRXFE;

// Receive filter enabled

enum USCI_A0_UART_2xx.UCIRRXFL0_t

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IRDA Receive Filter Length Bit 0

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRRXFL0_t

const USCI_A0_UART_2xx.UCIRRXFL0_OFF;

// Bit 0 OFF

const USCI_A0_UART_2xx.UCIRRXFL0;

// Bit 0 ON

enum USCI_A0_UART_2xx.UCIRRXFL1_t

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IRDA Receive Filter Length Bit 1

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRRXFL1_t

const USCI_A0_UART_2xx.UCIRRXFL1_OFF;

// Bit 1 OFF

const USCI_A0_UART_2xx.UCIRRXFL1;

// Bit 1 ON

enum USCI_A0_UART_2xx.UCIRRXFL2_t

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IRDA Receive Filter Length Bit 2

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRRXFL2_t

const USCI_A0_UART_2xx.UCIRRXFL2_OFF;

// Bit 2 OFF

const USCI_A0_UART_2xx.UCIRRXFL2;

// Bit 2 ON

enum USCI_A0_UART_2xx.UCIRRXFL3_t

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IRDA Receive Filter Length Bit 3

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRRXFL3_t

const USCI_A0_UART_2xx.UCIRRXFL3_OFF;

// Bit 3 OFF

const USCI_A0_UART_2xx.UCIRRXFL3;

// Bit 3 ON

enum USCI_A0_UART_2xx.UCIRRXFL4_t

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IRDA Receive Filter Length Bit 4

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRRXFL4_t

const USCI_A0_UART_2xx.UCIRRXFL4_OFF;

// Bit 4 OFF

const USCI_A0_UART_2xx.UCIRRXFL4;

// Bit 4 ON

enum USCI_A0_UART_2xx.UCIRRXFL5_t

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IRDA Receive Filter Length Bit 5

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRRXFL5_t

const USCI_A0_UART_2xx.UCIRRXFL5_OFF;

// Bit 5 OFF

const USCI_A0_UART_2xx.UCIRRXFL5;

// Bit 5 ON

enum USCI_A0_UART_2xx.UCIRRXPL_t

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IrDA receive input UCAxRXD polarity

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRRXPL_t

const USCI_A0_UART_2xx.UCIRRXPL_OFF;

// IrDA transceiver delivers a high pulse when a light pulse is seen

const USCI_A0_UART_2xx.UCIRRXPL;

// IrDA transceiver delivers a low pulse when a light pulse is seen

enum USCI_A0_UART_2xx.UCIRTXCLK_t

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IrDA transmit pulse clock select

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRTXCLK_t

const USCI_A0_UART_2xx.UCIRTXCLK_OFF;

// BRCLK

const USCI_A0_UART_2xx.UCIRTXCLK;

// BITCLK16 when UCOS16 = 1. Otherwise, BRCLK

enum USCI_A0_UART_2xx.UCIRTXPL0_t

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IRDA Transmit Pulse Length Bit 0

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRTXPL0_t

const USCI_A0_UART_2xx.UCIRTXPL0_OFF;

// Bit 0 OFF

const USCI_A0_UART_2xx.UCIRTXPL0;

// Bit 0 ON

enum USCI_A0_UART_2xx.UCIRTXPL1_t

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IRDA Transmit Pulse Length Bit 1

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRTXPL1_t

const USCI_A0_UART_2xx.UCIRTXPL1_OFF;

// Bit 1 OFF

const USCI_A0_UART_2xx.UCIRTXPL1;

// Bit 1 ON

enum USCI_A0_UART_2xx.UCIRTXPL2_t

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IRDA Transmit Pulse Length Bit 2

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRTXPL2_t

const USCI_A0_UART_2xx.UCIRTXPL2_OFF;

// Bit 2 OFF

const USCI_A0_UART_2xx.UCIRTXPL2;

// Bit 2 ON

enum USCI_A0_UART_2xx.UCIRTXPL3_t

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IRDA Transmit Pulse Length Bit 3

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRTXPL3_t

const USCI_A0_UART_2xx.UCIRTXPL3_OFF;

// Bit 3 OFF

const USCI_A0_UART_2xx.UCIRTXPL3;

// Bit 3 ON

enum USCI_A0_UART_2xx.UCIRTXPL4_t

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IRDA Transmit Pulse Length Bit 4

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRTXPL4_t

const USCI_A0_UART_2xx.UCIRTXPL4_OFF;

// Bit 4 OFF

const USCI_A0_UART_2xx.UCIRTXPL4;

// Bit 4 ON

enum USCI_A0_UART_2xx.UCIRTXPL5_t

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IRDA Transmit Pulse Length Bit 5

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCIRTXPL5_t

const USCI_A0_UART_2xx.UCIRTXPL5_OFF;

// Bit 5 OFF

const USCI_A0_UART_2xx.UCIRTXPL5;

// Bit 5 ON

enum USCI_A0_UART_2xx.UCLISTEN_t

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Listen enable. The UCLISTEN bit selects loopback mode

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCLISTEN_t

const USCI_A0_UART_2xx.UCLISTEN_OFF;

// Disabled

const USCI_A0_UART_2xx.UCLISTEN;

// Enabled. UCAxTXD is internally fed back to the receiver

enum USCI_A0_UART_2xx.UCMODE_ASYNC_t

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USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCMODE_ASYNC_t

const USCI_A0_UART_2xx.UCMODE_0;

// UART Mode

const USCI_A0_UART_2xx.UCMODE_1;

// Idle-Line Multiprocessor Mode

const USCI_A0_UART_2xx.UCMODE_2;

// Address-Bit Multiprocessor Mode

const USCI_A0_UART_2xx.UCMODE_3;

// UART Mode with automatic baud rate detection

enum USCI_A0_UART_2xx.UCMODE_SYNC_t

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USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCMODE_SYNC_t

const USCI_A0_UART_2xx.UCMODE_0;

// 3-Pin SPI

const USCI_A0_UART_2xx.UCMODE_1;

// 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1

const USCI_A0_UART_2xx.UCMODE_2;

// 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0

const USCI_A0_UART_2xx.UCMODE_3;

// I2C Mode

enum USCI_A0_UART_2xx.UCMSB_t

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MSB first select. Controls the direction of the receive and transmit shift register

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCMSB_t

const USCI_A0_UART_2xx.UCMSB_OFF;

// LSB first

const USCI_A0_UART_2xx.UCMSB;

// MSB first

enum USCI_A0_UART_2xx.UCOE_t

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Overrun error flag

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCOE_t

const USCI_A0_UART_2xx.UCOE_OFF;

// No error

const USCI_A0_UART_2xx.UCOE;

// Overrun error occurred

enum USCI_A0_UART_2xx.UCOS16_t

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Oversampling mode enabled

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCOS16_t

const USCI_A0_UART_2xx.UCOS16_OFF;

// Disabled

const USCI_A0_UART_2xx.UCOS16;

// Enabled

enum USCI_A0_UART_2xx.UCPAR_t

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Parity select. UCPAR is not used when parity is disabled

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCPAR_t

const USCI_A0_UART_2xx.UCPAR_OFF;

// Odd parity

const USCI_A0_UART_2xx.UCPAR;

// Even parity

enum USCI_A0_UART_2xx.UCPEN_t

index URL

Parity enable

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCPEN_t

const USCI_A0_UART_2xx.UCPEN_OFF;

// Parity Disabled

const USCI_A0_UART_2xx.UCPEN;

// Parity Enabled

enum USCI_A0_UART_2xx.UCPE_t

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Parity error flag. When UCPEN = 0, UCPE is read as 0

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCPE_t

const USCI_A0_UART_2xx.UCPE_OFF;

// No error

const USCI_A0_UART_2xx.UCPE;

// Character received with parity error

enum USCI_A0_UART_2xx.UCRXEIE_t

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Receive erroneous-character interrupt-enable

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCRXEIE_t

const USCI_A0_UART_2xx.UCRXEIE_OFF;

// Erroneous characters rejected and UCAxRXIFG is not set

const USCI_A0_UART_2xx.UCRXEIE;

// Erroneous characters received will set UCAxRXIFG

enum USCI_A0_UART_2xx.UCRXERR_t

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Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCRXERR_t

const USCI_A0_UART_2xx.UCRXERR_OFF;

// No receive errors detected

const USCI_A0_UART_2xx.UCRXERR;

// Receive error detected

enum USCI_A0_UART_2xx.UCSPB_t

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Stop bit select. Number of stop bits

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCSPB_t

const USCI_A0_UART_2xx.UCSPB_OFF;

// One stop bit

const USCI_A0_UART_2xx.UCSPB;

// Two stop bits

enum USCI_A0_UART_2xx.UCSSEL_UART_t

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USCI clock source select. These bits select the BRCLK source clock

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCSSEL_UART_t

const USCI_A0_UART_2xx.UCSSEL_0;

// UCLK

const USCI_A0_UART_2xx.UCSSEL_1;

// ACLK

const USCI_A0_UART_2xx.UCSSEL_2;

// SMCLK

enum USCI_A0_UART_2xx.UCSTOE_t

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Synch field time out error

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCSTOE_t

const USCI_A0_UART_2xx.UCSTOE_OFF;

// No error

const USCI_A0_UART_2xx.UCSTOE;

// Length of synch field exceeded measurable time

enum USCI_A0_UART_2xx.UCSWRST_t

index URL

Software reset enable

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCSWRST_t

const USCI_A0_UART_2xx.UCSWRST_OFF;

// Disabled. USCI reset released for operation

const USCI_A0_UART_2xx.UCSWRST;

// Enabled. USCI logic held in reset state

enum USCI_A0_UART_2xx.UCSYNC_t

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Synchronous mode enable

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCSYNC_t

const USCI_A0_UART_2xx.UCSYNC_OFF;

// Asynchronous mode

const USCI_A0_UART_2xx.UCSYNC;

// Synchronous Mode

enum USCI_A0_UART_2xx.UCTXADDR_t

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Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCTXADDR_t

const USCI_A0_UART_2xx.UCTXADDR_OFF;

// Next frame transmitted is data

const USCI_A0_UART_2xx.UCTXADDR;

// Next frame transmitted is an address

enum USCI_A0_UART_2xx.UCTXBRK_t

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Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer

XDCscript usage meta-domain

values of type USCI_A0_UART_2xx.UCTXBRK_t

const USCI_A0_UART_2xx.UCTXBRK_OFF;

// Next frame transmitted is not a break

const USCI_A0_UART_2xx.UCTXBRK;

// Next frame transmitted is a break or a break/synch

struct USCI_A0_UART_2xx.ForceSetDefaultRegister_t

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Force Set Default Register

XDCscript usage meta-domain

var obj = new USCI_A0_UART_2xx.ForceSetDefaultRegister_t;

obj.register = String ...

obj.regForceSet = Bool ...

DETAILS

Type to store if each register needs to be forced initialized even if the register is in default state.

SEE

ForceSetDefaultRegister_t

struct USCI_A0_UART_2xx.UCxABCTL_t

index URL

XDCscript usage meta-domain

var obj = new USCI_A0_UART_2xx.UCxABCTL_t;

obj.UCDELIM1 = IUSCI_UART.UCDELIM1_t ...

// Break/synch delimiter length 00 1 bit time 01 2 bit times 10 3 bit times 11 4 bit times

obj.UCDELIM0 = IUSCI_UART.UCDELIM0_t ...

// Break/synch delimiter length 00 1 bit time 01 2 bit times 10 3 bit times 11 4 bit times

obj.UCSTOE = IUSCI_UART.UCSTOE_t ...

// Synch field time out error 0 No error 1 Length of synch field exceeded measurable time

obj.UCBTOE = IUSCI_UART.UCBTOE_t ...

// Break time out error 0 No error 1 Length of break field exceeded 22 bit times

obj.UCABDEN = IUSCI_UART.UCABDEN_t ...

// Automatic baud rate detect enable 0 Baud rate detection disabled. Length of break and synch field is not measured. 1 Baud rate detection enabled. Length of break and synch field is measured and baud rate settings are changed accordingly

struct USCI_A0_UART_2xx.UCxCTL0_t

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XDCscript usage meta-domain

var obj = new USCI_A0_UART_2xx.UCxCTL0_t;

obj.UCPEN = IUSCI_UART.UCPEN_t ...

// Parity enable 0 Parity disabled. 1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation

obj.UCPAR = IUSCI_UART.UCPAR_t ...

// Parity select. UCPAR is not used when parity is disabled. 0 Odd parity 1 Even parity

obj.UCMSB = IUSCI_UART.UCMSB_t ...

// MSB first select. Controls the direction of the receive and transmit shift register. 0 LSB first 1 MSB first

obj.UC7BIT = IUSCI_UART.UC7BIT_t ...

// Character length. Selects 7-bit or 8-bit character length. 0 8-bit data 1 7-bit data

obj.UCSPB = IUSCI_UART.UCSPB_t ...

// Stop bit select. Number of stop bits. 0 One stop bit 1 Two stop bits

obj.UCMODE = IUSCI_UART.UCMODE_ASYNC_t ...

// USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0. 00 UART Mode. 01 Idle-Line Multiprocessor Mode. 10 Address-Bit Multiprocessor Mode. 11 UART Mode with automatic baud rate detection

obj.UCSYNC = IUSCI_UART.UCSYNC_t ...

// Synchronous mode enable 0 Asynchronous mode 1 Synchronous Mode

struct USCI_A0_UART_2xx.UCxCTL1_t

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XDCscript usage meta-domain

var obj = new USCI_A0_UART_2xx.UCxCTL1_t;

obj.UCSSEL = IUSCI_UART.UCSSEL_UART_t ...

// USCI clock source select. These bits select the BRCLK source clock. 00 UCLK 01 ACLK 10 SMCLK 11 SMCLK

obj.UCRXEIE = IUSCI_UART.UCRXEIE_t ...

// Receive erroneous-character interrupt-enable 0 Erroneous characters rejected and UCAxRXIFG is not set 1 Erroneous characters received will set UCAxRXIFG

obj.UCBRKIE = IUSCI_UART.UCBRKIE_t ...

// Receive break character interrupt-enable 0 Received break characters do not set UCAxRXIFG. 1 Received break characters set UCAxRXIFG

obj.UCDORM = IUSCI_UART.UCDORM_t ...

// Dormant. Puts USCI into sleep mode. 0 Not dormant. All received characters will set UCAxRXIFG. 1 Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG

obj.UCTXADDR = IUSCI_UART.UCTXADDR_t ...

// Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode. 0 Next frame transmitted is data 1 Next frame transmitted is an address

obj.UCTXBRK = IUSCI_UART.UCTXBRK_t ...

// Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer. 0 Next frame transmitted is not a break 1 Next frame transmitted is a break or a break/synch

obj.UCSWRST = IUSCI_UART.UCSWRST_t ...

// Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state

struct USCI_A0_UART_2xx.UCxIRRCTL_t

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XDCscript usage meta-domain

var obj = new USCI_A0_UART_2xx.UCxIRRCTL_t;

obj.UCIRRXFL5 = IUSCI_UART.UCIRRXFL5_t ...

// IRDA Receive Filter Length Bit 5

obj.UCIRRXFL4 = IUSCI_UART.UCIRRXFL4_t ...

// IRDA Receive Filter Length Bit 4

obj.UCIRRXFL3 = IUSCI_UART.UCIRRXFL3_t ...

// IRDA Receive Filter Length Bit 3

obj.UCIRRXFL2 = IUSCI_UART.UCIRRXFL2_t ...

// IRDA Receive Filter Length Bit 2

obj.UCIRRXFL1 = IUSCI_UART.UCIRRXFL1_t ...

// IRDA Receive Filter Length Bit 1

obj.UCIRRXFL0 = IUSCI_UART.UCIRRXFL0_t ...

// IRDA Receive Filter Length Bit 0

obj.UCIRRXPL = IUSCI_UART.UCIRRXPL_t ...

// IrDA receive input UCAxRXD polarity 0 IrDA transceiver delivers a high pulse when a light pulse is seen 1 IrDA transceiver delivers a low pulse when a light pulse is seen

obj.UCIRRXFE = IUSCI_UART.UCIRRXFE_t ...

// IrDA receive filter enabled 0 Receive filter disabled 1 Receive filter enabled

struct USCI_A0_UART_2xx.UCxIRTCTL_t

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XDCscript usage meta-domain

var obj = new USCI_A0_UART_2xx.UCxIRTCTL_t;

obj.UCIRTXPL5 = IUSCI_UART.UCIRTXPL5_t ...

// IRDA Transmit Pulse Length Bit 5

obj.UCIRTXPL4 = IUSCI_UART.UCIRTXPL4_t ...

// IRDA Transmit Pulse Length Bit 4

obj.UCIRTXPL3 = IUSCI_UART.UCIRTXPL3_t ...

// IRDA Transmit Pulse Length Bit 3

obj.UCIRTXPL2 = IUSCI_UART.UCIRTXPL2_t ...

// IRDA Transmit Pulse Length Bit 2

obj.UCIRTXPL1 = IUSCI_UART.UCIRTXPL1_t ...

// IRDA Transmit Pulse Length Bit 1

obj.UCIRTXPL0 = IUSCI_UART.UCIRTXPL0_t ...

// IRDA Transmit Pulse Length Bit 0

obj.UCIRTXCLK = IUSCI_UART.UCIRTXCLK_t ...

// IrDA transmit pulse clock select 0 BRCLK 1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK

obj.UCIREN = IUSCI_UART.UCIREN_t ...

// IrDA encoder/decoder enable. 0 IrDA encoder/decoder disabled 1 IrDA encoder/decoder enabled

struct USCI_A0_UART_2xx.UCxMCTL_t

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XDCscript usage meta-domain

var obj = new USCI_A0_UART_2xx.UCxMCTL_t;

obj.UCBRF = IUSCI_UART.UCBRF_t ...

// First modulation stage select. These bits determine the modulation pattern for BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0

obj.UCBRS = IUSCI_UART.UCBRS_t ...

// Second modulation stage select. These bits determine the modulation pattern for BITCLK

obj.UCOS16 = IUSCI_UART.UCOS16_t ...

// Oversampling mode enabled 0 Disabled 1 Enabled

struct USCI_A0_UART_2xx.UCxSTAT_t

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XDCscript usage meta-domain

var obj = new USCI_A0_UART_2xx.UCxSTAT_t;

obj.UCLISTEN = IUSCI_UART.UCLISTEN_t ...

// Listen enable. The UCLISTEN bit selects loopback mode. 0 Disabled 1 Enabled. UCAxTXD is internally fed back to the receiver

obj.UCFE = IUSCI_UART.UCFE_t ...

// Framing error flag 0 No error 1 Character received with low stop bit

obj.UCOE = IUSCI_UART.UCOE_t ...

// Overrun error flag. This bit is set when a character is transferred into UCAxRXBUF before the previous character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by software. Otherwise, it will not function correctly. 0 No error 1 Overrun error occurred

obj.UCPE = IUSCI_UART.UCPE_t ...

// Parity error flag. When UCPEN = 0, UCPE is read as 0. 0 No error 1 Character received with parity error

obj.UCBRK = IUSCI_UART.UCBRK_t ...

// Break detect flag 0 No break condition 1 Break condition occurred

obj.UCRXERR = IUSCI_UART.UCRXERR_t ...

// Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read. 0 No receive errors detected 1 Receive error detected

obj.UCADDR = IUSCI_UART.UCADDR_t ...

// Address received in address-bit multiprocessor mode. 0 Received character is data 1 Received character is an address

obj.UCIDLE = IUSCI_UART.UCIDLE_t ...

// Idle line detected in idle-line multiprocessor mode. 0 No idle line detected 1 Idle line detected

obj.UCBUSY = IUSCI_UART.UCBUSY_t ...

// USCI busy. This bit indicates if a transmit or receive operation is in progress. 0 USCI inactive 1 USCI transmitting or receiving

USCI_A0_UART_2xx.addPeripheralsMap() // module-wide

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Create a map of all peripherals available on a device

XDCscript usage meta-domain

USCI_A0_UART_2xx.addPeripheralsMap(ICpuDataSheet.Instance cds) returns Void

ARGUMENTS

cds — an xdc.platform.ICpuDataSheet instance

DETAILS

The config parameter peripherals is by default undefined in an xdc.platform.ICpuDataSheet instance. This function gathers all instance configuration parameters that are of the type xdc.platform.IPeripheral into the map peripherals.

USCI_A0_UART_2xx.getAll() // module-wide

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Find all peripherals of a certain type

XDCscript usage meta-domain

USCI_A0_UART_2xx.getAll() returns IPeripheral.Instance[]

DETAILS

The type of the peripherals returned is defined by the type of the caller.

RETURNS

Returns an array of IPeripheral instances

USCI_A0_UART_2xx.getRegisters() // module-wide

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Find all registers defined by the peripheral

XDCscript usage meta-domain

USCI_A0_UART_2xx.getRegisters() returns String[]

RETURNS

Returns an array of register names

Instance Config Parameters

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XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

// Instance config-params object

params.UCA0ABCTL = IUSCI_A0_UART.UCxABCTL_t {

// Auto Baud Rate Control Register

UCDELIM1: IUSCI_UART.UCDELIM1_OFF,

UCDELIM0: IUSCI_UART.UCDELIM0_OFF,

UCSTOE: IUSCI_UART.UCSTOE_OFF,

UCBTOE: IUSCI_UART.UCBTOE_OFF,

UCABDEN: IUSCI_UART.UCABDEN_OFF

};

params.UCA0BR0 = UChar 0;

// Baud rate control register 0

params.UCA0BR1 = UChar 0;

// Baud rate control register 1

params.UCA0CTL0 = IUSCI_A0_UART.UCxCTL0_t {

// Control Register 0

UCPEN: IUSCI_UART.UCPEN_OFF,

UCPAR: IUSCI_UART.UCPAR_OFF,

UCMSB: IUSCI.UCMSB_OFF,

UC7BIT: IUSCI.UC7BIT_OFF,

UCSPB: IUSCI_UART.UCSPB_OFF,

UCMODE: IUSCI_UART.UCMODE_0,

UCSYNC: IUSCI.UCSYNC_OFF

};

params.UCA0CTL1 = IUSCI_A0_UART.UCxCTL1_t {

// Control Register 1

UCSSEL: IUSCI_UART.UCSSEL_0,

UCRXEIE: IUSCI.UCRXEIE_OFF,

UCBRKIE: IUSCI.UCBRKIE_OFF,

UCDORM: IUSCI.UCDORM_OFF,

UCTXADDR: IUSCI.UCTXADDR_OFF,

UCTXBRK: IUSCI.UCTXBRK_OFF,

UCSWRST: IUSCI.UCSWRST

};

params.UCA0IRRCTL = IUSCI_A0_UART.UCxIRRCTL_t {

// IrDA Receive Control Register

UCIRRXFL5: IUSCI_UART.UCIRRXFL5_OFF,

UCIRRXFL4: IUSCI_UART.UCIRRXFL4_OFF,

UCIRRXFL3: IUSCI_UART.UCIRRXFL3_OFF,

UCIRRXFL2: IUSCI_UART.UCIRRXFL2_OFF,

UCIRRXFL1: IUSCI_UART.UCIRRXFL1_OFF,

UCIRRXFL0: IUSCI_UART.UCIRRXFL0_OFF,

UCIRRXPL: IUSCI_UART.UCIRRXPL_OFF,

UCIRRXFE: IUSCI_UART.UCIRRXFE_OFF

};

params.UCA0IRTCTL = IUSCI_A0_UART.UCxIRTCTL_t {

// IrDA Transmit Control Register

UCIRTXPL5: IUSCI_UART.UCIRTXPL5_OFF,

UCIRTXPL4: IUSCI_UART.UCIRTXPL4_OFF,

UCIRTXPL3: IUSCI_UART.UCIRTXPL3_OFF,

UCIRTXPL2: IUSCI_UART.UCIRTXPL2_OFF,

UCIRTXPL1: IUSCI_UART.UCIRTXPL1_OFF,

UCIRTXPL0: IUSCI_UART.UCIRTXPL0_OFF,

UCIRTXCLK: IUSCI_UART.UCIRTXCLK_OFF,

UCIREN: IUSCI_UART.UCIREN_OFF

};

params.UCA0MCTL = IUSCI_A0_UART.UCxMCTL_t {

// Modulation Control Register

UCBRF: IUSCI_UART.UCBRF_0,

UCBRS: IUSCI_UART.UCBRS_0,

UCOS16: IUSCI_UART.UCOS16_OFF

};

params.UCA0RXBUF = UChar 0;

// Receive Buffer Register

params.UCA0STAT = IUSCI_A0_UART.UCxSTAT_t {

// Status Register

UCLISTEN: IUSCI.UCLISTEN_OFF,

UCFE: IUSCI.UCFE_OFF,

UCOE: IUSCI.UCOE_OFF,

UCPE: IUSCI.UCPE_OFF,

UCBRK: IUSCI.UCBRK_OFF,

UCRXERR: IUSCI.UCRXERR_OFF,

UCADDR: IUSCI.UCADDR_OFF,

UCIDLE: IUSCI.UCIDLE_OFF,

UCBUSY: IUSCI.UCBUSY

};

params.UCA0TXBUF = UChar 0;

// Transmit Buffer Register

params.UCLKHz = Float 1000000;

// Stores the UCLK external clock frequency in float

params.forceSetDefaultRegister = USCI_A0_UART_2xx.ForceSetDefaultRegister_t[] [

// Determine if each Register needs to be forced set or not

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

params.name = String undefined;

// Specific peripheral name given by the device

params.owner = String undefined;

// String specifying the entity that manages the peripheral

config USCI_A0_UART_2xx.UCA0ABCTL // instance

index URL

Auto Baud Rate Control Register

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

params.UCA0ABCTL = IUSCI_A0_UART.UCxABCTL_t {

UCDELIM1: IUSCI_UART.UCDELIM1_OFF,

UCDELIM0: IUSCI_UART.UCDELIM0_OFF,

UCSTOE: IUSCI_UART.UCSTOE_OFF,

UCBTOE: IUSCI_UART.UCBTOE_OFF,

UCABDEN: IUSCI_UART.UCABDEN_OFF

};

config USCI_A0_UART_2xx.UCA0BR0 // instance

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Baud rate control register 0

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

params.UCA0BR0 = UChar 0;

config USCI_A0_UART_2xx.UCA0BR1 // instance

index URL

Baud rate control register 1

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

params.UCA0BR1 = UChar 0;

config USCI_A0_UART_2xx.UCA0CTL0 // instance

index URL

Control Register 0

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

params.UCA0CTL0 = IUSCI_A0_UART.UCxCTL0_t {

UCPEN: IUSCI_UART.UCPEN_OFF,

UCPAR: IUSCI_UART.UCPAR_OFF,

UCMSB: IUSCI.UCMSB_OFF,

UC7BIT: IUSCI.UC7BIT_OFF,

UCSPB: IUSCI_UART.UCSPB_OFF,

UCMODE: IUSCI_UART.UCMODE_0,

UCSYNC: IUSCI.UCSYNC_OFF

};

config USCI_A0_UART_2xx.UCA0CTL1 // instance

index URL

Control Register 1

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

params.UCA0CTL1 = IUSCI_A0_UART.UCxCTL1_t {

UCSSEL: IUSCI_UART.UCSSEL_0,

UCRXEIE: IUSCI.UCRXEIE_OFF,

UCBRKIE: IUSCI.UCBRKIE_OFF,

UCDORM: IUSCI.UCDORM_OFF,

UCTXADDR: IUSCI.UCTXADDR_OFF,

UCTXBRK: IUSCI.UCTXBRK_OFF,

UCSWRST: IUSCI.UCSWRST

};

config USCI_A0_UART_2xx.UCA0IRRCTL // instance

index URL

IrDA Receive Control Register

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

params.UCA0IRRCTL = IUSCI_A0_UART.UCxIRRCTL_t {

UCIRRXFL5: IUSCI_UART.UCIRRXFL5_OFF,

UCIRRXFL4: IUSCI_UART.UCIRRXFL4_OFF,

UCIRRXFL3: IUSCI_UART.UCIRRXFL3_OFF,

UCIRRXFL2: IUSCI_UART.UCIRRXFL2_OFF,

UCIRRXFL1: IUSCI_UART.UCIRRXFL1_OFF,

UCIRRXFL0: IUSCI_UART.UCIRRXFL0_OFF,

UCIRRXPL: IUSCI_UART.UCIRRXPL_OFF,

UCIRRXFE: IUSCI_UART.UCIRRXFE_OFF

};

config USCI_A0_UART_2xx.UCA0IRTCTL // instance

index URL

IrDA Transmit Control Register

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

params.UCA0IRTCTL = IUSCI_A0_UART.UCxIRTCTL_t {

UCIRTXPL5: IUSCI_UART.UCIRTXPL5_OFF,

UCIRTXPL4: IUSCI_UART.UCIRTXPL4_OFF,

UCIRTXPL3: IUSCI_UART.UCIRTXPL3_OFF,

UCIRTXPL2: IUSCI_UART.UCIRTXPL2_OFF,

UCIRTXPL1: IUSCI_UART.UCIRTXPL1_OFF,

UCIRTXPL0: IUSCI_UART.UCIRTXPL0_OFF,

UCIRTXCLK: IUSCI_UART.UCIRTXCLK_OFF,

UCIREN: IUSCI_UART.UCIREN_OFF

};

config USCI_A0_UART_2xx.UCA0MCTL // instance

index URL

Modulation Control Register

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

params.UCA0MCTL = IUSCI_A0_UART.UCxMCTL_t {

UCBRF: IUSCI_UART.UCBRF_0,

UCBRS: IUSCI_UART.UCBRS_0,

UCOS16: IUSCI_UART.UCOS16_OFF

};

config USCI_A0_UART_2xx.UCA0RXBUF // instance

index URL

Receive Buffer Register

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

params.UCA0RXBUF = UChar 0;

config USCI_A0_UART_2xx.UCA0STAT // instance

index URL

Status Register

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

params.UCA0STAT = IUSCI_A0_UART.UCxSTAT_t {

UCLISTEN: IUSCI.UCLISTEN_OFF,

UCFE: IUSCI.UCFE_OFF,

UCOE: IUSCI.UCOE_OFF,

UCPE: IUSCI.UCPE_OFF,

UCBRK: IUSCI.UCBRK_OFF,

UCRXERR: IUSCI.UCRXERR_OFF,

UCADDR: IUSCI.UCADDR_OFF,

UCIDLE: IUSCI.UCIDLE_OFF,

UCBUSY: IUSCI.UCBUSY

};

config USCI_A0_UART_2xx.UCA0TXBUF // instance

index URL

Transmit Buffer Register

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

params.UCA0TXBUF = UChar 0;

config USCI_A0_UART_2xx.UCLKHz // instance

index URL

Stores the UCLK external clock frequency in float

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

params.UCLKHz = Float 1000000;

config USCI_A0_UART_2xx.forceSetDefaultRegister // instance

index URL

Determine if each Register needs to be forced set or not

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

const params.forceSetDefaultRegister = USCI_A0_UART_2xx.ForceSetDefaultRegister_t[] [

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

config USCI_A0_UART_2xx.name // instance

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Specific peripheral name given by the device

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

params.name = String undefined;

DETAILS

Devices can have more than one peripheral of the same type. In such cases, device data sheets give different names to the instances of a same peripheral. For example, the name for a timer module could be TimerA3, and a device that has two such timers can name them TA0 and TA1.

config USCI_A0_UART_2xx.owner // instance

index URL

String specifying the entity that manages the peripheral

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

...

params.owner = String undefined;

Instance Creation

index URL

XDCscript usage meta-domain

var params = new USCI_A0_UART_2xx.Params;

// Allocate instance config-params