enum USCI_A1_UART_2xx.UC7BIT_t |
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Character length. Selects 7-bit or 8-bit character length
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UC7BIT_t
const USCI_A1_UART_2xx.UC7BIT_OFF;
// 8-bit
const USCI_A1_UART_2xx.UC7BIT;
// 7-bit
enum USCI_A1_UART_2xx.UCABDEN_t |
|
Automatic baud rate detect enable
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCABDEN_t
const USCI_A1_UART_2xx.UCABDEN_OFF;
// Baud rate detection disabled. Length of break and synch field is not
measured
const USCI_A1_UART_2xx.UCABDEN;
// Baud rate detection enabled. Length of break and synch field is
measured and baud rate settings are changed accordingly
enum USCI_A1_UART_2xx.UCADDR_t |
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Address received in address-bit multiprocessor mode
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCADDR_t
const USCI_A1_UART_2xx.UCADDR_OFF;
// Received character is data
const USCI_A1_UART_2xx.UCADDR;
// Received character is an address
enum USCI_A1_UART_2xx.UCBRF_t |
|
First modulation stage select
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCBRF_t
const USCI_A1_UART_2xx.UCBRF_0;
// First stage 0
const USCI_A1_UART_2xx.UCBRF_1;
// First stage 1
const USCI_A1_UART_2xx.UCBRF_2;
// First stage 2
const USCI_A1_UART_2xx.UCBRF_3;
// First stage 3
const USCI_A1_UART_2xx.UCBRF_4;
// First stage 4
const USCI_A1_UART_2xx.UCBRF_5;
// First stage 5
const USCI_A1_UART_2xx.UCBRF_6;
// First stage 6
const USCI_A1_UART_2xx.UCBRF_7;
// First stage 7
const USCI_A1_UART_2xx.UCBRF_8;
// First stage 8
const USCI_A1_UART_2xx.UCBRF_9;
// First stage 9
const USCI_A1_UART_2xx.UCBRF_10;
// First stage 10
const USCI_A1_UART_2xx.UCBRF_11;
// First stage 11
const USCI_A1_UART_2xx.UCBRF_12;
// First stage 12
const USCI_A1_UART_2xx.UCBRF_13;
// First stage 13
const USCI_A1_UART_2xx.UCBRF_14;
// First stage 14
const USCI_A1_UART_2xx.UCBRF_15;
// First stage 15
enum USCI_A1_UART_2xx.UCBRKIE_t |
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Receive break character interrupt-enable
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCBRKIE_t
const USCI_A1_UART_2xx.UCBRKIE_OFF;
// Received break characters do not set UCAxRXIFG
const USCI_A1_UART_2xx.UCBRKIE;
// Received break characters set UCAxRXIFG
enum USCI_A1_UART_2xx.UCBRK_t |
|
Break detect flag
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCBRK_t
const USCI_A1_UART_2xx.UCBRK_OFF;
// No break condition
const USCI_A1_UART_2xx.UCBRK;
// Break condition occurred
enum USCI_A1_UART_2xx.UCBRS_t |
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Second modulation stage select
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCBRS_t
const USCI_A1_UART_2xx.UCBRS_0;
// Second stage 0
const USCI_A1_UART_2xx.UCBRS_1;
// Second stage 1
const USCI_A1_UART_2xx.UCBRS_2;
// Second stage 2
const USCI_A1_UART_2xx.UCBRS_3;
// Second stage 3
const USCI_A1_UART_2xx.UCBRS_4;
// Second stage 4
const USCI_A1_UART_2xx.UCBRS_5;
// Second stage 5
const USCI_A1_UART_2xx.UCBRS_6;
// Second stage 6
const USCI_A1_UART_2xx.UCBRS_7;
// Second stage 7
enum USCI_A1_UART_2xx.UCBTOE_t |
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Break time out error
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCBTOE_t
const USCI_A1_UART_2xx.UCBTOE_OFF;
// No error
const USCI_A1_UART_2xx.UCBTOE;
// Length of break field exceeded 22 bit times
enum USCI_A1_UART_2xx.UCBUSY_t |
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USCI busy. This bit indicates if a transmit or receive operation is in progress
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCBUSY_t
const USCI_A1_UART_2xx.UCBUSY_OFF;
// USCI inactive
const USCI_A1_UART_2xx.UCBUSY;
// USCI transmitting or receiving
enum USCI_A1_UART_2xx.UCDELIM0_t |
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Break/synch delimiter length bit 0
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCDELIM0_t
const USCI_A1_UART_2xx.UCDELIM0_OFF;
// Break Sync Delimiter bit 0 Off
const USCI_A1_UART_2xx.UCDELIM0;
// Break Sync Delimiter bit 0 On
enum USCI_A1_UART_2xx.UCDELIM1_t |
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Break/synch delimiter length bit 1
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCDELIM1_t
const USCI_A1_UART_2xx.UCDELIM1_OFF;
// Break Sync Delimiter bit 1 Off
const USCI_A1_UART_2xx.UCDELIM1;
// Break Sync Delimiter bit 1 On
enum USCI_A1_UART_2xx.UCDORM_t |
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Dormant. Puts USCI into sleep mode
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCDORM_t
const USCI_A1_UART_2xx.UCDORM_OFF;
// Not dormant. All received characters will set UCAxRXIFG
const USCI_A1_UART_2xx.UCDORM;
// Dormant. Only characters that are preceded by an idle-line or with
address bit set will set UCAxRXIFG. In UART mode with automatic baud
rate detection only the combination of a break and synch field will set
UCAxRXIFG
enum USCI_A1_UART_2xx.UCFE_t |
|
Framing error flag
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCFE_t
const USCI_A1_UART_2xx.UCFE_OFF;
// 0 No error
const USCI_A1_UART_2xx.UCFE;
// Character received with low stop bit
enum USCI_A1_UART_2xx.UCIDLE_t |
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Idle line detected in idle-line multiprocessor mode
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIDLE_t
const USCI_A1_UART_2xx.UCIDLE_OFF;
// No idle line detected
const USCI_A1_UART_2xx.UCIDLE;
// Idle line detected
enum USCI_A1_UART_2xx.UCIREN_t |
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IrDA encoder/decoder enable
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIREN_t
const USCI_A1_UART_2xx.UCIREN_OFF;
// IrDA encoder/decoder disabled
const USCI_A1_UART_2xx.UCIREN;
// IrDA encoder/decoder enabled
enum USCI_A1_UART_2xx.UCIRRXFE_t |
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IrDA receive filter enabled
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRRXFE_t
const USCI_A1_UART_2xx.UCIRRXFE_OFF;
// Receive filter disabled
const USCI_A1_UART_2xx.UCIRRXFE;
// Receive filter enabled
enum USCI_A1_UART_2xx.UCIRRXFL0_t |
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IRDA Receive Filter Length Bit 0
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRRXFL0_t
const USCI_A1_UART_2xx.UCIRRXFL0_OFF;
// Bit 0 OFF
const USCI_A1_UART_2xx.UCIRRXFL0;
// Bit 0 ON
enum USCI_A1_UART_2xx.UCIRRXFL1_t |
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IRDA Receive Filter Length Bit 1
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRRXFL1_t
const USCI_A1_UART_2xx.UCIRRXFL1_OFF;
// Bit 1 OFF
const USCI_A1_UART_2xx.UCIRRXFL1;
// Bit 1 ON
enum USCI_A1_UART_2xx.UCIRRXFL2_t |
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IRDA Receive Filter Length Bit 2
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRRXFL2_t
const USCI_A1_UART_2xx.UCIRRXFL2_OFF;
// Bit 2 OFF
const USCI_A1_UART_2xx.UCIRRXFL2;
// Bit 2 ON
enum USCI_A1_UART_2xx.UCIRRXFL3_t |
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IRDA Receive Filter Length Bit 3
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRRXFL3_t
const USCI_A1_UART_2xx.UCIRRXFL3_OFF;
// Bit 3 OFF
const USCI_A1_UART_2xx.UCIRRXFL3;
// Bit 3 ON
enum USCI_A1_UART_2xx.UCIRRXFL4_t |
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IRDA Receive Filter Length Bit 4
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRRXFL4_t
const USCI_A1_UART_2xx.UCIRRXFL4_OFF;
// Bit 4 OFF
const USCI_A1_UART_2xx.UCIRRXFL4;
// Bit 4 ON
enum USCI_A1_UART_2xx.UCIRRXFL5_t |
|
IRDA Receive Filter Length Bit 5
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRRXFL5_t
const USCI_A1_UART_2xx.UCIRRXFL5_OFF;
// Bit 5 OFF
const USCI_A1_UART_2xx.UCIRRXFL5;
// Bit 5 ON
enum USCI_A1_UART_2xx.UCIRRXPL_t |
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IrDA receive input UCAxRXD polarity
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRRXPL_t
const USCI_A1_UART_2xx.UCIRRXPL_OFF;
// IrDA transceiver delivers a high pulse when a light pulse is seen
const USCI_A1_UART_2xx.UCIRRXPL;
// IrDA transceiver delivers a low pulse when a light pulse is seen
enum USCI_A1_UART_2xx.UCIRTXCLK_t |
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IrDA transmit pulse clock select
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRTXCLK_t
const USCI_A1_UART_2xx.UCIRTXCLK_OFF;
// BRCLK
const USCI_A1_UART_2xx.UCIRTXCLK;
// BITCLK16 when UCOS16 = 1. Otherwise, BRCLK
enum USCI_A1_UART_2xx.UCIRTXPL0_t |
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IRDA Transmit Pulse Length Bit 0
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRTXPL0_t
const USCI_A1_UART_2xx.UCIRTXPL0_OFF;
// Bit 0 OFF
const USCI_A1_UART_2xx.UCIRTXPL0;
// Bit 0 ON
enum USCI_A1_UART_2xx.UCIRTXPL1_t |
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IRDA Transmit Pulse Length Bit 1
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRTXPL1_t
const USCI_A1_UART_2xx.UCIRTXPL1_OFF;
// Bit 1 OFF
const USCI_A1_UART_2xx.UCIRTXPL1;
// Bit 1 ON
enum USCI_A1_UART_2xx.UCIRTXPL2_t |
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IRDA Transmit Pulse Length Bit 2
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRTXPL2_t
const USCI_A1_UART_2xx.UCIRTXPL2_OFF;
// Bit 2 OFF
const USCI_A1_UART_2xx.UCIRTXPL2;
// Bit 2 ON
enum USCI_A1_UART_2xx.UCIRTXPL3_t |
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IRDA Transmit Pulse Length Bit 3
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRTXPL3_t
const USCI_A1_UART_2xx.UCIRTXPL3_OFF;
// Bit 3 OFF
const USCI_A1_UART_2xx.UCIRTXPL3;
// Bit 3 ON
enum USCI_A1_UART_2xx.UCIRTXPL4_t |
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IRDA Transmit Pulse Length Bit 4
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRTXPL4_t
const USCI_A1_UART_2xx.UCIRTXPL4_OFF;
// Bit 4 OFF
const USCI_A1_UART_2xx.UCIRTXPL4;
// Bit 4 ON
enum USCI_A1_UART_2xx.UCIRTXPL5_t |
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IRDA Transmit Pulse Length Bit 5
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCIRTXPL5_t
const USCI_A1_UART_2xx.UCIRTXPL5_OFF;
// Bit 5 OFF
const USCI_A1_UART_2xx.UCIRTXPL5;
// Bit 5 ON
enum USCI_A1_UART_2xx.UCLISTEN_t |
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Listen enable. The UCLISTEN bit selects loopback mode
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCLISTEN_t
const USCI_A1_UART_2xx.UCLISTEN_OFF;
// Disabled
const USCI_A1_UART_2xx.UCLISTEN;
// Enabled. UCAxTXD is internally fed back to the receiver
enum USCI_A1_UART_2xx.UCMODE_ASYNC_t |
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USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCMODE_ASYNC_t
const USCI_A1_UART_2xx.UCMODE_0;
// UART Mode
const USCI_A1_UART_2xx.UCMODE_1;
// Idle-Line Multiprocessor Mode
const USCI_A1_UART_2xx.UCMODE_2;
// Address-Bit Multiprocessor Mode
const USCI_A1_UART_2xx.UCMODE_3;
// UART Mode with automatic baud rate detection
enum USCI_A1_UART_2xx.UCMODE_SYNC_t |
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USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCMODE_SYNC_t
const USCI_A1_UART_2xx.UCMODE_0;
// 3-Pin SPI
const USCI_A1_UART_2xx.UCMODE_1;
// 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
const USCI_A1_UART_2xx.UCMODE_2;
// 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
const USCI_A1_UART_2xx.UCMODE_3;
// I2C Mode
enum USCI_A1_UART_2xx.UCMSB_t |
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MSB first select. Controls the direction of the receive and transmit shift register
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCMSB_t
const USCI_A1_UART_2xx.UCMSB_OFF;
// LSB first
const USCI_A1_UART_2xx.UCMSB;
// MSB first
enum USCI_A1_UART_2xx.UCOE_t |
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Overrun error flag
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCOE_t
const USCI_A1_UART_2xx.UCOE_OFF;
// No error
const USCI_A1_UART_2xx.UCOE;
// Overrun error occurred
enum USCI_A1_UART_2xx.UCOS16_t |
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Oversampling mode enabled
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCOS16_t
const USCI_A1_UART_2xx.UCOS16_OFF;
// Disabled
const USCI_A1_UART_2xx.UCOS16;
// Enabled
enum USCI_A1_UART_2xx.UCPAR_t |
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Parity select. UCPAR is not used when parity is disabled
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCPAR_t
const USCI_A1_UART_2xx.UCPAR_OFF;
// Odd parity
const USCI_A1_UART_2xx.UCPAR;
// Even parity
enum USCI_A1_UART_2xx.UCPEN_t |
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Parity enable
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCPEN_t
const USCI_A1_UART_2xx.UCPEN_OFF;
// Parity Disabled
const USCI_A1_UART_2xx.UCPEN;
// Parity Enabled
enum USCI_A1_UART_2xx.UCPE_t |
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Parity error flag. When UCPEN = 0, UCPE is read as 0
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCPE_t
const USCI_A1_UART_2xx.UCPE_OFF;
// No error
const USCI_A1_UART_2xx.UCPE;
// Character received with parity error
enum USCI_A1_UART_2xx.UCRXEIE_t |
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Receive erroneous-character interrupt-enable
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCRXEIE_t
const USCI_A1_UART_2xx.UCRXEIE_OFF;
// Erroneous characters rejected and UCAxRXIFG is not set
const USCI_A1_UART_2xx.UCRXEIE;
// Erroneous characters received will set UCAxRXIFG
enum USCI_A1_UART_2xx.UCRXERR_t |
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Bit 2 Receive error flag. This bit indicates a character was received with error(s).
When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also
set. UCRXERR is cleared when UCAxRXBUF is read
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCRXERR_t
const USCI_A1_UART_2xx.UCRXERR_OFF;
// No receive errors detected
const USCI_A1_UART_2xx.UCRXERR;
// Receive error detected
enum USCI_A1_UART_2xx.UCSPB_t |
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Stop bit select. Number of stop bits
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCSPB_t
const USCI_A1_UART_2xx.UCSPB_OFF;
// One stop bit
const USCI_A1_UART_2xx.UCSPB;
// Two stop bits
enum USCI_A1_UART_2xx.UCSSEL_UART_t |
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USCI clock source select. These bits select the BRCLK source clock
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCSSEL_UART_t
const USCI_A1_UART_2xx.UCSSEL_0;
// UCLK
const USCI_A1_UART_2xx.UCSSEL_1;
// ACLK
const USCI_A1_UART_2xx.UCSSEL_2;
// SMCLK
enum USCI_A1_UART_2xx.UCSTOE_t |
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Synch field time out error
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCSTOE_t
const USCI_A1_UART_2xx.UCSTOE_OFF;
// No error
const USCI_A1_UART_2xx.UCSTOE;
// Length of synch field exceeded measurable time
enum USCI_A1_UART_2xx.UCSWRST_t |
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Software reset enable
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCSWRST_t
const USCI_A1_UART_2xx.UCSWRST_OFF;
// Disabled. USCI reset released for operation
const USCI_A1_UART_2xx.UCSWRST;
// Enabled. USCI logic held in reset state
enum USCI_A1_UART_2xx.UCSYNC_t |
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Synchronous mode enable
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCSYNC_t
const USCI_A1_UART_2xx.UCSYNC_OFF;
// Asynchronous mode
const USCI_A1_UART_2xx.UCSYNC;
// Synchronous Mode
enum USCI_A1_UART_2xx.UCTXADDR_t |
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Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCTXADDR_t
const USCI_A1_UART_2xx.UCTXADDR_OFF;
// Next frame transmitted is data
const USCI_A1_UART_2xx.UCTXADDR;
// Next frame transmitted is an address
enum USCI_A1_UART_2xx.UCTXBRK_t |
|
Transmit break. Transmits a break with the next write to the transmit buffer.
In UART mode with automatic baud rate detection 055h must be written
into UCAxTXBUF to generate the required break/synch fields. Otherwise
0h must be written into the transmit buffer
XDCscript usage |
meta-domain |
values of type USCI_A1_UART_2xx.UCTXBRK_t
const USCI_A1_UART_2xx.UCTXBRK_OFF;
// Next frame transmitted is not a break
const USCI_A1_UART_2xx.UCTXBRK;
// Next frame transmitted is a break or a break/synch
struct USCI_A1_UART_2xx.ForceSetDefaultRegister_t |
|
Force Set Default Register
XDCscript usage |
meta-domain |
var obj = new USCI_A1_UART_2xx.ForceSetDefaultRegister_t;
obj.register = String ...
obj.regForceSet = Bool ...
DETAILS
Type to store if each register needs to be forced initialized
even if the register is in default state.
SEE
struct USCI_A1_UART_2xx.UCxABCTL_t |
|
XDCscript usage |
meta-domain |
var obj = new USCI_A1_UART_2xx.UCxABCTL_t;
// Break/synch delimiter length
00 1 bit time
01 2 bit times
10 3 bit times
11 4 bit times
// Break/synch delimiter length
00 1 bit time
01 2 bit times
10 3 bit times
11 4 bit times
// Synch field time out error
0 No error
1 Length of synch field exceeded measurable time
// Break time out error
0 No error
1 Length of break field exceeded 22 bit times
// Automatic baud rate detect enable
0 Baud rate detection disabled. Length of break and synch field is not
measured.
1 Baud rate detection enabled. Length of break and synch field is
measured and baud rate settings are changed accordingly
struct USCI_A1_UART_2xx.UCxCTL0_t |
|
XDCscript usage |
meta-domain |
var obj = new USCI_A1_UART_2xx.UCxCTL0_t;
// Parity enable
0 Parity disabled.
1 Parity enabled. Parity bit is generated (UCAxTXD) and expected
(UCAxRXD). In address-bit multiprocessor mode, the address bit is
included in the parity calculation
// Parity select. UCPAR is not used when parity is disabled.
0 Odd parity
1 Even parity
// MSB first select. Controls the direction of the receive and transmit shift
register.
0 LSB first
1 MSB first
// Character length. Selects 7-bit or 8-bit character length.
0 8-bit data
1 7-bit data
// Stop bit select. Number of stop bits.
0 One stop bit
1 Two stop bits
// USCI mode. The UCMODEx bits select the asynchronous mode when
UCSYNC = 0.
00 UART Mode.
01 Idle-Line Multiprocessor Mode.
10 Address-Bit Multiprocessor Mode.
11 UART Mode with automatic baud rate detection
// Synchronous mode enable
0 Asynchronous mode
1 Synchronous Mode
struct USCI_A1_UART_2xx.UCxCTL1_t |
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XDCscript usage |
meta-domain |
var obj = new USCI_A1_UART_2xx.UCxCTL1_t;
// USCI clock source select. These bits select the BRCLK source clock.
00 UCLK
01 ACLK
10 SMCLK
11 SMCLK
// Receive erroneous-character interrupt-enable
0 Erroneous characters rejected and UCAxRXIFG is not set
1 Erroneous characters received will set UCAxRXIFG
// Receive break character interrupt-enable
0 Received break characters do not set UCAxRXIFG.
1 Received break characters set UCAxRXIFG
// Dormant. Puts USCI into sleep mode.
0 Not dormant. All received characters will set UCAxRXIFG.
1 Dormant. Only characters that are preceded by an idle-line or with
address bit set will set UCAxRXIFG. In UART mode with automatic baud
rate detection only the combination of a break and synch field will set
UCAxRXIFG
// Transmit address. Next frame to be transmitted will be marked as address
depending on the selected multiprocessor mode.
0 Next frame transmitted is data
1 Next frame transmitted is an address
// Transmit break. Transmits a break with the next write to the transmit buffer.
In UART mode with automatic baud rate detection 055h must be written
into UCAxTXBUF to generate the required break/synch fields. Otherwise
0h must be written into the transmit buffer.
0 Next frame transmitted is not a break
1 Next frame transmitted is a break or a break/synch
// Software reset enable
0 Disabled. USCI reset released for operation.
1 Enabled. USCI logic held in reset state
struct USCI_A1_UART_2xx.UCxIRRCTL_t |
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XDCscript usage |
meta-domain |
var obj = new USCI_A1_UART_2xx.UCxIRRCTL_t;
// IRDA Receive Filter Length Bit 5
// IRDA Receive Filter Length Bit 4
// IRDA Receive Filter Length Bit 3
// IRDA Receive Filter Length Bit 2
// IRDA Receive Filter Length Bit 1
// IRDA Receive Filter Length Bit 0
// IrDA receive input UCAxRXD polarity
0 IrDA transceiver delivers a high pulse when a light pulse is seen
1 IrDA transceiver delivers a low pulse when a light pulse is seen
// IrDA receive filter enabled
0 Receive filter disabled
1 Receive filter enabled
struct USCI_A1_UART_2xx.UCxIRTCTL_t |
|
XDCscript usage |
meta-domain |
var obj = new USCI_A1_UART_2xx.UCxIRTCTL_t;
// IRDA Transmit Pulse Length Bit 5
// IRDA Transmit Pulse Length Bit 4
// IRDA Transmit Pulse Length Bit 3
// IRDA Transmit Pulse Length Bit 2
// IRDA Transmit Pulse Length Bit 1
// IRDA Transmit Pulse Length Bit 0
// IrDA transmit pulse clock select
0 BRCLK
1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK
// IrDA encoder/decoder enable.
0 IrDA encoder/decoder disabled
1 IrDA encoder/decoder enabled
struct USCI_A1_UART_2xx.UCxMCTL_t |
|
XDCscript usage |
meta-domain |
var obj = new USCI_A1_UART_2xx.UCxMCTL_t;
// First modulation stage select. These bits determine the modulation pattern
for BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0
// Second modulation stage select. These bits determine the modulation
pattern for BITCLK
// Oversampling mode enabled
0 Disabled
1 Enabled
struct USCI_A1_UART_2xx.UCxSTAT_t |
|
XDCscript usage |
meta-domain |
var obj = new USCI_A1_UART_2xx.UCxSTAT_t;
// Listen enable. The UCLISTEN bit selects loopback mode.
0 Disabled
1 Enabled. UCAxTXD is internally fed back to the receiver
// Framing error flag
0 No error
1 Character received with low stop bit
// Overrun error flag. This bit is set when a character is transferred into
UCAxRXBUF before the previous character was read. UCOE is cleared
automatically when UCxRXBUF is read, and must not be cleared by
software. Otherwise, it will not function correctly.
0 No error
1 Overrun error occurred
// Parity error flag. When UCPEN = 0, UCPE is read as 0.
0 No error
1 Character received with parity error
// Break detect flag
0 No break condition
1 Break condition occurred
// Receive error flag. This bit indicates a character was received with error(s).
When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also
set. UCRXERR is cleared when UCAxRXBUF is read.
0 No receive errors detected
1 Receive error detected
// Address received in address-bit multiprocessor mode.
0 Received character is data
1 Received character is an address
// Idle line detected in idle-line multiprocessor mode.
0 No idle line detected
1 Idle line detected
// USCI busy. This bit indicates if a transmit or receive operation is in
progress.
0 USCI inactive
1 USCI transmitting or receiving
USCI_A1_UART_2xx.addPeripheralsMap() // module-wide |
|
Create a map of all peripherals available on a device
XDCscript usage |
meta-domain |
ARGUMENTS
DETAILS
The config parameter
peripherals is by default undefined in an
xdc.platform.ICpuDataSheet instance. This function gathers
all instance configuration parameters that are of the type
xdc.platform.IPeripheral into the map
peripherals.
USCI_A1_UART_2xx.getAll() // module-wide |
|
Find all peripherals of a certain type
XDCscript usage |
meta-domain |
DETAILS
The type of the peripherals returned is defined by the type of the
caller.
RETURNS
Returns an array of IPeripheral instances
USCI_A1_UART_2xx.getRegisters() // module-wide |
|
Find all registers defined by the peripheral
XDCscript usage |
meta-domain |
USCI_A1_UART_2xx.getRegisters() returns String[]
RETURNS
Returns an array of register names
Instance Config Parameters |
|
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
// Instance config-params object
// Auto Baud Rate Control Register
};
params.UCA0BR0 = UChar 0;
// Baud rate control register 0
params.UCA0BR1 = UChar 0;
// Baud rate control register 1
// Control Register 0
};
// Control Register 1
};
// IrDA Receive Control Register
};
// IrDA Transmit Control Register
};
// Modulation Control Register
};
params.UCA0RXBUF = UChar 0;
// Receive Buffer Register
// Status Register
};
params.UCA0TXBUF = UChar 0;
// Transmit Buffer Register
params.UCLKHz = Float 1000000;
// Stores the UCLK external clock frequency in float
// Determine if each Register needs to be forced set or not
{
register: "UCA1CTL0",
regForceSet: false
},
{
register: "UCA1CTL1",
regForceSet: false
},
{
register: "UCA1BR0",
regForceSet: false
},
{
register: "UCA1BR1",
regForceSet: false
},
{
register: "UCA1MCTL",
regForceSet: false
},
{
register: "UCA1STAT",
regForceSet: false
},
{
register: "UCA1RXBUF",
regForceSet: false
},
{
register: "UCA1TXBUF",
regForceSet: false
},
{
register: "UCA1ABCTL",
regForceSet: false
},
{
register: "UCA1IRTCTL",
regForceSet: false
},
{
register: "UCA1IRRCTL",
regForceSet: false
}
];
params.name = String undefined;
// Specific peripheral name given by the device
params.owner = String undefined;
// String specifying the entity that manages the peripheral
config USCI_A1_UART_2xx.UCA0ABCTL // instance |
|
Auto Baud Rate Control Register
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
};
config USCI_A1_UART_2xx.UCA0BR0 // instance |
|
Baud rate control register 0
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
params.UCA0BR0 = UChar 0;
config USCI_A1_UART_2xx.UCA0BR1 // instance |
|
Baud rate control register 1
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
params.UCA0BR1 = UChar 0;
config USCI_A1_UART_2xx.UCA0CTL0 // instance |
|
Control Register 0
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
};
config USCI_A1_UART_2xx.UCA0CTL1 // instance |
|
Control Register 1
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
};
config USCI_A1_UART_2xx.UCA0IRRCTL // instance |
|
IrDA Receive Control Register
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
};
config USCI_A1_UART_2xx.UCA0IRTCTL // instance |
|
IrDA Transmit Control Register
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
};
config USCI_A1_UART_2xx.UCA0MCTL // instance |
|
Modulation Control Register
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
};
config USCI_A1_UART_2xx.UCA0RXBUF // instance |
|
Receive Buffer Register
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
params.UCA0RXBUF = UChar 0;
config USCI_A1_UART_2xx.UCA0STAT // instance |
|
Status Register
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
};
config USCI_A1_UART_2xx.UCA0TXBUF // instance |
|
Transmit Buffer Register
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
params.UCA0TXBUF = UChar 0;
config USCI_A1_UART_2xx.UCLKHz // instance |
|
Stores the UCLK external clock frequency in float
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
params.UCLKHz = Float 1000000;
config USCI_A1_UART_2xx.forceSetDefaultRegister // instance |
|
Determine if each Register needs to be forced set or not
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
{
register: "UCA1CTL0",
regForceSet: false
},
{
register: "UCA1CTL1",
regForceSet: false
},
{
register: "UCA1BR0",
regForceSet: false
},
{
register: "UCA1BR1",
regForceSet: false
},
{
register: "UCA1MCTL",
regForceSet: false
},
{
register: "UCA1STAT",
regForceSet: false
},
{
register: "UCA1RXBUF",
regForceSet: false
},
{
register: "UCA1TXBUF",
regForceSet: false
},
{
register: "UCA1ABCTL",
regForceSet: false
},
{
register: "UCA1IRTCTL",
regForceSet: false
},
{
register: "UCA1IRRCTL",
regForceSet: false
}
];
config USCI_A1_UART_2xx.name // instance |
|
Specific peripheral name given by the device
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
params.name = String undefined;
DETAILS
Devices can have more than one peripheral of the same type. In such
cases, device data sheets give different names to the instances of a
same peripheral. For example, the name for a timer module could be
TimerA3, and a device that has two such timers can name them TA0
and TA1.
config USCI_A1_UART_2xx.owner // instance |
|
String specifying the entity that manages the peripheral
XDCscript usage |
meta-domain |
var params = new USCI_A1_UART_2xx.Params;
...
params.owner = String undefined;
USCI_A1_UART_2xx.getUCRXIE() // instance |
|
XDCscript usage |
meta-domain |
inst.getUCRXIE() returns Bool
USCI_A1_UART_2xx.getUCTXIE() // instance |
|
XDCscript usage |
meta-domain |
inst.getUCTXIE() returns Bool
USCI_A1_UART_2xx.setUCRXIE() // instance |
|
XDCscript usage |
meta-domain |
inst.setUCRXIE(Bool set) returns Bool
USCI_A1_UART_2xx.setUCTXIE() // instance |
|
XDCscript usage |
meta-domain |
inst.setUCTXIE(Bool set) returns Bool