enum IUSCI_A0_UART.UC7BIT_t |
|
Character length. Selects 7-bit or 8-bit character length
enum UC7BIT_t {
UC7BIT_OFF,
// 8-bit
UC7BIT
// 7-bit
};
enum IUSCI_A0_UART.UCABDEN_t |
|
Automatic baud rate detect enable
enum UCABDEN_t {
UCABDEN_OFF,
// Baud rate detection disabled. Length of break and synch field is not
measured
UCABDEN
// Baud rate detection enabled. Length of break and synch field is
measured and baud rate settings are changed accordingly
};
enum IUSCI_A0_UART.UCADDR_t |
|
Address received in address-bit multiprocessor mode
enum UCADDR_t {
UCADDR_OFF,
// Received character is data
UCADDR
// Received character is an address
};
enum IUSCI_A0_UART.UCBRF_t |
|
First modulation stage select
enum UCBRF_t {
UCBRF_0,
// First stage 0
UCBRF_1,
// First stage 1
UCBRF_2,
// First stage 2
UCBRF_3,
// First stage 3
UCBRF_4,
// First stage 4
UCBRF_5,
// First stage 5
UCBRF_6,
// First stage 6
UCBRF_7,
// First stage 7
UCBRF_8,
// First stage 8
UCBRF_9,
// First stage 9
UCBRF_10,
// First stage 10
UCBRF_11,
// First stage 11
UCBRF_12,
// First stage 12
UCBRF_13,
// First stage 13
UCBRF_14,
// First stage 14
UCBRF_15
// First stage 15
};
enum IUSCI_A0_UART.UCBRKIE_t |
|
Receive break character interrupt-enable
enum UCBRKIE_t {
UCBRKIE_OFF,
// Received break characters do not set UCAxRXIFG
UCBRKIE
// Received break characters set UCAxRXIFG
};
enum IUSCI_A0_UART.UCBRK_t |
|
Break detect flag
enum UCBRK_t {
UCBRK_OFF,
// No break condition
UCBRK
// Break condition occurred
};
enum IUSCI_A0_UART.UCBRS_t |
|
Second modulation stage select
enum UCBRS_t {
UCBRS_0,
// Second stage 0
UCBRS_1,
// Second stage 1
UCBRS_2,
// Second stage 2
UCBRS_3,
// Second stage 3
UCBRS_4,
// Second stage 4
UCBRS_5,
// Second stage 5
UCBRS_6,
// Second stage 6
UCBRS_7
// Second stage 7
};
enum IUSCI_A0_UART.UCBTOE_t |
|
Break time out error
enum UCBTOE_t {
UCBTOE_OFF,
// No error
UCBTOE
// Length of break field exceeded 22 bit times
};
enum IUSCI_A0_UART.UCBUSY_t |
|
USCI busy. This bit indicates if a transmit or receive operation is in progress
enum UCBUSY_t {
UCBUSY_OFF,
// USCI inactive
UCBUSY
// USCI transmitting or receiving
};
enum IUSCI_A0_UART.UCDELIM0_t |
|
Break/synch delimiter length bit 0
enum UCDELIM0_t {
UCDELIM0_OFF,
// Break Sync Delimiter bit 0 Off
UCDELIM0
// Break Sync Delimiter bit 0 On
};
enum IUSCI_A0_UART.UCDELIM1_t |
|
Break/synch delimiter length bit 1
enum UCDELIM1_t {
UCDELIM1_OFF,
// Break Sync Delimiter bit 1 Off
UCDELIM1
// Break Sync Delimiter bit 1 On
};
enum IUSCI_A0_UART.UCDORM_t |
|
Dormant. Puts USCI into sleep mode
enum UCDORM_t {
UCDORM_OFF,
// Not dormant. All received characters will set UCAxRXIFG
UCDORM
// Dormant. Only characters that are preceded by an idle-line or with
address bit set will set UCAxRXIFG. In UART mode with automatic baud
rate detection only the combination of a break and synch field will set
UCAxRXIFG
};
enum IUSCI_A0_UART.UCFE_t |
|
Framing error flag
enum UCFE_t {
UCFE_OFF,
// 0 No error
UCFE
// Character received with low stop bit
};
enum IUSCI_A0_UART.UCIDLE_t |
|
Idle line detected in idle-line multiprocessor mode
enum UCIDLE_t {
UCIDLE_OFF,
// No idle line detected
UCIDLE
// Idle line detected
};
enum IUSCI_A0_UART.UCIREN_t |
|
IrDA encoder/decoder enable
enum UCIREN_t {
UCIREN_OFF,
// IrDA encoder/decoder disabled
UCIREN
// IrDA encoder/decoder enabled
};
enum IUSCI_A0_UART.UCIRRXFE_t |
|
IrDA receive filter enabled
enum UCIRRXFE_t {
UCIRRXFE_OFF,
// Receive filter disabled
UCIRRXFE
// Receive filter enabled
};
enum IUSCI_A0_UART.UCIRRXFL0_t |
|
IRDA Receive Filter Length Bit 0
enum UCIRRXFL0_t {
UCIRRXFL0_OFF,
// Bit 0 OFF
UCIRRXFL0
// Bit 0 ON
};
enum IUSCI_A0_UART.UCIRRXFL1_t |
|
IRDA Receive Filter Length Bit 1
enum UCIRRXFL1_t {
UCIRRXFL1_OFF,
// Bit 1 OFF
UCIRRXFL1
// Bit 1 ON
};
enum IUSCI_A0_UART.UCIRRXFL2_t |
|
IRDA Receive Filter Length Bit 2
enum UCIRRXFL2_t {
UCIRRXFL2_OFF,
// Bit 2 OFF
UCIRRXFL2
// Bit 2 ON
};
enum IUSCI_A0_UART.UCIRRXFL3_t |
|
IRDA Receive Filter Length Bit 3
enum UCIRRXFL3_t {
UCIRRXFL3_OFF,
// Bit 3 OFF
UCIRRXFL3
// Bit 3 ON
};
enum IUSCI_A0_UART.UCIRRXFL4_t |
|
IRDA Receive Filter Length Bit 4
enum UCIRRXFL4_t {
UCIRRXFL4_OFF,
// Bit 4 OFF
UCIRRXFL4
// Bit 4 ON
};
enum IUSCI_A0_UART.UCIRRXFL5_t |
|
IRDA Receive Filter Length Bit 5
enum UCIRRXFL5_t {
UCIRRXFL5_OFF,
// Bit 5 OFF
UCIRRXFL5
// Bit 5 ON
};
enum IUSCI_A0_UART.UCIRRXPL_t |
|
IrDA receive input UCAxRXD polarity
enum UCIRRXPL_t {
UCIRRXPL_OFF,
// IrDA transceiver delivers a high pulse when a light pulse is seen
UCIRRXPL
// IrDA transceiver delivers a low pulse when a light pulse is seen
};
enum IUSCI_A0_UART.UCIRTXCLK_t |
|
IrDA transmit pulse clock select
enum UCIRTXCLK_t {
UCIRTXCLK_OFF,
// BRCLK
UCIRTXCLK
// BITCLK16 when UCOS16 = 1. Otherwise, BRCLK
};
enum IUSCI_A0_UART.UCIRTXPL0_t |
|
IRDA Transmit Pulse Length Bit 0
enum UCIRTXPL0_t {
UCIRTXPL0_OFF,
// Bit 0 OFF
UCIRTXPL0
// Bit 0 ON
};
enum IUSCI_A0_UART.UCIRTXPL1_t |
|
IRDA Transmit Pulse Length Bit 1
enum UCIRTXPL1_t {
UCIRTXPL1_OFF,
// Bit 1 OFF
UCIRTXPL1
// Bit 1 ON
};
enum IUSCI_A0_UART.UCIRTXPL2_t |
|
IRDA Transmit Pulse Length Bit 2
enum UCIRTXPL2_t {
UCIRTXPL2_OFF,
// Bit 2 OFF
UCIRTXPL2
// Bit 2 ON
};
enum IUSCI_A0_UART.UCIRTXPL3_t |
|
IRDA Transmit Pulse Length Bit 3
enum UCIRTXPL3_t {
UCIRTXPL3_OFF,
// Bit 3 OFF
UCIRTXPL3
// Bit 3 ON
};
enum IUSCI_A0_UART.UCIRTXPL4_t |
|
IRDA Transmit Pulse Length Bit 4
enum UCIRTXPL4_t {
UCIRTXPL4_OFF,
// Bit 4 OFF
UCIRTXPL4
// Bit 4 ON
};
enum IUSCI_A0_UART.UCIRTXPL5_t |
|
IRDA Transmit Pulse Length Bit 5
enum UCIRTXPL5_t {
UCIRTXPL5_OFF,
// Bit 5 OFF
UCIRTXPL5
// Bit 5 ON
};
enum IUSCI_A0_UART.UCLISTEN_t |
|
Listen enable. The UCLISTEN bit selects loopback mode
enum UCLISTEN_t {
UCLISTEN_OFF,
// Disabled
UCLISTEN
// Enabled. UCAxTXD is internally fed back to the receiver
};
enum IUSCI_A0_UART.UCMODE_ASYNC_t |
|
USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0
enum UCMODE_ASYNC_t {
UCMODE_0,
// UART Mode
UCMODE_1,
// Idle-Line Multiprocessor Mode
UCMODE_2,
// Address-Bit Multiprocessor Mode
UCMODE_3
// UART Mode with automatic baud rate detection
};
enum IUSCI_A0_UART.UCMODE_SYNC_t |
|
USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1
enum UCMODE_SYNC_t {
UCMODE_0,
// 3-Pin SPI
UCMODE_1,
// 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
UCMODE_2,
// 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
UCMODE_3
// I2C Mode
};
enum IUSCI_A0_UART.UCMSB_t |
|
MSB first select. Controls the direction of the receive and transmit shift register
enum UCMSB_t {
UCMSB_OFF,
// LSB first
UCMSB
// MSB first
};
enum IUSCI_A0_UART.UCOE_t |
|
Overrun error flag
enum UCOE_t {
UCOE_OFF,
// No error
UCOE
// Overrun error occurred
};
enum IUSCI_A0_UART.UCOS16_t |
|
Oversampling mode enabled
enum UCOS16_t {
UCOS16_OFF,
// Disabled
UCOS16
// Enabled
};
enum IUSCI_A0_UART.UCPAR_t |
|
Parity select. UCPAR is not used when parity is disabled
enum UCPAR_t {
UCPAR_OFF,
// Odd parity
UCPAR
// Even parity
};
enum IUSCI_A0_UART.UCPEN_t |
|
Parity enable
enum UCPEN_t {
UCPEN_OFF,
// Parity Disabled
UCPEN
// Parity Enabled
};
enum IUSCI_A0_UART.UCPE_t |
|
Parity error flag. When UCPEN = 0, UCPE is read as 0
enum UCPE_t {
UCPE_OFF,
// No error
UCPE
// Character received with parity error
};
enum IUSCI_A0_UART.UCRXEIE_t |
|
Receive erroneous-character interrupt-enable
enum UCRXEIE_t {
UCRXEIE_OFF,
// Erroneous characters rejected and UCAxRXIFG is not set
UCRXEIE
// Erroneous characters received will set UCAxRXIFG
};
enum IUSCI_A0_UART.UCRXERR_t |
|
Bit 2 Receive error flag. This bit indicates a character was received with error(s).
When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also
set. UCRXERR is cleared when UCAxRXBUF is read
enum UCRXERR_t {
UCRXERR_OFF,
// No receive errors detected
UCRXERR
// Receive error detected
};
enum IUSCI_A0_UART.UCSPB_t |
|
Stop bit select. Number of stop bits
enum UCSPB_t {
UCSPB_OFF,
// One stop bit
UCSPB
// Two stop bits
};
enum IUSCI_A0_UART.UCSSEL_UART_t |
|
USCI clock source select. These bits select the BRCLK source clock
enum UCSSEL_UART_t {
UCSSEL_0,
// UCLK
UCSSEL_1,
// ACLK
UCSSEL_2
// SMCLK
};
enum IUSCI_A0_UART.UCSTOE_t |
|
Synch field time out error
enum UCSTOE_t {
UCSTOE_OFF,
// No error
UCSTOE
// Length of synch field exceeded measurable time
};
enum IUSCI_A0_UART.UCSWRST_t |
|
Software reset enable
enum UCSWRST_t {
UCSWRST_OFF,
// Disabled. USCI reset released for operation
UCSWRST
// Enabled. USCI logic held in reset state
};
enum IUSCI_A0_UART.UCSYNC_t |
|
Synchronous mode enable
enum UCSYNC_t {
UCSYNC_OFF,
// Asynchronous mode
UCSYNC
// Synchronous Mode
};
enum IUSCI_A0_UART.UCTXADDR_t |
|
Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode
enum UCTXADDR_t {
UCTXADDR_OFF,
// Next frame transmitted is data
UCTXADDR
// Next frame transmitted is an address
};
enum IUSCI_A0_UART.UCTXBRK_t |
|
Transmit break. Transmits a break with the next write to the transmit buffer.
In UART mode with automatic baud rate detection 055h must be written
into UCAxTXBUF to generate the required break/synch fields. Otherwise
0h must be written into the transmit buffer
enum UCTXBRK_t {
UCTXBRK_OFF,
// Next frame transmitted is not a break
UCTXBRK
// Next frame transmitted is a break or a break/synch
};
typedef IUSCI_A0_UART.IPeripheralArray |
|
typedef IUSCI_A0_UART.StringArray |
|
typedef String StringArray[];
struct IUSCI_A0_UART.ForceSetDefaultRegister_t |
|
Force Set Default Register
metaonly struct ForceSetDefaultRegister_t {
String register;
Bool regForceSet;
};
DETAILS
Type to store if each register needs to be forced initialized
even if the register is in default state.
SEE
struct IUSCI_A0_UART.UCxABCTL_t |
|
metaonly struct UCxABCTL_t {
// Break/synch delimiter length
00 1 bit time
01 2 bit times
10 3 bit times
11 4 bit times
// Break/synch delimiter length
00 1 bit time
01 2 bit times
10 3 bit times
11 4 bit times
// Synch field time out error
0 No error
1 Length of synch field exceeded measurable time
// Break time out error
0 No error
1 Length of break field exceeded 22 bit times
// Automatic baud rate detect enable
0 Baud rate detection disabled. Length of break and synch field is not
measured.
1 Baud rate detection enabled. Length of break and synch field is
measured and baud rate settings are changed accordingly
};
struct IUSCI_A0_UART.UCxCTL0_t |
|
metaonly struct UCxCTL0_t {
// Parity enable
0 Parity disabled.
1 Parity enabled. Parity bit is generated (UCAxTXD) and expected
(UCAxRXD). In address-bit multiprocessor mode, the address bit is
included in the parity calculation
// Parity select. UCPAR is not used when parity is disabled.
0 Odd parity
1 Even parity
// MSB first select. Controls the direction of the receive and transmit shift
register.
0 LSB first
1 MSB first
// Character length. Selects 7-bit or 8-bit character length.
0 8-bit data
1 7-bit data
// Stop bit select. Number of stop bits.
0 One stop bit
1 Two stop bits
// USCI mode. The UCMODEx bits select the asynchronous mode when
UCSYNC = 0.
00 UART Mode.
01 Idle-Line Multiprocessor Mode.
10 Address-Bit Multiprocessor Mode.
11 UART Mode with automatic baud rate detection
// Synchronous mode enable
0 Asynchronous mode
1 Synchronous Mode
};
struct IUSCI_A0_UART.UCxCTL1_t |
|
metaonly struct UCxCTL1_t {
// USCI clock source select. These bits select the BRCLK source clock.
00 UCLK
01 ACLK
10 SMCLK
11 SMCLK
// Receive erroneous-character interrupt-enable
0 Erroneous characters rejected and UCAxRXIFG is not set
1 Erroneous characters received will set UCAxRXIFG
// Receive break character interrupt-enable
0 Received break characters do not set UCAxRXIFG.
1 Received break characters set UCAxRXIFG
// Dormant. Puts USCI into sleep mode.
0 Not dormant. All received characters will set UCAxRXIFG.
1 Dormant. Only characters that are preceded by an idle-line or with
address bit set will set UCAxRXIFG. In UART mode with automatic baud
rate detection only the combination of a break and synch field will set
UCAxRXIFG
// Transmit address. Next frame to be transmitted will be marked as address
depending on the selected multiprocessor mode.
0 Next frame transmitted is data
1 Next frame transmitted is an address
// Transmit break. Transmits a break with the next write to the transmit buffer.
In UART mode with automatic baud rate detection 055h must be written
into UCAxTXBUF to generate the required break/synch fields. Otherwise
0h must be written into the transmit buffer.
0 Next frame transmitted is not a break
1 Next frame transmitted is a break or a break/synch
// Software reset enable
0 Disabled. USCI reset released for operation.
1 Enabled. USCI logic held in reset state
};
struct IUSCI_A0_UART.UCxIRRCTL_t |
|
metaonly struct UCxIRRCTL_t {
// IRDA Receive Filter Length Bit 5
// IRDA Receive Filter Length Bit 4
// IRDA Receive Filter Length Bit 3
// IRDA Receive Filter Length Bit 2
// IRDA Receive Filter Length Bit 1
// IRDA Receive Filter Length Bit 0
// IrDA receive input UCAxRXD polarity
0 IrDA transceiver delivers a high pulse when a light pulse is seen
1 IrDA transceiver delivers a low pulse when a light pulse is seen
// IrDA receive filter enabled
0 Receive filter disabled
1 Receive filter enabled
};
struct IUSCI_A0_UART.UCxIRTCTL_t |
|
metaonly struct UCxIRTCTL_t {
// IRDA Transmit Pulse Length Bit 5
// IRDA Transmit Pulse Length Bit 4
// IRDA Transmit Pulse Length Bit 3
// IRDA Transmit Pulse Length Bit 2
// IRDA Transmit Pulse Length Bit 1
// IRDA Transmit Pulse Length Bit 0
// IrDA transmit pulse clock select
0 BRCLK
1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK
// IrDA encoder/decoder enable.
0 IrDA encoder/decoder disabled
1 IrDA encoder/decoder enabled
};
struct IUSCI_A0_UART.UCxMCTL_t |
|
metaonly struct UCxMCTL_t {
// First modulation stage select. These bits determine the modulation pattern
for BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0
// Second modulation stage select. These bits determine the modulation
pattern for BITCLK
// Oversampling mode enabled
0 Disabled
1 Enabled
};
struct IUSCI_A0_UART.UCxSTAT_t |
|
metaonly struct UCxSTAT_t {
// Listen enable. The UCLISTEN bit selects loopback mode.
0 Disabled
1 Enabled. UCAxTXD is internally fed back to the receiver
// Framing error flag
0 No error
1 Character received with low stop bit
// Overrun error flag. This bit is set when a character is transferred into
UCAxRXBUF before the previous character was read. UCOE is cleared
automatically when UCxRXBUF is read, and must not be cleared by
software. Otherwise, it will not function correctly.
0 No error
1 Overrun error occurred
// Parity error flag. When UCPEN = 0, UCPE is read as 0.
0 No error
1 Character received with parity error
// Break detect flag
0 No break condition
1 Break condition occurred
// Receive error flag. This bit indicates a character was received with error(s).
When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also
set. UCRXERR is cleared when UCAxRXBUF is read.
0 No receive errors detected
1 Receive error detected
// Address received in address-bit multiprocessor mode.
0 Received character is data
1 Received character is an address
// Idle line detected in idle-line multiprocessor mode.
0 No idle line detected
1 Idle line detected
// USCI busy. This bit indicates if a transmit or receive operation is in
progress.
0 USCI inactive
1 USCI transmitting or receiving
};
IUSCI_A0_UART.addPeripheralsMap() // module-wide |
|
Create a map of all peripherals available on a device
ARGUMENTS
DETAILS
The config parameter
peripherals is by default undefined in an
xdc.platform.ICpuDataSheet instance. This function gathers
all instance configuration parameters that are of the type
xdc.platform.IPeripheral into the map
peripherals.
IUSCI_A0_UART.getAll() // module-wide |
|
Find all peripherals of a certain type
DETAILS
The type of the peripherals returned is defined by the type of the
caller.
RETURNS
Returns an array of IPeripheral instances
IUSCI_A0_UART.getRegisters() // module-wide |
|
Find all registers defined by the peripheral
RETURNS
Returns an array of register names
config IUSCI_A0_UART.UCA0ABCTL // instance |
|
Auto Baud Rate Control Register
config IUSCI_A0_UART.UCA0BR0 // instance |
|
Baud rate control register 0
config UChar UCA0BR0 = 0;
config IUSCI_A0_UART.UCA0BR1 // instance |
|
Baud rate control register 1
config UChar UCA0BR1 = 0;
config IUSCI_A0_UART.UCA0CTL0 // instance |
|
Control Register 0
config IUSCI_A0_UART.UCA0CTL1 // instance |
|
Control Register 1
config IUSCI_A0_UART.UCA0IRRCTL // instance |
|
IrDA Receive Control Register
config IUSCI_A0_UART.UCA0IRTCTL // instance |
|
IrDA Transmit Control Register
config IUSCI_A0_UART.UCA0MCTL // instance |
|
Modulation Control Register
config IUSCI_A0_UART.UCA0RXBUF // instance |
|
Receive Buffer Register
config UChar UCA0RXBUF = 0;
config IUSCI_A0_UART.UCA0STAT // instance |
|
Status Register
config IUSCI_A0_UART.UCA0TXBUF // instance |
|
Transmit Buffer Register
config UChar UCA0TXBUF = 0;
config IUSCI_A0_UART.UCLKHz // instance |
|
Stores the UCLK external clock frequency in float
config Float UCLKHz = 1000000;
config IUSCI_A0_UART.name // instance |
|
Specific peripheral name given by the device
DETAILS
Devices can have more than one peripheral of the same type. In such
cases, device data sheets give different names to the instances of a
same peripheral. For example, the name for a timer module could be
TimerA3, and a device that has two such timers can name them TA0
and TA1.
config IUSCI_A0_UART.owner // instance |
|
String specifying the entity that manages the peripheral
IUSCI_A0_UART.getUCRXIE() // instance |
|
IUSCI_A0_UART.getUCTXIE() // instance |
|
IUSCI_A0_UART.setUCRXIE() // instance |
|
Bool setUCRXIE(Bool set);
IUSCI_A0_UART.setUCTXIE() // instance |
|
Bool setUCTXIE(Bool set);