metaonly interface ti.catalog.msp430.peripherals.communication.IUSCI_A1_UART
index URL

Universal Serial Communication Interface A0 UART 2xx

XDCspec summary sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
metaonly interface IUSCI_A1_UART {  ...
// inherits ti.catalog.msp430.peripherals.communication.IUSCI_UART
    // inherits ti.catalog.msp430.peripherals.communication.IUSCI
        // inherits xdc.platform.IPeripheral
instance:  ...
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
package ti.catalog.msp430.peripherals.communication;
 
metaonly interface IUSCI_A1_UART inherits IUSCI_UART {
module-wide constants & types
    enum UC7BIT_t// Character length. Selects 7-bit or 8-bit character length {
        UC7BIT_OFF// 8-bit,
        UC7BIT// 7-bit
    };
    enum UCABDEN_t// Automatic baud rate detect enable {
        UCABDEN_OFF// Baud rate detection disabled. Length of break and synch field is not measured,
        UCABDEN// Baud rate detection enabled. Length of break and synch field is measured and baud rate settings are changed accordingly
    };
    enum UCADDR_t// Address received in address-bit multiprocessor mode {
        UCADDR_OFF// Received character is data,
        UCADDR// Received character is an address
    };
    enum UCBRF_t// First modulation stage select {
        UCBRF_0// First stage 0,
        UCBRF_1// First stage 1,
        UCBRF_2// First stage 2,
        UCBRF_3// First stage 3,
        UCBRF_4// First stage 4,
        UCBRF_5// First stage 5,
        UCBRF_6// First stage 6,
        UCBRF_7// First stage 7,
        UCBRF_8// First stage 8,
        UCBRF_9// First stage 9,
        UCBRF_10// First stage 10,
        UCBRF_11// First stage 11,
        UCBRF_12// First stage 12,
        UCBRF_13// First stage 13,
        UCBRF_14// First stage 14,
        UCBRF_15// First stage 15
    };
    enum UCBRKIE_t// Receive break character interrupt-enable {
        UCBRKIE_OFF// Received break characters do not set UCAxRXIFG,
        UCBRKIE// Received break characters set UCAxRXIFG
    };
    enum UCBRK_t// Break detect flag {
        UCBRK_OFF// No break condition,
        UCBRK// Break condition occurred
    };
    enum UCBRS_t// Second modulation stage select {
        UCBRS_0// Second stage 0,
        UCBRS_1// Second stage 1,
        UCBRS_2// Second stage 2,
        UCBRS_3// Second stage 3,
        UCBRS_4// Second stage 4,
        UCBRS_5// Second stage 5,
        UCBRS_6// Second stage 6,
        UCBRS_7// Second stage 7
    };
    enum UCBTOE_t// Break time out error {
        UCBTOE_OFF// No error,
        UCBTOE// Length of break field exceeded 22 bit times
    };
    enum UCBUSY_t// USCI busy. This bit indicates if a transmit or receive operation is in progress {
        UCBUSY_OFF// USCI inactive,
        UCBUSY// USCI transmitting or receiving
    };
    enum UCDELIM0_t// Break/synch delimiter length bit 0 {
        UCDELIM0_OFF// Break Sync Delimiter bit 0 Off,
        UCDELIM0// Break Sync Delimiter bit 0 On
    };
    enum UCDELIM1_t// Break/synch delimiter length bit 1 {
        UCDELIM1_OFF// Break Sync Delimiter bit 1 Off,
        UCDELIM1// Break Sync Delimiter bit 1 On
    };
    enum UCDORM_t// Dormant. Puts USCI into sleep mode {
        UCDORM_OFF// Not dormant. All received characters will set UCAxRXIFG,
        UCDORM// Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG
    };
    enum UCFE_t// Framing error flag {
        UCFE_OFF// 0 No error,
        UCFE// Character received with low stop bit
    };
    enum UCIDLE_t// Idle line detected in idle-line multiprocessor mode {
        UCIDLE_OFF// No idle line detected,
        UCIDLE// Idle line detected
    };
    enum UCIREN_t// IrDA encoder/decoder enable {
        UCIREN_OFF// IrDA encoder/decoder disabled,
        UCIREN// IrDA encoder/decoder enabled
    };
    enum UCIRRXFE_t// IrDA receive filter enabled {
        UCIRRXFE_OFF// Receive filter disabled,
        UCIRRXFE// Receive filter enabled
    };
    enum UCIRRXFL0_t// IRDA Receive Filter Length Bit 0 {
        UCIRRXFL0_OFF// Bit 0 OFF,
        UCIRRXFL0// Bit 0 ON
    };
    enum UCIRRXFL1_t// IRDA Receive Filter Length Bit 1 {
        UCIRRXFL1_OFF// Bit 1 OFF,
        UCIRRXFL1// Bit 1 ON
    };
    enum UCIRRXFL2_t// IRDA Receive Filter Length Bit 2 {
        UCIRRXFL2_OFF// Bit 2 OFF,
        UCIRRXFL2// Bit 2 ON
    };
    enum UCIRRXFL3_t// IRDA Receive Filter Length Bit 3 {
        UCIRRXFL3_OFF// Bit 3 OFF,
        UCIRRXFL3// Bit 3 ON
    };
    enum UCIRRXFL4_t// IRDA Receive Filter Length Bit 4 {
        UCIRRXFL4_OFF// Bit 4 OFF,
        UCIRRXFL4// Bit 4 ON
    };
    enum UCIRRXFL5_t// IRDA Receive Filter Length Bit 5 {
        UCIRRXFL5_OFF// Bit 5 OFF,
        UCIRRXFL5// Bit 5 ON
    };
    enum UCIRRXPL_t// IrDA receive input UCAxRXD polarity {
        UCIRRXPL_OFF// IrDA transceiver delivers a high pulse when a light pulse is seen,
        UCIRRXPL// IrDA transceiver delivers a low pulse when a light pulse is seen
    };
    enum UCIRTXCLK_t// IrDA transmit pulse clock select {
        UCIRTXCLK_OFF// BRCLK,
        UCIRTXCLK// BITCLK16 when UCOS16 = 1. Otherwise, BRCLK
    };
    enum UCIRTXPL0_t// IRDA Transmit Pulse Length Bit 0 {
        UCIRTXPL0_OFF// Bit 0 OFF,
        UCIRTXPL0// Bit 0 ON
    };
    enum UCIRTXPL1_t// IRDA Transmit Pulse Length Bit 1 {
        UCIRTXPL1_OFF// Bit 1 OFF,
        UCIRTXPL1// Bit 1 ON
    };
    enum UCIRTXPL2_t// IRDA Transmit Pulse Length Bit 2 {
        UCIRTXPL2_OFF// Bit 2 OFF,
        UCIRTXPL2// Bit 2 ON
    };
    enum UCIRTXPL3_t// IRDA Transmit Pulse Length Bit 3 {
        UCIRTXPL3_OFF// Bit 3 OFF,
        UCIRTXPL3// Bit 3 ON
    };
    enum UCIRTXPL4_t// IRDA Transmit Pulse Length Bit 4 {
        UCIRTXPL4_OFF// Bit 4 OFF,
        UCIRTXPL4// Bit 4 ON
    };
    enum UCIRTXPL5_t// IRDA Transmit Pulse Length Bit 5 {
        UCIRTXPL5_OFF// Bit 5 OFF,
        UCIRTXPL5// Bit 5 ON
    };
    enum UCLISTEN_t// Listen enable. The UCLISTEN bit selects loopback mode {
        UCLISTEN_OFF// Disabled,
        UCLISTEN// Enabled. UCAxTXD is internally fed back to the receiver
    };
    enum UCMODE_ASYNC_t// USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0 {
        UCMODE_0// UART Mode,
        UCMODE_1// Idle-Line Multiprocessor Mode,
        UCMODE_2// Address-Bit Multiprocessor Mode,
        UCMODE_3// UART Mode with automatic baud rate detection
    };
    enum UCMODE_SYNC_t// USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1 {
        UCMODE_0// 3-Pin SPI,
        UCMODE_1// 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1,
        UCMODE_2// 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0,
        UCMODE_3// I2C Mode
    };
    enum UCMSB_t// MSB first select. Controls the direction of the receive and transmit shift register {
        UCMSB_OFF// LSB first,
        UCMSB// MSB first
    };
    enum UCOE_t// Overrun error flag {
        UCOE_OFF// No error,
        UCOE// Overrun error occurred
    };
    enum UCOS16_t// Oversampling mode enabled {
        UCOS16_OFF// Disabled,
        UCOS16// Enabled
    };
    enum UCPAR_t// Parity select. UCPAR is not used when parity is disabled {
        UCPAR_OFF// Odd parity,
        UCPAR// Even parity
    };
    enum UCPEN_t// Parity enable {
        UCPEN_OFF// Parity Disabled,
        UCPEN// Parity Enabled
    };
    enum UCPE_t// Parity error flag. When UCPEN = 0, UCPE is read as 0 {
        UCPE_OFF// No error,
        UCPE// Character received with parity error
    };
    enum UCRXEIE_t// Receive erroneous-character interrupt-enable {
        UCRXEIE_OFF// Erroneous characters rejected and UCAxRXIFG is not set,
        UCRXEIE// Erroneous characters received will set UCAxRXIFG
    };
    enum UCRXERR_t// Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read {
        UCRXERR_OFF// No receive errors detected,
        UCRXERR// Receive error detected
    };
    enum UCSPB_t// Stop bit select. Number of stop bits {
        UCSPB_OFF// One stop bit,
        UCSPB// Two stop bits
    };
    enum UCSSEL_UART_t// USCI clock source select. These bits select the BRCLK source clock {
        UCSSEL_0// UCLK,
        UCSSEL_1// ACLK,
        UCSSEL_2// SMCLK
    };
    enum UCSTOE_t// Synch field time out error {
        UCSTOE_OFF// No error,
        UCSTOE// Length of synch field exceeded measurable time
    };
    enum UCSWRST_t// Software reset enable {
        UCSWRST_OFF// Disabled. USCI reset released for operation,
        UCSWRST// Enabled. USCI logic held in reset state
    };
    enum UCSYNC_t// Synchronous mode enable {
        UCSYNC_OFF// Asynchronous mode,
        UCSYNC// Synchronous Mode
    };
    enum UCTXADDR_t// Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode {
        UCTXADDR_OFF// Next frame transmitted is data,
        UCTXADDR// Next frame transmitted is an address
    };
    enum UCTXBRK_t// Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer {
        UCTXBRK_OFF// Next frame transmitted is not a break,
        UCTXBRK// Next frame transmitted is a break or a break/synch
    };
    typedef IPeripheral.Instance IPeripheralArray// [];
    typedef String StringArray// [];
    metaonly struct ForceSetDefaultRegister_t// Force Set Default Register {
        String register;
        Bool regForceSet;
    };
    metaonly struct UCxABCTL_t//  {
        IUSCI_UART.UCDELIM1_t UCDELIM1// Break/synch delimiter length 00 1 bit time 01 2 bit times 10 3 bit times 11 4 bit times;
        IUSCI_UART.UCDELIM0_t UCDELIM0// Break/synch delimiter length 00 1 bit time 01 2 bit times 10 3 bit times 11 4 bit times;
        IUSCI_UART.UCSTOE_t UCSTOE// Synch field time out error 0 No error 1 Length of synch field exceeded measurable time;
        IUSCI_UART.UCBTOE_t UCBTOE// Break time out error 0 No error 1 Length of break field exceeded 22 bit times;
        IUSCI_UART.UCABDEN_t UCABDEN// Automatic baud rate detect enable 0 Baud rate detection disabled. Length of break and synch field is not measured. 1 Baud rate detection enabled. Length of break and synch field is measured and baud rate settings are changed accordingly;
    };
    metaonly struct UCxCTL0_t//  {
        IUSCI_UART.UCPEN_t UCPEN// Parity enable 0 Parity disabled. 1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation;
        IUSCI_UART.UCPAR_t UCPAR// Parity select. UCPAR is not used when parity is disabled. 0 Odd parity 1 Even parity;
        IUSCI_UART.UCMSB_t UCMSB// MSB first select. Controls the direction of the receive and transmit shift register. 0 LSB first 1 MSB first;
        IUSCI_UART.UC7BIT_t UC7BIT// Character length. Selects 7-bit or 8-bit character length. 0 8-bit data 1 7-bit data;
        IUSCI_UART.UCSPB_t UCSPB// Stop bit select. Number of stop bits. 0 One stop bit 1 Two stop bits;
        IUSCI_UART.UCMODE_ASYNC_t UCMODE// USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0. 00 UART Mode. 01 Idle-Line Multiprocessor Mode. 10 Address-Bit Multiprocessor Mode. 11 UART Mode with automatic baud rate detection;
        IUSCI_UART.UCSYNC_t UCSYNC// Synchronous mode enable 0 Asynchronous mode 1 Synchronous Mode;
    };
    metaonly struct UCxCTL1_t//  {
        IUSCI_UART.UCSSEL_UART_t UCSSEL// USCI clock source select. These bits select the BRCLK source clock. 00 UCLK 01 ACLK 10 SMCLK 11 SMCLK;
        IUSCI_UART.UCRXEIE_t UCRXEIE// Receive erroneous-character interrupt-enable 0 Erroneous characters rejected and UCAxRXIFG is not set 1 Erroneous characters received will set UCAxRXIFG;
        IUSCI_UART.UCBRKIE_t UCBRKIE// Receive break character interrupt-enable 0 Received break characters do not set UCAxRXIFG. 1 Received break characters set UCAxRXIFG;
        IUSCI_UART.UCDORM_t UCDORM// Dormant. Puts USCI into sleep mode. 0 Not dormant. All received characters will set UCAxRXIFG. 1 Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG;
        IUSCI_UART.UCTXADDR_t UCTXADDR// Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode. 0 Next frame transmitted is data 1 Next frame transmitted is an address;
        IUSCI_UART.UCTXBRK_t UCTXBRK// Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer. 0 Next frame transmitted is not a break 1 Next frame transmitted is a break or a break/synch;
        IUSCI_UART.UCSWRST_t UCSWRST// Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state;
    };
    metaonly struct UCxIRRCTL_t//  {
        IUSCI_UART.UCIRRXFL5_t UCIRRXFL5// IRDA Receive Filter Length Bit 5;
        IUSCI_UART.UCIRRXFL4_t UCIRRXFL4// IRDA Receive Filter Length Bit 4;
        IUSCI_UART.UCIRRXFL3_t UCIRRXFL3// IRDA Receive Filter Length Bit 3;
        IUSCI_UART.UCIRRXFL2_t UCIRRXFL2// IRDA Receive Filter Length Bit 2;
        IUSCI_UART.UCIRRXFL1_t UCIRRXFL1// IRDA Receive Filter Length Bit 1;
        IUSCI_UART.UCIRRXFL0_t UCIRRXFL0// IRDA Receive Filter Length Bit 0;
        IUSCI_UART.UCIRRXPL_t UCIRRXPL// IrDA receive input UCAxRXD polarity 0 IrDA transceiver delivers a high pulse when a light pulse is seen 1 IrDA transceiver delivers a low pulse when a light pulse is seen;
        IUSCI_UART.UCIRRXFE_t UCIRRXFE// IrDA receive filter enabled 0 Receive filter disabled 1 Receive filter enabled;
    };
    metaonly struct UCxIRTCTL_t//  {
        IUSCI_UART.UCIRTXPL5_t UCIRTXPL5// IRDA Transmit Pulse Length Bit 5;
        IUSCI_UART.UCIRTXPL4_t UCIRTXPL4// IRDA Transmit Pulse Length Bit 4;
        IUSCI_UART.UCIRTXPL3_t UCIRTXPL3// IRDA Transmit Pulse Length Bit 3;
        IUSCI_UART.UCIRTXPL2_t UCIRTXPL2// IRDA Transmit Pulse Length Bit 2;
        IUSCI_UART.UCIRTXPL1_t UCIRTXPL1// IRDA Transmit Pulse Length Bit 1;
        IUSCI_UART.UCIRTXPL0_t UCIRTXPL0// IRDA Transmit Pulse Length Bit 0;
        IUSCI_UART.UCIRTXCLK_t UCIRTXCLK// IrDA transmit pulse clock select 0 BRCLK 1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK;
        IUSCI_UART.UCIREN_t UCIREN// IrDA encoder/decoder enable. 0 IrDA encoder/decoder disabled 1 IrDA encoder/decoder enabled;
    };
    metaonly struct UCxMCTL_t//  {
        IUSCI_UART.UCBRF_t UCBRF// First modulation stage select. These bits determine the modulation pattern for BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0;
        IUSCI_UART.UCBRS_t UCBRS// Second modulation stage select. These bits determine the modulation pattern for BITCLK;
        IUSCI_UART.UCOS16_t UCOS16// Oversampling mode enabled 0 Disabled 1 Enabled;
    };
    metaonly struct UCxSTAT_t//  {
        IUSCI_UART.UCLISTEN_t UCLISTEN// Listen enable. The UCLISTEN bit selects loopback mode. 0 Disabled 1 Enabled. UCAxTXD is internally fed back to the receiver;
        IUSCI_UART.UCFE_t UCFE// Framing error flag 0 No error 1 Character received with low stop bit;
        IUSCI_UART.UCOE_t UCOE// Overrun error flag. This bit is set when a character is transferred into UCAxRXBUF before the previous character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by software. Otherwise, it will not function correctly. 0 No error 1 Overrun error occurred;
        IUSCI_UART.UCPE_t UCPE// Parity error flag. When UCPEN = 0, UCPE is read as 0. 0 No error 1 Character received with parity error;
        IUSCI_UART.UCBRK_t UCBRK// Break detect flag 0 No break condition 1 Break condition occurred;
        IUSCI_UART.UCRXERR_t UCRXERR// Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read. 0 No receive errors detected 1 Receive error detected;
        IUSCI_UART.UCADDR_t UCADDR// Address received in address-bit multiprocessor mode. 0 Received character is data 1 Received character is an address;
        IUSCI_UART.UCIDLE_t UCIDLE// Idle line detected in idle-line multiprocessor mode. 0 No idle line detected 1 Idle line detected;
        IUSCI_UART.UCBUSY_t UCBUSY// USCI busy. This bit indicates if a transmit or receive operation is in progress. 0 USCI inactive 1 USCI transmitting or receiving;
    };
module-wide functions
    Void addPeripheralsMap// Create a map of all peripherals available on a device(ICpuDataSheet.Instance cds);
    IPeripheral.IPeripheralArray getAll// Find all peripherals of a certain type();
    IPeripheral.StringArray getRegisters// Find all registers defined by the peripheral();
 
instance:
per-instance config parameters
    config IUSCI_A1_UART.UCxABCTL_t UCA1ABCTL// Auto Baud Rate Control Register = {
        UCDELIM1: IUSCI_UART.UCDELIM1_OFF,
        UCDELIM0: IUSCI_UART.UCDELIM0_OFF,
        UCSTOE: IUSCI_UART.UCSTOE_OFF,
        UCBTOE: IUSCI_UART.UCBTOE_OFF,
        UCABDEN: IUSCI_UART.UCABDEN_OFF
    };
    config UChar UCA1BR0// Baud rate control register 0 = 0;
    config UChar UCA1BR1// Baud rate control register 1 = 0;
    config IUSCI_A1_UART.UCxCTL0_t UCA1CTL0// Control Register 0 = {
        UCPEN: IUSCI_UART.UCPEN_OFF,
        UCPAR: IUSCI_UART.UCPAR_OFF,
        UCMSB: IUSCI.UCMSB_OFF,
        UC7BIT: IUSCI.UC7BIT_OFF,
        UCSPB: IUSCI_UART.UCSPB_OFF,
        UCMODE: IUSCI_UART.UCMODE_0,
        UCSYNC: IUSCI.UCSYNC_OFF
    };
    config IUSCI_A1_UART.UCxCTL1_t UCA1CTL1// Control Register 1 = {
        UCSSEL: IUSCI_UART.UCSSEL_0,
        UCRXEIE: IUSCI.UCRXEIE_OFF,
        UCBRKIE: IUSCI.UCBRKIE_OFF,
        UCDORM: IUSCI.UCDORM_OFF,
        UCTXADDR: IUSCI.UCTXADDR_OFF,
        UCTXBRK: IUSCI.UCTXBRK_OFF,
        UCSWRST: IUSCI.UCSWRST
    };
    config IUSCI_A1_UART.UCxIRRCTL_t UCA1IRRCTL// IrDA Receive Control Register = {
        UCIRRXFL5: IUSCI_UART.UCIRRXFL5_OFF,
        UCIRRXFL4: IUSCI_UART.UCIRRXFL4_OFF,
        UCIRRXFL3: IUSCI_UART.UCIRRXFL3_OFF,
        UCIRRXFL2: IUSCI_UART.UCIRRXFL2_OFF,
        UCIRRXFL1: IUSCI_UART.UCIRRXFL1_OFF,
        UCIRRXFL0: IUSCI_UART.UCIRRXFL0_OFF,
        UCIRRXPL: IUSCI_UART.UCIRRXPL_OFF,
        UCIRRXFE: IUSCI_UART.UCIRRXFE_OFF
    };
    config IUSCI_A1_UART.UCxIRTCTL_t UCA1IRTCTL// IrDA Transmit Control Register = {
        UCIRTXPL5: IUSCI_UART.UCIRTXPL5_OFF,
        UCIRTXPL4: IUSCI_UART.UCIRTXPL4_OFF,
        UCIRTXPL3: IUSCI_UART.UCIRTXPL3_OFF,
        UCIRTXPL2: IUSCI_UART.UCIRTXPL2_OFF,
        UCIRTXPL1: IUSCI_UART.UCIRTXPL1_OFF,
        UCIRTXPL0: IUSCI_UART.UCIRTXPL0_OFF,
        UCIRTXCLK: IUSCI_UART.UCIRTXCLK_OFF,
        UCIREN: IUSCI_UART.UCIREN_OFF
    };
    config IUSCI_A1_UART.UCxMCTL_t UCA1MCTL// Modulation Control Register = {
        UCBRF: IUSCI_UART.UCBRF_0,
        UCBRS: IUSCI_UART.UCBRS_0,
        UCOS16: IUSCI_UART.UCOS16_OFF
    };
    config UChar UCA1RXBUF// Receive Buffer Register = 0;
    config IUSCI_A1_UART.UCxSTAT_t UCA1STAT// Status Register = {
        UCLISTEN: IUSCI.UCLISTEN_OFF,
        UCFE: IUSCI.UCFE_OFF,
        UCOE: IUSCI.UCOE_OFF,
        UCPE: IUSCI.UCPE_OFF,
        UCBRK: IUSCI.UCBRK_OFF,
        UCRXERR: IUSCI.UCRXERR_OFF,
        UCADDR: IUSCI.UCADDR_OFF,
        UCIDLE: IUSCI.UCIDLE_OFF,
        UCBUSY: IUSCI.UCBUSY
    };
    config UChar UCA1TXBUF// Transmit Buffer Register = 0;
    config Float UCLKHz// Stores the UCLK external clock frequency in float = 1000000;
    config String name// Specific peripheral name given by the device;
    config String owner// String specifying the entity that manages the peripheral;
per-instance functions
    Bool getUCRXIE// ();
    Bool getUCTXIE// ();
    Bool setUCRXIE// (Bool set);
    Bool setUCTXIE// (Bool set);
}
enum IUSCI_A1_UART.UC7BIT_t
index URL

Character length. Selects 7-bit or 8-bit character length

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UC7BIT_t {
    UC7BIT_OFF,
    // 8-bit
    UC7BIT
    // 7-bit
};
enum IUSCI_A1_UART.UCABDEN_t
index URL

Automatic baud rate detect enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCABDEN_t {
    UCABDEN_OFF,
    // Baud rate detection disabled. Length of break and synch field is not measured
    UCABDEN
    // Baud rate detection enabled. Length of break and synch field is measured and baud rate settings are changed accordingly
};
enum IUSCI_A1_UART.UCADDR_t
index URL

Address received in address-bit multiprocessor mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCADDR_t {
    UCADDR_OFF,
    // Received character is data
    UCADDR
    // Received character is an address
};
enum IUSCI_A1_UART.UCBRF_t
index URL

First modulation stage select

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCBRF_t {
    UCBRF_0,
    // First stage 0
    UCBRF_1,
    // First stage 1
    UCBRF_2,
    // First stage 2
    UCBRF_3,
    // First stage 3
    UCBRF_4,
    // First stage 4
    UCBRF_5,
    // First stage 5
    UCBRF_6,
    // First stage 6
    UCBRF_7,
    // First stage 7
    UCBRF_8,
    // First stage 8
    UCBRF_9,
    // First stage 9
    UCBRF_10,
    // First stage 10
    UCBRF_11,
    // First stage 11
    UCBRF_12,
    // First stage 12
    UCBRF_13,
    // First stage 13
    UCBRF_14,
    // First stage 14
    UCBRF_15
    // First stage 15
};
enum IUSCI_A1_UART.UCBRKIE_t
index URL

Receive break character interrupt-enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCBRKIE_t {
    UCBRKIE_OFF,
    // Received break characters do not set UCAxRXIFG
    UCBRKIE
    // Received break characters set UCAxRXIFG
};
enum IUSCI_A1_UART.UCBRK_t
index URL

Break detect flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCBRK_t {
    UCBRK_OFF,
    // No break condition
    UCBRK
    // Break condition occurred
};
enum IUSCI_A1_UART.UCBRS_t
index URL

Second modulation stage select

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCBRS_t {
    UCBRS_0,
    // Second stage 0
    UCBRS_1,
    // Second stage 1
    UCBRS_2,
    // Second stage 2
    UCBRS_3,
    // Second stage 3
    UCBRS_4,
    // Second stage 4
    UCBRS_5,
    // Second stage 5
    UCBRS_6,
    // Second stage 6
    UCBRS_7
    // Second stage 7
};
enum IUSCI_A1_UART.UCBTOE_t
index URL

Break time out error

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCBTOE_t {
    UCBTOE_OFF,
    // No error
    UCBTOE
    // Length of break field exceeded 22 bit times
};
enum IUSCI_A1_UART.UCBUSY_t
index URL

USCI busy. This bit indicates if a transmit or receive operation is in progress

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCBUSY_t {
    UCBUSY_OFF,
    // USCI inactive
    UCBUSY
    // USCI transmitting or receiving
};
enum IUSCI_A1_UART.UCDELIM0_t
index URL

Break/synch delimiter length bit 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCDELIM0_t {
    UCDELIM0_OFF,
    // Break Sync Delimiter bit 0 Off
    UCDELIM0
    // Break Sync Delimiter bit 0 On
};
enum IUSCI_A1_UART.UCDELIM1_t
index URL

Break/synch delimiter length bit 1

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCDELIM1_t {
    UCDELIM1_OFF,
    // Break Sync Delimiter bit 1 Off
    UCDELIM1
    // Break Sync Delimiter bit 1 On
};
enum IUSCI_A1_UART.UCDORM_t
index URL

Dormant. Puts USCI into sleep mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCDORM_t {
    UCDORM_OFF,
    // Not dormant. All received characters will set UCAxRXIFG
    UCDORM
    // Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG
};
enum IUSCI_A1_UART.UCFE_t
index URL

Framing error flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCFE_t {
    UCFE_OFF,
    // 0 No error
    UCFE
    // Character received with low stop bit
};
enum IUSCI_A1_UART.UCIDLE_t
index URL

Idle line detected in idle-line multiprocessor mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIDLE_t {
    UCIDLE_OFF,
    // No idle line detected
    UCIDLE
    // Idle line detected
};
enum IUSCI_A1_UART.UCIREN_t
index URL

IrDA encoder/decoder enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIREN_t {
    UCIREN_OFF,
    // IrDA encoder/decoder disabled
    UCIREN
    // IrDA encoder/decoder enabled
};
enum IUSCI_A1_UART.UCIRRXFE_t
index URL

IrDA receive filter enabled

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRRXFE_t {
    UCIRRXFE_OFF,
    // Receive filter disabled
    UCIRRXFE
    // Receive filter enabled
};
enum IUSCI_A1_UART.UCIRRXFL0_t
index URL

IRDA Receive Filter Length Bit 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRRXFL0_t {
    UCIRRXFL0_OFF,
    // Bit 0 OFF
    UCIRRXFL0
    // Bit 0 ON
};
enum IUSCI_A1_UART.UCIRRXFL1_t
index URL

IRDA Receive Filter Length Bit 1

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRRXFL1_t {
    UCIRRXFL1_OFF,
    // Bit 1 OFF
    UCIRRXFL1
    // Bit 1 ON
};
enum IUSCI_A1_UART.UCIRRXFL2_t
index URL

IRDA Receive Filter Length Bit 2

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRRXFL2_t {
    UCIRRXFL2_OFF,
    // Bit 2 OFF
    UCIRRXFL2
    // Bit 2 ON
};
enum IUSCI_A1_UART.UCIRRXFL3_t
index URL

IRDA Receive Filter Length Bit 3

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRRXFL3_t {
    UCIRRXFL3_OFF,
    // Bit 3 OFF
    UCIRRXFL3
    // Bit 3 ON
};
enum IUSCI_A1_UART.UCIRRXFL4_t
index URL

IRDA Receive Filter Length Bit 4

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRRXFL4_t {
    UCIRRXFL4_OFF,
    // Bit 4 OFF
    UCIRRXFL4
    // Bit 4 ON
};
enum IUSCI_A1_UART.UCIRRXFL5_t
index URL

IRDA Receive Filter Length Bit 5

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRRXFL5_t {
    UCIRRXFL5_OFF,
    // Bit 5 OFF
    UCIRRXFL5
    // Bit 5 ON
};
enum IUSCI_A1_UART.UCIRRXPL_t
index URL

IrDA receive input UCAxRXD polarity

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRRXPL_t {
    UCIRRXPL_OFF,
    // IrDA transceiver delivers a high pulse when a light pulse is seen
    UCIRRXPL
    // IrDA transceiver delivers a low pulse when a light pulse is seen
};
enum IUSCI_A1_UART.UCIRTXCLK_t
index URL

IrDA transmit pulse clock select

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRTXCLK_t {
    UCIRTXCLK_OFF,
    // BRCLK
    UCIRTXCLK
    // BITCLK16 when UCOS16 = 1. Otherwise, BRCLK
};
enum IUSCI_A1_UART.UCIRTXPL0_t
index URL

IRDA Transmit Pulse Length Bit 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRTXPL0_t {
    UCIRTXPL0_OFF,
    // Bit 0 OFF
    UCIRTXPL0
    // Bit 0 ON
};
enum IUSCI_A1_UART.UCIRTXPL1_t
index URL

IRDA Transmit Pulse Length Bit 1

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRTXPL1_t {
    UCIRTXPL1_OFF,
    // Bit 1 OFF
    UCIRTXPL1
    // Bit 1 ON
};
enum IUSCI_A1_UART.UCIRTXPL2_t
index URL

IRDA Transmit Pulse Length Bit 2

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRTXPL2_t {
    UCIRTXPL2_OFF,
    // Bit 2 OFF
    UCIRTXPL2
    // Bit 2 ON
};
enum IUSCI_A1_UART.UCIRTXPL3_t
index URL

IRDA Transmit Pulse Length Bit 3

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRTXPL3_t {
    UCIRTXPL3_OFF,
    // Bit 3 OFF
    UCIRTXPL3
    // Bit 3 ON
};
enum IUSCI_A1_UART.UCIRTXPL4_t
index URL

IRDA Transmit Pulse Length Bit 4

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRTXPL4_t {
    UCIRTXPL4_OFF,
    // Bit 4 OFF
    UCIRTXPL4
    // Bit 4 ON
};
enum IUSCI_A1_UART.UCIRTXPL5_t
index URL

IRDA Transmit Pulse Length Bit 5

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCIRTXPL5_t {
    UCIRTXPL5_OFF,
    // Bit 5 OFF
    UCIRTXPL5
    // Bit 5 ON
};
enum IUSCI_A1_UART.UCLISTEN_t
index URL

Listen enable. The UCLISTEN bit selects loopback mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCLISTEN_t {
    UCLISTEN_OFF,
    // Disabled
    UCLISTEN
    // Enabled. UCAxTXD is internally fed back to the receiver
};
enum IUSCI_A1_UART.UCMODE_ASYNC_t
index URL

USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCMODE_ASYNC_t {
    UCMODE_0,
    // UART Mode
    UCMODE_1,
    // Idle-Line Multiprocessor Mode
    UCMODE_2,
    // Address-Bit Multiprocessor Mode
    UCMODE_3
    // UART Mode with automatic baud rate detection
};
enum IUSCI_A1_UART.UCMODE_SYNC_t
index URL

USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCMODE_SYNC_t {
    UCMODE_0,
    // 3-Pin SPI
    UCMODE_1,
    // 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
    UCMODE_2,
    // 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
    UCMODE_3
    // I2C Mode
};
enum IUSCI_A1_UART.UCMSB_t
index URL

MSB first select. Controls the direction of the receive and transmit shift register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCMSB_t {
    UCMSB_OFF,
    // LSB first
    UCMSB
    // MSB first
};
enum IUSCI_A1_UART.UCOE_t
index URL

Overrun error flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCOE_t {
    UCOE_OFF,
    // No error
    UCOE
    // Overrun error occurred
};
enum IUSCI_A1_UART.UCOS16_t
index URL

Oversampling mode enabled

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCOS16_t {
    UCOS16_OFF,
    // Disabled
    UCOS16
    // Enabled
};
enum IUSCI_A1_UART.UCPAR_t
index URL

Parity select. UCPAR is not used when parity is disabled

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCPAR_t {
    UCPAR_OFF,
    // Odd parity
    UCPAR
    // Even parity
};
enum IUSCI_A1_UART.UCPEN_t
index URL

Parity enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCPEN_t {
    UCPEN_OFF,
    // Parity Disabled
    UCPEN
    // Parity Enabled
};
enum IUSCI_A1_UART.UCPE_t
index URL

Parity error flag. When UCPEN = 0, UCPE is read as 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCPE_t {
    UCPE_OFF,
    // No error
    UCPE
    // Character received with parity error
};
enum IUSCI_A1_UART.UCRXEIE_t
index URL

Receive erroneous-character interrupt-enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCRXEIE_t {
    UCRXEIE_OFF,
    // Erroneous characters rejected and UCAxRXIFG is not set
    UCRXEIE
    // Erroneous characters received will set UCAxRXIFG
};
enum IUSCI_A1_UART.UCRXERR_t
index URL

Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCRXERR_t {
    UCRXERR_OFF,
    // No receive errors detected
    UCRXERR
    // Receive error detected
};
enum IUSCI_A1_UART.UCSPB_t
index URL

Stop bit select. Number of stop bits

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCSPB_t {
    UCSPB_OFF,
    // One stop bit
    UCSPB
    // Two stop bits
};
enum IUSCI_A1_UART.UCSSEL_UART_t
index URL

USCI clock source select. These bits select the BRCLK source clock

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCSSEL_UART_t {
    UCSSEL_0,
    // UCLK
    UCSSEL_1,
    // ACLK
    UCSSEL_2
    // SMCLK
};
enum IUSCI_A1_UART.UCSTOE_t
index URL

Synch field time out error

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCSTOE_t {
    UCSTOE_OFF,
    // No error
    UCSTOE
    // Length of synch field exceeded measurable time
};
enum IUSCI_A1_UART.UCSWRST_t
index URL

Software reset enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCSWRST_t {
    UCSWRST_OFF,
    // Disabled. USCI reset released for operation
    UCSWRST
    // Enabled. USCI logic held in reset state
};
enum IUSCI_A1_UART.UCSYNC_t
index URL

Synchronous mode enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCSYNC_t {
    UCSYNC_OFF,
    // Asynchronous mode
    UCSYNC
    // Synchronous Mode
};
enum IUSCI_A1_UART.UCTXADDR_t
index URL

Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCTXADDR_t {
    UCTXADDR_OFF,
    // Next frame transmitted is data
    UCTXADDR
    // Next frame transmitted is an address
};
enum IUSCI_A1_UART.UCTXBRK_t
index URL

Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
enum UCTXBRK_t {
    UCTXBRK_OFF,
    // Next frame transmitted is not a break
    UCTXBRK
    // Next frame transmitted is a break or a break/synch
};
typedef IUSCI_A1_UART.IPeripheralArray
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
typedef IPeripheral.Instance IPeripheralArray[];
typedef IUSCI_A1_UART.StringArray
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
typedef String StringArray[];
struct IUSCI_A1_UART.ForceSetDefaultRegister_t
index URL

Force Set Default Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
metaonly struct ForceSetDefaultRegister_t {
    String register;
    Bool regForceSet;
};
DETAILS
Type to store if each register needs to be forced initialized even if the register is in default state.
SEE
ForceSetDefaultRegister_t
struct IUSCI_A1_UART.UCxABCTL_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
metaonly struct UCxABCTL_t {
    IUSCI_UART.UCDELIM1_t UCDELIM1;
    // Break/synch delimiter length 00 1 bit time 01 2 bit times 10 3 bit times 11 4 bit times
    IUSCI_UART.UCDELIM0_t UCDELIM0;
    // Break/synch delimiter length 00 1 bit time 01 2 bit times 10 3 bit times 11 4 bit times
    IUSCI_UART.UCSTOE_t UCSTOE;
    // Synch field time out error 0 No error 1 Length of synch field exceeded measurable time
    IUSCI_UART.UCBTOE_t UCBTOE;
    // Break time out error 0 No error 1 Length of break field exceeded 22 bit times
    IUSCI_UART.UCABDEN_t UCABDEN;
    // Automatic baud rate detect enable 0 Baud rate detection disabled. Length of break and synch field is not measured. 1 Baud rate detection enabled. Length of break and synch field is measured and baud rate settings are changed accordingly
};
struct IUSCI_A1_UART.UCxCTL0_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
metaonly struct UCxCTL0_t {
    IUSCI_UART.UCPEN_t UCPEN;
    // Parity enable 0 Parity disabled. 1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation
    IUSCI_UART.UCPAR_t UCPAR;
    // Parity select. UCPAR is not used when parity is disabled. 0 Odd parity 1 Even parity
    IUSCI_UART.UCMSB_t UCMSB;
    // MSB first select. Controls the direction of the receive and transmit shift register. 0 LSB first 1 MSB first
    IUSCI_UART.UC7BIT_t UC7BIT;
    // Character length. Selects 7-bit or 8-bit character length. 0 8-bit data 1 7-bit data
    IUSCI_UART.UCSPB_t UCSPB;
    // Stop bit select. Number of stop bits. 0 One stop bit 1 Two stop bits
    IUSCI_UART.UCMODE_ASYNC_t UCMODE;
    // USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0. 00 UART Mode. 01 Idle-Line Multiprocessor Mode. 10 Address-Bit Multiprocessor Mode. 11 UART Mode with automatic baud rate detection
    IUSCI_UART.UCSYNC_t UCSYNC;
    // Synchronous mode enable 0 Asynchronous mode 1 Synchronous Mode
};
struct IUSCI_A1_UART.UCxCTL1_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
metaonly struct UCxCTL1_t {
    IUSCI_UART.UCSSEL_UART_t UCSSEL;
    // USCI clock source select. These bits select the BRCLK source clock. 00 UCLK 01 ACLK 10 SMCLK 11 SMCLK
    IUSCI_UART.UCRXEIE_t UCRXEIE;
    // Receive erroneous-character interrupt-enable 0 Erroneous characters rejected and UCAxRXIFG is not set 1 Erroneous characters received will set UCAxRXIFG
    IUSCI_UART.UCBRKIE_t UCBRKIE;
    // Receive break character interrupt-enable 0 Received break characters do not set UCAxRXIFG. 1 Received break characters set UCAxRXIFG
    IUSCI_UART.UCDORM_t UCDORM;
    // Dormant. Puts USCI into sleep mode. 0 Not dormant. All received characters will set UCAxRXIFG. 1 Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG
    IUSCI_UART.UCTXADDR_t UCTXADDR;
    // Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode. 0 Next frame transmitted is data 1 Next frame transmitted is an address
    IUSCI_UART.UCTXBRK_t UCTXBRK;
    // Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer. 0 Next frame transmitted is not a break 1 Next frame transmitted is a break or a break/synch
    IUSCI_UART.UCSWRST_t UCSWRST;
    // Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state
};
struct IUSCI_A1_UART.UCxIRRCTL_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
metaonly struct UCxIRRCTL_t {
    IUSCI_UART.UCIRRXFL5_t UCIRRXFL5;
    // IRDA Receive Filter Length Bit 5
    IUSCI_UART.UCIRRXFL4_t UCIRRXFL4;
    // IRDA Receive Filter Length Bit 4
    IUSCI_UART.UCIRRXFL3_t UCIRRXFL3;
    // IRDA Receive Filter Length Bit 3
    IUSCI_UART.UCIRRXFL2_t UCIRRXFL2;
    // IRDA Receive Filter Length Bit 2
    IUSCI_UART.UCIRRXFL1_t UCIRRXFL1;
    // IRDA Receive Filter Length Bit 1
    IUSCI_UART.UCIRRXFL0_t UCIRRXFL0;
    // IRDA Receive Filter Length Bit 0
    IUSCI_UART.UCIRRXPL_t UCIRRXPL;
    // IrDA receive input UCAxRXD polarity 0 IrDA transceiver delivers a high pulse when a light pulse is seen 1 IrDA transceiver delivers a low pulse when a light pulse is seen
    IUSCI_UART.UCIRRXFE_t UCIRRXFE;
    // IrDA receive filter enabled 0 Receive filter disabled 1 Receive filter enabled
};
struct IUSCI_A1_UART.UCxIRTCTL_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
metaonly struct UCxIRTCTL_t {
    IUSCI_UART.UCIRTXPL5_t UCIRTXPL5;
    // IRDA Transmit Pulse Length Bit 5
    IUSCI_UART.UCIRTXPL4_t UCIRTXPL4;
    // IRDA Transmit Pulse Length Bit 4
    IUSCI_UART.UCIRTXPL3_t UCIRTXPL3;
    // IRDA Transmit Pulse Length Bit 3
    IUSCI_UART.UCIRTXPL2_t UCIRTXPL2;
    // IRDA Transmit Pulse Length Bit 2
    IUSCI_UART.UCIRTXPL1_t UCIRTXPL1;
    // IRDA Transmit Pulse Length Bit 1
    IUSCI_UART.UCIRTXPL0_t UCIRTXPL0;
    // IRDA Transmit Pulse Length Bit 0
    IUSCI_UART.UCIRTXCLK_t UCIRTXCLK;
    // IrDA transmit pulse clock select 0 BRCLK 1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK
    IUSCI_UART.UCIREN_t UCIREN;
    // IrDA encoder/decoder enable. 0 IrDA encoder/decoder disabled 1 IrDA encoder/decoder enabled
};
struct IUSCI_A1_UART.UCxMCTL_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
metaonly struct UCxMCTL_t {
    IUSCI_UART.UCBRF_t UCBRF;
    // First modulation stage select. These bits determine the modulation pattern for BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0
    IUSCI_UART.UCBRS_t UCBRS;
    // Second modulation stage select. These bits determine the modulation pattern for BITCLK
    IUSCI_UART.UCOS16_t UCOS16;
    // Oversampling mode enabled 0 Disabled 1 Enabled
};
struct IUSCI_A1_UART.UCxSTAT_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
metaonly struct UCxSTAT_t {
    IUSCI_UART.UCLISTEN_t UCLISTEN;
    // Listen enable. The UCLISTEN bit selects loopback mode. 0 Disabled 1 Enabled. UCAxTXD is internally fed back to the receiver
    IUSCI_UART.UCFE_t UCFE;
    // Framing error flag 0 No error 1 Character received with low stop bit
    IUSCI_UART.UCOE_t UCOE;
    // Overrun error flag. This bit is set when a character is transferred into UCAxRXBUF before the previous character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by software. Otherwise, it will not function correctly. 0 No error 1 Overrun error occurred
    IUSCI_UART.UCPE_t UCPE;
    // Parity error flag. When UCPEN = 0, UCPE is read as 0. 0 No error 1 Character received with parity error
    IUSCI_UART.UCBRK_t UCBRK;
    // Break detect flag 0 No break condition 1 Break condition occurred
    IUSCI_UART.UCRXERR_t UCRXERR;
    // Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read. 0 No receive errors detected 1 Receive error detected
    IUSCI_UART.UCADDR_t UCADDR;
    // Address received in address-bit multiprocessor mode. 0 Received character is data 1 Received character is an address
    IUSCI_UART.UCIDLE_t UCIDLE;
    // Idle line detected in idle-line multiprocessor mode. 0 No idle line detected 1 Idle line detected
    IUSCI_UART.UCBUSY_t UCBUSY;
    // USCI busy. This bit indicates if a transmit or receive operation is in progress. 0 USCI inactive 1 USCI transmitting or receiving
};
IUSCI_A1_UART.addPeripheralsMap()  // module-wide
index URL

Create a map of all peripherals available on a device

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
Void addPeripheralsMap(ICpuDataSheet.Instance cds);
ARGUMENTS
cds — an xdc.platform.ICpuDataSheet instance
DETAILS
The config parameter peripherals is by default undefined in an xdc.platform.ICpuDataSheet instance. This function gathers all instance configuration parameters that are of the type xdc.platform.IPeripheral into the map peripherals.
IUSCI_A1_UART.getAll()  // module-wide
index URL

Find all peripherals of a certain type

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
IPeripheral.IPeripheralArray getAll();
DETAILS
The type of the peripherals returned is defined by the type of the caller.
RETURNS
Returns an array of IPeripheral instances
IUSCI_A1_UART.getRegisters()  // module-wide
index URL

Find all registers defined by the peripheral

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
IPeripheral.StringArray getRegisters();
RETURNS
Returns an array of register names
config IUSCI_A1_UART.UCA1ABCTL  // instance
index URL

Auto Baud Rate Control Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
config IUSCI_A1_UART.UCxABCTL_t UCA1ABCTL = {
    UCDELIM1: IUSCI_UART.UCDELIM1_OFF,
    UCDELIM0: IUSCI_UART.UCDELIM0_OFF,
    UCSTOE: IUSCI_UART.UCSTOE_OFF,
    UCBTOE: IUSCI_UART.UCBTOE_OFF,
    UCABDEN: IUSCI_UART.UCABDEN_OFF
};
config IUSCI_A1_UART.UCA1BR0  // instance
index URL

Baud rate control register 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
config UChar UCA1BR0 = 0;
config IUSCI_A1_UART.UCA1BR1  // instance
index URL

Baud rate control register 1

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
config UChar UCA1BR1 = 0;
config IUSCI_A1_UART.UCA1CTL0  // instance
index URL

Control Register 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
config IUSCI_A1_UART.UCxCTL0_t UCA1CTL0 = {
    UCPEN: IUSCI_UART.UCPEN_OFF,
    UCPAR: IUSCI_UART.UCPAR_OFF,
    UCMSB: IUSCI.UCMSB_OFF,
    UC7BIT: IUSCI.UC7BIT_OFF,
    UCSPB: IUSCI_UART.UCSPB_OFF,
    UCMODE: IUSCI_UART.UCMODE_0,
    UCSYNC: IUSCI.UCSYNC_OFF
};
config IUSCI_A1_UART.UCA1CTL1  // instance
index URL

Control Register 1

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
config IUSCI_A1_UART.UCxCTL1_t UCA1CTL1 = {
    UCSSEL: IUSCI_UART.UCSSEL_0,
    UCRXEIE: IUSCI.UCRXEIE_OFF,
    UCBRKIE: IUSCI.UCBRKIE_OFF,
    UCDORM: IUSCI.UCDORM_OFF,
    UCTXADDR: IUSCI.UCTXADDR_OFF,
    UCTXBRK: IUSCI.UCTXBRK_OFF,
    UCSWRST: IUSCI.UCSWRST
};
config IUSCI_A1_UART.UCA1IRRCTL  // instance
index URL

IrDA Receive Control Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
config IUSCI_A1_UART.UCxIRRCTL_t UCA1IRRCTL = {
    UCIRRXFL5: IUSCI_UART.UCIRRXFL5_OFF,
    UCIRRXFL4: IUSCI_UART.UCIRRXFL4_OFF,
    UCIRRXFL3: IUSCI_UART.UCIRRXFL3_OFF,
    UCIRRXFL2: IUSCI_UART.UCIRRXFL2_OFF,
    UCIRRXFL1: IUSCI_UART.UCIRRXFL1_OFF,
    UCIRRXFL0: IUSCI_UART.UCIRRXFL0_OFF,
    UCIRRXPL: IUSCI_UART.UCIRRXPL_OFF,
    UCIRRXFE: IUSCI_UART.UCIRRXFE_OFF
};
config IUSCI_A1_UART.UCA1IRTCTL  // instance
index URL

IrDA Transmit Control Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
config IUSCI_A1_UART.UCxIRTCTL_t UCA1IRTCTL = {
    UCIRTXPL5: IUSCI_UART.UCIRTXPL5_OFF,
    UCIRTXPL4: IUSCI_UART.UCIRTXPL4_OFF,
    UCIRTXPL3: IUSCI_UART.UCIRTXPL3_OFF,
    UCIRTXPL2: IUSCI_UART.UCIRTXPL2_OFF,
    UCIRTXPL1: IUSCI_UART.UCIRTXPL1_OFF,
    UCIRTXPL0: IUSCI_UART.UCIRTXPL0_OFF,
    UCIRTXCLK: IUSCI_UART.UCIRTXCLK_OFF,
    UCIREN: IUSCI_UART.UCIREN_OFF
};
config IUSCI_A1_UART.UCA1MCTL  // instance
index URL

Modulation Control Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
config IUSCI_A1_UART.UCxMCTL_t UCA1MCTL = {
    UCBRF: IUSCI_UART.UCBRF_0,
    UCBRS: IUSCI_UART.UCBRS_0,
    UCOS16: IUSCI_UART.UCOS16_OFF
};
config IUSCI_A1_UART.UCA1RXBUF  // instance
index URL

Receive Buffer Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
config UChar UCA1RXBUF = 0;
config IUSCI_A1_UART.UCA1STAT  // instance
index URL

Status Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
config IUSCI_A1_UART.UCxSTAT_t UCA1STAT = {
    UCLISTEN: IUSCI.UCLISTEN_OFF,
    UCFE: IUSCI.UCFE_OFF,
    UCOE: IUSCI.UCOE_OFF,
    UCPE: IUSCI.UCPE_OFF,
    UCBRK: IUSCI.UCBRK_OFF,
    UCRXERR: IUSCI.UCRXERR_OFF,
    UCADDR: IUSCI.UCADDR_OFF,
    UCIDLE: IUSCI.UCIDLE_OFF,
    UCBUSY: IUSCI.UCBUSY
};
config IUSCI_A1_UART.UCA1TXBUF  // instance
index URL

Transmit Buffer Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
config UChar UCA1TXBUF = 0;
config IUSCI_A1_UART.UCLKHz  // instance
index URL

Stores the UCLK external clock frequency in float

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
config Float UCLKHz = 1000000;
config IUSCI_A1_UART.name  // instance
index URL

Specific peripheral name given by the device

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
config String name;
DETAILS
Devices can have more than one peripheral of the same type. In such cases, device data sheets give different names to the instances of a same peripheral. For example, the name for a timer module could be TimerA3, and a device that has two such timers can name them TA0 and TA1.
config IUSCI_A1_UART.owner  // instance
index URL

String specifying the entity that manages the peripheral

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
config String owner;
IUSCI_A1_UART.getUCRXIE()  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
Bool getUCRXIE();
IUSCI_A1_UART.getUCTXIE()  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
Bool getUCTXIE();
IUSCI_A1_UART.setUCRXIE()  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
Bool setUCRXIE(Bool set);
IUSCI_A1_UART.setUCTXIE()  // instance
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_A1_UART.xdc
Bool setUCTXIE(Bool set);
generated on Tue, 24 Aug 2010 15:40:43 GMT