J784S4 Interrupt Management Device Descriptions¶
Introduction¶
This chapter provides information on the Interrupt Management devices in the J784S4 SoC. Some System Firmware TISCI messages take device specific inputs. This chapter provides information on the valid values for Interrupt Management TISCI message parameters.
Interrupt Router Device IDs¶
Some System Firmware TISCI message APIs require the Interrupt Router device ID be provided as part of the request. Based on J784S4 Device IDs these are the valid Interrupt Router device IDs.
| Interrupt Router Device Name | Interrupt Router Device ID |
|---|---|
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 |
| J784S4_DEV_NAVSS0_INTR_0 | 283 |
| J784S4_DEV_MCU_NAVSS0_INTR_ROUTER_0 | 324 |
MAIN2MCU_LVL_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 0 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 1 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 2 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 3 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 4 | J784S4_DEV_SA2_UL0 | sa_ul_trng | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 5 | J784S4_DEV_SA2_UL0 | sa_ul_pka | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 6 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 7 | J784S4_DEV_ELM0 | elm_porocpsinterrupt_lvl | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 8 | J784S4_DEV_GPMC0 | gpmc_sinterrupt | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 9 | J784S4_DEV_DDR0 | ddrss_pll_freq_change_req | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 10 | J784S4_DEV_DDR0 | ddrss_controller | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 11 | J784S4_DEV_DDR0 | ddrss_v2a_other_err_lvl | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 12 | J784S4_DEV_DDR0 | ddrss_hs_phy_global_error | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 13 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 14 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 15 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 16 | J784S4_DEV_MCAN0 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 17 | J784S4_DEV_MCAN0 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 18 | J784S4_DEV_MCAN0 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 19 | J784S4_DEV_MCAN1 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 20 | J784S4_DEV_MCAN1 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 21 | J784S4_DEV_MCAN1 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 22 | J784S4_DEV_MCAN2 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 23 | J784S4_DEV_MCAN2 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 24 | J784S4_DEV_MCAN2 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 25 | J784S4_DEV_MCAN3 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 26 | J784S4_DEV_MCAN3 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 27 | J784S4_DEV_MCAN3 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 28 | J784S4_DEV_MMCSD0 | emmcss_intr | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 29 | J784S4_DEV_MMCSD1 | emmcsdss_intr | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 30 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 31 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 32 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 33 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 34 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 35 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 36 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 37 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 38 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 39 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 40 | J784S4_DEV_VPAC1 | vpac_level | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 41 | J784S4_DEV_VPAC1 | vpac_level | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 42 | J784S4_DEV_VPAC1 | vpac_level | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 43 | J784S4_DEV_VPAC1 | vpac_level | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 44 | J784S4_DEV_VPAC1 | vpac_level | 4 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 45 | J784S4_DEV_VPAC1 | vpac_level | 5 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 46 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 47 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 48 | J784S4_DEV_MCSPI0 | intr_spi | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 49 | J784S4_DEV_MCSPI1 | intr_spi | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 50 | J784S4_DEV_MCSPI2 | intr_spi | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 51 | J784S4_DEV_MCSPI3 | intr_spi | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 52 | J784S4_DEV_MCSPI4 | intr_spi | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 53 | J784S4_DEV_MCSPI5 | intr_spi | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 54 | J784S4_DEV_MCSPI6 | intr_spi | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 55 | J784S4_DEV_MCSPI7 | intr_spi | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 56 | J784S4_DEV_I2C0 | pointrpend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 57 | J784S4_DEV_I2C1 | pointrpend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 58 | J784S4_DEV_I2C2 | pointrpend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 59 | J784S4_DEV_I2C3 | pointrpend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 60 | J784S4_DEV_I2C4 | pointrpend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 61 | J784S4_DEV_I2C5 | pointrpend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 62 | J784S4_DEV_I2C6 | pointrpend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 63 | J784S4_DEV_DDR1 | ddrss_pll_freq_change_req | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 64 | J784S4_DEV_DDR1 | ddrss_controller | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 65 | J784S4_DEV_DDR1 | ddrss_v2a_other_err_lvl | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 66 | J784S4_DEV_DDR1 | ddrss_hs_phy_global_error | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 67 | J784S4_DEV_PCIE0 | pcie_phy_level | 13 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 68 | J784S4_DEV_PCIE0 | pcie_local_level | 12 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 69 | J784S4_DEV_PCIE0 | pcie_cpts_pend | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 70 | J784S4_DEV_CPSW1 | stat_pend | 6 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 71 | J784S4_DEV_CPSW1 | mdio_pend | 5 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 72 | J784S4_DEV_CPSW1 | evnt_pend | 4 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 73 | J784S4_DEV_PCIE1 | pcie_phy_level | 13 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 74 | J784S4_DEV_PCIE1 | pcie_local_level | 12 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 75 | J784S4_DEV_PCIE1 | pcie_cpts_pend | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 76 | J784S4_DEV_PCIE2 | pcie_phy_level | 13 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 77 | J784S4_DEV_PCIE2 | pcie_local_level | 12 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 78 | J784S4_DEV_PCIE2 | pcie_cpts_pend | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 79 | J784S4_DEV_PCIE3 | pcie_phy_level | 13 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 80 | J784S4_DEV_PCIE3 | pcie_local_level | 12 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 81 | J784S4_DEV_PCIE3 | pcie_cpts_pend | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 82 | J784S4_DEV_VUSR_DUAL0 | v0_vusr_intlvl | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 83 | J784S4_DEV_VUSR_DUAL0 | v0_mcp_lo_intlvl | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 84 | J784S4_DEV_VUSR_DUAL0 | v0_mcp_hi_intlvl | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 85 | J784S4_DEV_VUSR_DUAL0 | v1_vusr_intlvl | 5 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 86 | J784S4_DEV_VUSR_DUAL0 | v1_mcp_lo_intlvl | 4 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 87 | J784S4_DEV_VUSR_DUAL0 | v1_mcp_hi_intlvl | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 88 | J784S4_DEV_DCC0 | intr_done_level | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 89 | J784S4_DEV_DCC1 | intr_done_level | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 90 | J784S4_DEV_DCC2 | intr_done_level | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 91 | J784S4_DEV_DCC3 | intr_done_level | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 92 | J784S4_DEV_DCC4 | intr_done_level | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 93 | J784S4_DEV_DCC5 | intr_done_level | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 94 | J784S4_DEV_DCC6 | intr_done_level | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 95 | J784S4_DEV_DCC7 | intr_done_level | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 96 | J784S4_DEV_UART0 | usart_irq | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 97 | J784S4_DEV_UART1 | usart_irq | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 98 | J784S4_DEV_UART2 | usart_irq | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 99 | J784S4_DEV_UART3 | usart_irq | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 100 | J784S4_DEV_UART4 | usart_irq | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 101 | J784S4_DEV_UART5 | usart_irq | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 102 | J784S4_DEV_UART6 | usart_irq | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 103 | J784S4_DEV_UART7 | usart_irq | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 104 | J784S4_DEV_UART8 | usart_irq | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 105 | J784S4_DEV_UART9 | usart_irq | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 106 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 107 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 108 | J784S4_DEV_TIMER0 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 109 | J784S4_DEV_TIMER1 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 110 | J784S4_DEV_TIMER2 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 111 | J784S4_DEV_TIMER3 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 112 | J784S4_DEV_TIMER4 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 113 | J784S4_DEV_TIMER5 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 114 | J784S4_DEV_TIMER6 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 115 | J784S4_DEV_TIMER7 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 116 | J784S4_DEV_TIMER8 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 117 | J784S4_DEV_TIMER9 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 118 | J784S4_DEV_TIMER10 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 119 | J784S4_DEV_TIMER11 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 120 | J784S4_DEV_TIMER12 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 121 | J784S4_DEV_TIMER13 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 122 | J784S4_DEV_TIMER14 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 123 | J784S4_DEV_TIMER15 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 124 | J784S4_DEV_TIMER16 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 125 | J784S4_DEV_TIMER17 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 126 | J784S4_DEV_TIMER18 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 127 | J784S4_DEV_TIMER19 | intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 128 | J784S4_DEV_USB0 | irq | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 129 | J784S4_DEV_USB0 | irq | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 130 | J784S4_DEV_USB0 | irq | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 131 | J784S4_DEV_USB0 | irq | 4 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 132 | J784S4_DEV_USB0 | irq | 5 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 133 | J784S4_DEV_USB0 | irq | 6 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 134 | J784S4_DEV_USB0 | irq | 7 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 135 | J784S4_DEV_USB0 | irq | 8 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 136 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 137 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 138 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 139 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 140 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 141 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 142 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 143 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 144 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 145 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 146 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 147 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 148 | J784S4_DEV_DDR3 | ddrss_pll_freq_change_req | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 149 | J784S4_DEV_DDR3 | ddrss_controller | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 150 | J784S4_DEV_DDR3 | ddrss_v2a_other_err_lvl | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 151 | J784S4_DEV_DDR3 | ddrss_hs_phy_global_error | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 152 | J784S4_DEV_USB0 | otgirq | 9 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 153 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 154 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 155 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 156 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 157 | J784S4_DEV_USB0 | host_system_error | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 158 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 159 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 160 | J784S4_DEV_MCAN14 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 161 | J784S4_DEV_MCAN14 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 162 | J784S4_DEV_MCAN14 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 163 | J784S4_DEV_MCAN15 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 164 | J784S4_DEV_MCAN15 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 165 | J784S4_DEV_MCAN15 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 166 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 167 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 168 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 169 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 170 | J784S4_DEV_MCAN16 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 171 | J784S4_DEV_MCAN16 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 172 | J784S4_DEV_MCAN16 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 173 | J784S4_DEV_MCAN17 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 174 | J784S4_DEV_MCAN17 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 175 | J784S4_DEV_MCAN17 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 176 | J784S4_DEV_MCASP0 | xmit_intr_pend | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 177 | J784S4_DEV_MCASP0 | rec_intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 178 | J784S4_DEV_MCASP1 | xmit_intr_pend | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 179 | J784S4_DEV_MCASP1 | rec_intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 180 | J784S4_DEV_MCASP2 | xmit_intr_pend | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 181 | J784S4_DEV_MCASP2 | rec_intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 182 | J784S4_DEV_MCASP3 | xmit_intr_pend | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 183 | J784S4_DEV_MCASP3 | rec_intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 184 | J784S4_DEV_MCASP4 | xmit_intr_pend | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 185 | J784S4_DEV_MCASP4 | rec_intr_pend | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 186 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 187 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 188 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 189 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 190 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 191 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 192 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 193 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 194 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 195 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 196 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 197 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 198 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 199 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 200 | J784S4_DEV_DDR2 | ddrss_pll_freq_change_req | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 201 | J784S4_DEV_DDR2 | ddrss_controller | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 202 | J784S4_DEV_DDR2 | ddrss_v2a_other_err_lvl | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 203 | J784S4_DEV_DDR2 | ddrss_hs_phy_global_error | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 204 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 205 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 206 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 207 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 208 | J784S4_DEV_DCC8 | intr_done_level | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 209 | J784S4_DEV_DCC9 | intr_done_level | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 210 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 211 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 212 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 213 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 214 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 215 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 216 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 217 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 218 | J784S4_DEV_UFS0 | ufs_intr | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 219 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 220 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 221 | J784S4_DEV_CPSW_9XUSS_J7AM0 | stat_pend | 6 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 222 | J784S4_DEV_CPSW_9XUSS_J7AM0 | mdio_pend | 5 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 223 | J784S4_DEV_CPSW_9XUSS_J7AM0 | evnt_pend | 4 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 224 | J784S4_DEV_DSS_DSI0 | dsi_0_func_intr | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 225 | J784S4_DEV_DSS_DSI1 | dsi_0_func_intr | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 226 | J784S4_DEV_DSS0 | dss_inst0_dispc_func_irq_proc0 | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 227 | J784S4_DEV_DSS0 | dss_inst0_dispc_func_irq_proc1 | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 228 | J784S4_DEV_DSS0 | dss_inst0_dispc_secure_irq_proc0 | 4 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 229 | J784S4_DEV_DSS0 | dss_inst0_dispc_secure_irq_proc1 | 5 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 230 | J784S4_DEV_DSS0 | dss_inst0_dispc_safety_error_irq_proc0 | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 231 | J784S4_DEV_DSS0 | dss_inst0_dispc_safety_error_irq_proc1 | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 232 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 233 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 234 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 235 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 236 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 237 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 238 | J784S4_DEV_DSS_EDP0 | intr | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 239 | J784S4_DEV_DSS_EDP0 | intr | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 240 | J784S4_DEV_DSS_EDP0 | intr | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 241 | J784S4_DEV_DSS_EDP0 | intr | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 242 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 243 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 244 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 245 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 246 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 247 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 248 | J784S4_DEV_CSI_TX_IF1 | csi_interrupt | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 249 | J784S4_DEV_CSI_TX_IF1 | csi_level | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 250 | J784S4_DEV_CSI_TX_IF0 | csi_interrupt | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 251 | J784S4_DEV_CSI_TX_IF0 | csi_level | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 252 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 253 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 254 | J784S4_DEV_CSI_RX_IF0 | csi_irq | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 255 | J784S4_DEV_CSI_RX_IF0 | csi_err_irq | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 256 | J784S4_DEV_CSI_RX_IF0 | csi_level | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 257 | J784S4_DEV_CSI_RX_IF1 | csi_irq | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 258 | J784S4_DEV_CSI_RX_IF1 | csi_err_irq | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 259 | J784S4_DEV_CSI_RX_IF1 | csi_level | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 260 | J784S4_DEV_CSI_RX_IF2 | csi_irq | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 261 | J784S4_DEV_CSI_RX_IF2 | csi_err_irq | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 262 | J784S4_DEV_CSI_RX_IF2 | csi_level | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 263 | J784S4_DEV_CODEC0 | vpu_wave521cl_intr | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 264 | J784S4_DEV_CODEC1 | vpu_wave521cl_intr | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 265 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 266 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 267 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 268 | J784S4_DEV_DMPAC0_INTD_0 | system_intr_level | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 269 | J784S4_DEV_DMPAC0_INTD_0 | system_intr_level | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 270 | J784S4_DEV_VPAC0 | vpac_level | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 271 | J784S4_DEV_VPAC0 | vpac_level | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 272 | J784S4_DEV_VPAC0 | vpac_level | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 273 | J784S4_DEV_VPAC0 | vpac_level | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 274 | J784S4_DEV_VPAC0 | vpac_level | 4 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 275 | J784S4_DEV_VPAC0 | vpac_level | 5 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 276 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 277 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 278 | J784S4_DEV_MCAN4 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 279 | J784S4_DEV_MCAN4 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 280 | J784S4_DEV_MCAN4 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 281 | J784S4_DEV_MCAN5 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 282 | J784S4_DEV_MCAN5 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 283 | J784S4_DEV_MCAN5 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 284 | J784S4_DEV_MCAN6 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 285 | J784S4_DEV_MCAN6 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 286 | J784S4_DEV_MCAN6 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 287 | J784S4_DEV_MCAN7 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 288 | J784S4_DEV_MCAN7 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 289 | J784S4_DEV_MCAN7 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 290 | J784S4_DEV_MCAN8 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 291 | J784S4_DEV_MCAN8 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 292 | J784S4_DEV_MCAN8 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 293 | J784S4_DEV_MCAN9 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 294 | J784S4_DEV_MCAN9 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 295 | J784S4_DEV_MCAN9 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 296 | J784S4_DEV_MCAN10 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 297 | J784S4_DEV_MCAN10 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 298 | J784S4_DEV_MCAN10 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 299 | J784S4_DEV_MCAN11 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 300 | J784S4_DEV_MCAN11 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 301 | J784S4_DEV_MCAN11 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 302 | J784S4_DEV_MCAN12 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 303 | J784S4_DEV_MCAN12 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 304 | J784S4_DEV_MCAN12 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 305 | J784S4_DEV_MCAN13 | mcanss_mcan_lvl_int | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 306 | J784S4_DEV_MCAN13 | mcanss_mcan_lvl_int | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 307 | J784S4_DEV_MCAN13 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 308 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 309 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 310 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 311 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 312 | J784S4_DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0 | os_irq | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 313 | J784S4_DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0 | os_irq | 1 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 314 | J784S4_DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0 | os_irq | 2 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 315 | J784S4_DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0 | os_irq | 3 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 316 | J784S4_DEV_J7AEP_GPU_BXS464_WRAP0 | gpu_pwrctrl_req | 0 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 317 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 318 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 319 | Use TRM - Not managed by TISCI |
MAIN2MCU_LVL_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 0 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 160 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 160 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 1 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 161 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 161 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 2 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 162 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 162 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 3 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 163 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 163 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 4 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 164 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 164 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 5 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 165 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 165 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 6 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 166 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 166 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 7 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 167 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 167 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 8 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 168 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 168 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 9 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 169 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 169 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 10 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 170 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 170 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 11 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 171 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 171 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 12 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 172 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 172 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 13 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 173 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 173 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 14 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 174 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 174 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 15 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 175 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 175 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 16 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 176 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 176 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 17 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 177 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 177 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 18 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 178 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 178 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 19 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 179 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 179 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 20 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 180 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 180 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 21 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 181 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 181 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 22 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 182 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 182 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 23 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 183 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 183 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 24 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 184 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 184 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 25 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 185 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 185 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 26 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 186 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 186 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 27 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 187 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 187 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 28 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 188 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 188 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 29 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 189 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 189 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 30 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 190 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 190 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 31 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 191 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 191 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 32 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 192 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 192 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 33 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 193 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 193 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 34 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 194 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 194 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 35 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 195 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 195 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 36 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 196 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 196 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 37 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 197 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 197 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 38 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 198 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 198 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 39 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 199 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 199 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 40 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 200 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 200 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 41 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 201 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 201 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 42 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 202 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 202 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 43 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 203 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 203 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 44 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 204 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 204 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 45 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 205 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 205 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 46 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 206 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 206 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 47 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 207 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 207 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 48 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 208 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 208 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 49 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 209 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 209 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 50 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 210 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 210 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 51 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 211 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 211 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 52 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 212 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 212 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 53 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 213 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 213 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 54 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 214 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 214 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 55 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 215 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 215 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 56 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 216 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 216 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 56 | J784S4_DEV_WKUP_HSM0 | nvic | 64 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 57 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 217 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 217 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 57 | J784S4_DEV_WKUP_HSM0 | nvic | 65 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 58 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 218 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 218 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 58 | J784S4_DEV_WKUP_HSM0 | nvic | 66 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 59 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 219 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 219 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 59 | J784S4_DEV_WKUP_HSM0 | nvic | 67 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 60 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 220 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 220 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 60 | J784S4_DEV_WKUP_HSM0 | nvic | 68 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 61 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 221 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 221 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 61 | J784S4_DEV_WKUP_HSM0 | nvic | 69 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 62 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 222 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 222 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 62 | J784S4_DEV_WKUP_HSM0 | nvic | 70 |
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 63 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 223 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 223 | |||
| J784S4_DEV_MAIN2MCU_LVL_INTRTR0 | 173 | 63 | J784S4_DEV_WKUP_HSM0 | nvic | 71 |
MAIN2MCU_PLS_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 0 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 1 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 2 | J784S4_DEV_EPWM0 | epwm_etint | 0 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 3 | J784S4_DEV_EPWM1 | epwm_etint | 0 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 4 | J784S4_DEV_EPWM2 | epwm_etint | 0 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 5 | J784S4_DEV_EPWM3 | epwm_etint | 0 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 6 | J784S4_DEV_EPWM4 | epwm_etint | 0 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 7 | J784S4_DEV_EPWM5 | epwm_etint | 0 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 8 | J784S4_DEV_EPWM0 | epwm_tripzint | 1 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 9 | J784S4_DEV_EPWM1 | epwm_tripzint | 1 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 10 | J784S4_DEV_EPWM2 | epwm_tripzint | 1 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 11 | J784S4_DEV_EPWM3 | epwm_tripzint | 1 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 12 | J784S4_DEV_EPWM4 | epwm_tripzint | 1 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 13 | J784S4_DEV_EPWM5 | epwm_tripzint | 1 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 14 | J784S4_DEV_EQEP0 | eqep_int | 0 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 15 | J784S4_DEV_EQEP1 | eqep_int | 0 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 16 | J784S4_DEV_EQEP2 | eqep_int | 0 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 17 | J784S4_DEV_ECAP0 | ecap_int | 0 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 18 | J784S4_DEV_ECAP1 | ecap_int | 0 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 19 | J784S4_DEV_ECAP2 | ecap_int | 0 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 20 | J784S4_DEV_PCIE0 | pcie_dpa_pulse | 6 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 21 | J784S4_DEV_PCIE1 | pcie_dpa_pulse | 6 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 22 | J784S4_DEV_PCIE2 | pcie_dpa_pulse | 6 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 23 | J784S4_DEV_PCIE3 | pcie_dpa_pulse | 6 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 24 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 25 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 26 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 27 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 28 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 29 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 30 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 31 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 32 | J784S4_DEV_PCIE0 | pcie_legacy_pulse | 10 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 33 | J784S4_DEV_PCIE0 | pcie_downstream_pulse | 5 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 34 | J784S4_DEV_PCIE0 | pcie_flr_pulse | 8 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 35 | J784S4_DEV_PCIE0 | pcie_error_pulse | 7 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 36 | J784S4_DEV_PCIE0 | pcie_link_state_pulse | 11 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 37 | J784S4_DEV_PCIE0 | pcie_pwr_state_pulse | 15 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 38 | J784S4_DEV_PCIE0 | pcie_ptm_valid_pulse | 14 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 39 | J784S4_DEV_PCIE0 | pcie_hot_reset_pulse | 9 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 40 | J784S4_DEV_PCIE1 | pcie_legacy_pulse | 10 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 41 | J784S4_DEV_PCIE1 | pcie_downstream_pulse | 5 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 42 | J784S4_DEV_PCIE1 | pcie_flr_pulse | 8 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 43 | J784S4_DEV_PCIE1 | pcie_error_pulse | 7 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 44 | J784S4_DEV_PCIE1 | pcie_link_state_pulse | 11 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 45 | J784S4_DEV_PCIE1 | pcie_pwr_state_pulse | 15 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 46 | J784S4_DEV_PCIE1 | pcie_ptm_valid_pulse | 14 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 47 | J784S4_DEV_PCIE1 | pcie_hot_reset_pulse | 9 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 48 | J784S4_DEV_PCIE2 | pcie_legacy_pulse | 10 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 49 | J784S4_DEV_PCIE2 | pcie_downstream_pulse | 5 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 50 | J784S4_DEV_PCIE2 | pcie_flr_pulse | 8 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 51 | J784S4_DEV_PCIE2 | pcie_error_pulse | 7 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 52 | J784S4_DEV_PCIE2 | pcie_link_state_pulse | 11 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 53 | J784S4_DEV_PCIE2 | pcie_pwr_state_pulse | 15 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 54 | J784S4_DEV_PCIE2 | pcie_ptm_valid_pulse | 14 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 55 | J784S4_DEV_PCIE2 | pcie_hot_reset_pulse | 9 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 56 | J784S4_DEV_PCIE3 | pcie_legacy_pulse | 10 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 57 | J784S4_DEV_PCIE3 | pcie_downstream_pulse | 5 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 58 | J784S4_DEV_PCIE3 | pcie_flr_pulse | 8 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 59 | J784S4_DEV_PCIE3 | pcie_error_pulse | 7 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 60 | J784S4_DEV_PCIE3 | pcie_link_state_pulse | 11 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 61 | J784S4_DEV_PCIE3 | pcie_pwr_state_pulse | 15 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 62 | J784S4_DEV_PCIE3 | pcie_ptm_valid_pulse | 14 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 63 | J784S4_DEV_PCIE3 | pcie_hot_reset_pulse | 9 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 64 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 0 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 65 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 1 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 66 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 2 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 67 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 3 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 68 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 4 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 69 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 5 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 70 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 6 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 71 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 7 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 72 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 8 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 73 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 9 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 74 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 10 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 75 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 11 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 76 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 12 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 77 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 13 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 78 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 14 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 79 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 15 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 80 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 16 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 81 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 17 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 82 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 18 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 83 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 19 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 84 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 20 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 85 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 21 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 86 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 22 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 87 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 23 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 88 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 24 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 89 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 25 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 90 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 26 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 91 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 27 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 92 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 28 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 93 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 29 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 94 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 30 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 95 | J784S4_DEV_GPIOMUX_INTRTR0 | outp | 31 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 96 | J784S4_DEV_CMPEVENT_INTRTR0 | outp | 4 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 97 | J784S4_DEV_CMPEVENT_INTRTR0 | outp | 5 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 98 | J784S4_DEV_CMPEVENT_INTRTR0 | outp | 6 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 99 | J784S4_DEV_CMPEVENT_INTRTR0 | outp | 7 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 100 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 101 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 102 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 103 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 104 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 105 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 106 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 107 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 108 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 109 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 110 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 111 | Use TRM - Not managed by TISCI |
MAIN2MCU_PLS_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 0 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 224 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 224 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 1 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 225 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 225 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 2 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 226 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 226 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 3 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 227 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 227 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 4 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 228 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 228 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 5 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 229 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 229 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 6 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 230 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 230 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 7 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 231 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 231 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 8 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 232 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 232 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 9 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 233 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 233 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 10 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 234 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 234 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 11 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 235 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 235 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 12 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 236 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 236 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 13 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 237 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 237 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 14 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 238 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 238 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 15 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 239 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 239 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 16 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 240 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 240 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 17 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 241 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 241 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 18 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 242 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 242 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 19 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 243 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 243 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 20 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 244 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 244 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 21 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 245 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 245 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 22 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 246 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 246 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 23 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 247 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 247 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 24 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 248 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 248 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 25 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 249 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 249 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 26 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 250 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 250 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 27 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 251 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 251 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 28 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 252 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 252 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 29 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 253 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 253 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 30 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 254 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 254 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 31 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 255 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 255 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 32 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 256 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 256 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 33 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 257 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 257 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 34 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 258 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 258 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 35 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 259 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 259 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 36 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 260 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 260 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 37 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 261 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 261 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 38 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 262 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 262 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 39 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 263 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 263 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 40 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 264 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 264 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 40 | J784S4_DEV_WKUP_HSM0 | nvic | 72 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 41 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 265 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 265 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 41 | J784S4_DEV_WKUP_HSM0 | nvic | 73 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 42 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 266 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 266 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 42 | J784S4_DEV_WKUP_HSM0 | nvic | 74 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 43 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 267 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 267 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 43 | J784S4_DEV_WKUP_HSM0 | nvic | 75 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 44 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 268 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 268 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 44 | J784S4_DEV_WKUP_HSM0 | nvic | 76 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 45 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 269 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 269 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 45 | J784S4_DEV_WKUP_HSM0 | nvic | 77 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 46 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 270 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 270 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 46 | J784S4_DEV_WKUP_HSM0 | nvic | 78 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 47 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 271 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 271 | |||
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | 174 | 47 | J784S4_DEV_WKUP_HSM0 | nvic | 79 |
TIMESYNC_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 0 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 1 | J784S4_DEV_GTC0 | gtc_push_event | 0 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 2 | J784S4_DEV_TIMER14 | timer_pwm | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 3 | J784S4_DEV_TIMER15 | timer_pwm | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 4 | J784S4_DEV_NAVSS0 | cpts0_genf0 | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 5 | J784S4_DEV_NAVSS0 | cpts0_genf1 | 2 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 6 | J784S4_DEV_NAVSS0 | cpts0_genf2 | 3 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 7 | J784S4_DEV_NAVSS0 | cpts0_genf3 | 4 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 8 | J784S4_DEV_NAVSS0 | cpts0_genf4 | 5 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 9 | J784S4_DEV_NAVSS0 | cpts0_genf5 | 6 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 10 | J784S4_DEV_PCIE0 | pcie_cpts_genf0 | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 11 | J784S4_DEV_PCIE1 | pcie_cpts_genf0 | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 12 | J784S4_DEV_PCIE2 | pcie_cpts_genf0 | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 13 | J784S4_DEV_PCIE3 | pcie_cpts_genf0 | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 14 | J784S4_DEV_CPSW_9XUSS_J7AM0 | cpts_genf0 | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 15 | J784S4_DEV_CPSW_9XUSS_J7AM0 | cpts_genf1 | 2 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 16 | J784S4_DEV_MCU_CPSW0 | cpts_genf0 | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 17 | J784S4_DEV_MCU_CPSW0 | cpts_genf1 | 2 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 18 | J784S4_DEV_CPSW1 | cpts_genf0 | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 19 | J784S4_DEV_CPSW1 | cpts_genf1 | 2 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 20 | J784S4_DEV_PCIE0 | pcie_cpts_hw1_push | 2 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 21 | J784S4_DEV_PCIE1 | pcie_cpts_hw1_push | 2 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 22 | J784S4_DEV_PCIE2 | pcie_cpts_hw1_push | 2 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 23 | J784S4_DEV_PCIE3 | pcie_cpts_hw1_push | 2 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 24 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 25 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 26 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 27 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 28 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 29 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 30 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 31 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 32 | J784S4_DEV_PCIE0 | pcie_cpts_sync | 4 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 33 | J784S4_DEV_PCIE1 | pcie_cpts_sync | 4 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 34 | J784S4_DEV_PCIE2 | pcie_cpts_sync | 4 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 35 | J784S4_DEV_PCIE3 | pcie_cpts_sync | 4 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 36 | J784S4_DEV_NAVSS0 | cpts0_sync | 7 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 37 | J784S4_DEV_CPSW_9XUSS_J7AM0 | cpts_sync | 3 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 38 | J784S4_DEV_MCU_CPSW0 | cpts_sync | 3 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 39 | J784S4_DEV_CPSW1 | cpts_sync | 3 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 40 | J784S4_DEV_TIMER16 | timer_pwm | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 41 | J784S4_DEV_TIMER17 | timer_pwm | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 42 | J784S4_DEV_TIMER18 | timer_pwm | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 43 | J784S4_DEV_TIMER19 | timer_pwm | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 44 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 45 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 46 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 47 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 48 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 49 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 50 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 51 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 52 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 53 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 54 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 55 | Use TRM - Not managed by TISCI |
TIMESYNC_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 0 | J784S4_DEV_NAVSS0 | cpts0_hw1_push | 0 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 1 | J784S4_DEV_NAVSS0 | cpts0_hw2_push | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 2 | J784S4_DEV_NAVSS0 | cpts0_hw3_push | 2 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 3 | J784S4_DEV_NAVSS0 | cpts0_hw4_push | 3 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 4 | J784S4_DEV_NAVSS0 | cpts0_hw5_push | 4 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 5 | J784S4_DEV_NAVSS0 | cpts0_hw6_push | 5 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 6 | J784S4_DEV_NAVSS0 | cpts0_hw7_push | 6 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 7 | J784S4_DEV_NAVSS0 | cpts0_hw8_push | 7 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 8 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 9 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 10 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 11 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 12 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 13 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 14 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 15 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 16 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 17 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 18 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 19 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 20 | J784S4_DEV_PCIE0 | pcie_cpts_hw2_push | 0 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 21 | J784S4_DEV_PCIE1 | pcie_cpts_hw2_push | 0 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 22 | J784S4_DEV_PCIE2 | pcie_cpts_hw2_push | 0 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 23 | J784S4_DEV_PCIE3 | pcie_cpts_hw2_push | 0 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 24 | J784S4_DEV_MCU_CPSW0 | cpts_hw3_push | 0 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 25 | J784S4_DEV_MCU_CPSW0 | cpts_hw4_push | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 26 | J784S4_DEV_CPSW_9XUSS_J7AM0 | cpts_hw1_push | 0 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 27 | J784S4_DEV_CPSW_9XUSS_J7AM0 | cpts_hw2_push | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 28 | J784S4_DEV_CPSW_9XUSS_J7AM0 | cpts_hw3_push | 2 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 29 | J784S4_DEV_CPSW_9XUSS_J7AM0 | cpts_hw4_push | 3 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 30 | J784S4_DEV_CPSW_9XUSS_J7AM0 | cpts_hw5_push | 4 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 31 | J784S4_DEV_CPSW_9XUSS_J7AM0 | cpts_hw6_push | 5 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 32 | J784S4_DEV_CPSW_9XUSS_J7AM0 | cpts_hw7_push | 6 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 33 | J784S4_DEV_CPSW_9XUSS_J7AM0 | cpts_hw8_push | 7 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 34 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 35 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 36 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 37 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 38 | J784S4_DEV_CPSW1 | cpts_hw3_push | 0 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 39 | J784S4_DEV_CPSW1 | cpts_hw4_push | 1 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 40 | J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 100 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 41 | J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 101 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 42 | J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 102 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 43 | J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 103 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 44 | J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 104 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 45 | J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 105 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 46 | J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 106 |
| J784S4_DEV_TIMESYNC_INTRTR0 | 176 | 47 | J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 107 |
WKUP_GPIOMUX_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 0 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 1 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 2 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 3 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 4 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 5 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 6 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 7 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 8 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 9 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 10 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 11 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 12 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 13 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 14 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 15 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 16 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 17 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 18 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 19 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 20 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 21 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 22 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 23 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 24 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 25 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 26 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 27 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 28 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 29 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 30 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 31 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 32 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 33 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 34 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 35 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 36 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 37 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 38 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 39 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 40 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 41 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 42 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 43 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 44 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 45 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 46 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 47 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 48 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 49 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 50 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 51 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 52 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 53 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 54 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 55 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 56 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 57 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 58 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 59 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 60 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 61 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 62 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 63 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 64 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 65 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 66 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 67 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 68 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 69 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 70 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 71 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 72 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 73 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 74 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 75 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 76 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 77 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 78 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 79 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 80 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 81 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 82 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 83 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 84 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 85 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 86 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 87 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 88 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 89 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 90 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 91 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 92 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 93 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 94 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 95 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 96 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 97 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 98 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 99 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 100 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 101 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 102 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 103 | J784S4_DEV_WKUP_GPIO0 | gpio_bank | 0 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 104 | J784S4_DEV_WKUP_GPIO0 | gpio_bank | 1 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 105 | J784S4_DEV_WKUP_GPIO0 | gpio_bank | 2 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 106 | J784S4_DEV_WKUP_GPIO0 | gpio_bank | 3 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 107 | J784S4_DEV_WKUP_GPIO0 | gpio_bank | 4 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 108 | J784S4_DEV_WKUP_GPIO0 | gpio_bank | 5 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 109 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 110 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 111 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 112 | J784S4_DEV_WKUP_GPIO1 | gpio_bank | 0 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 113 | J784S4_DEV_WKUP_GPIO1 | gpio_bank | 1 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 114 | J784S4_DEV_WKUP_GPIO1 | gpio_bank | 2 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 115 | J784S4_DEV_WKUP_GPIO1 | gpio_bank | 3 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 116 | J784S4_DEV_WKUP_GPIO1 | gpio_bank | 4 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 117 | J784S4_DEV_WKUP_GPIO1 | gpio_bank | 5 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 118 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 119 | Use TRM - Not managed by TISCI |
WKUP_GPIOMUX_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 0 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 124 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 124 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 0 | J784S4_DEV_WKUP_HSM0 | nvic | 184 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 1 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 125 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 125 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 1 | J784S4_DEV_WKUP_HSM0 | nvic | 185 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 2 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 126 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 126 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 2 | J784S4_DEV_WKUP_HSM0 | nvic | 186 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 3 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 127 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 127 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 3 | J784S4_DEV_WKUP_HSM0 | nvic | 187 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 4 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 128 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 128 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 4 | J784S4_DEV_WKUP_HSM0 | nvic | 188 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 5 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 129 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 129 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 5 | J784S4_DEV_WKUP_HSM0 | nvic | 189 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 6 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 130 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 130 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 6 | J784S4_DEV_WKUP_HSM0 | nvic | 190 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 7 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 131 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 131 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 7 | J784S4_DEV_WKUP_HSM0 | nvic | 191 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 8 | J784S4_DEV_WKUP_ESM0 | esm_pls_event0 | 120 |
| J784S4_DEV_WKUP_ESM0 | esm_pls_event1 | 128 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 8 | J784S4_DEV_WKUP_ESM0 | esm_pls_event2 | 136 |
| J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 132 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 8 | J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 132 |
| J784S4_DEV_WKUP_HSM0 | nvic | 192 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 9 | J784S4_DEV_WKUP_ESM0 | esm_pls_event0 | 121 |
| J784S4_DEV_WKUP_ESM0 | esm_pls_event1 | 129 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 9 | J784S4_DEV_WKUP_ESM0 | esm_pls_event2 | 137 |
| J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 133 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 9 | J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 133 |
| J784S4_DEV_WKUP_HSM0 | nvic | 193 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 10 | J784S4_DEV_WKUP_ESM0 | esm_pls_event0 | 122 |
| J784S4_DEV_WKUP_ESM0 | esm_pls_event1 | 130 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 10 | J784S4_DEV_WKUP_ESM0 | esm_pls_event2 | 138 |
| J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 134 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 10 | J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 134 |
| J784S4_DEV_WKUP_HSM0 | nvic | 194 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 11 | J784S4_DEV_WKUP_ESM0 | esm_pls_event0 | 123 |
| J784S4_DEV_WKUP_ESM0 | esm_pls_event1 | 131 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 11 | J784S4_DEV_WKUP_ESM0 | esm_pls_event2 | 139 |
| J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 135 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 11 | J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 135 |
| J784S4_DEV_WKUP_HSM0 | nvic | 195 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 12 | J784S4_DEV_WKUP_ESM0 | esm_pls_event0 | 124 |
| J784S4_DEV_WKUP_ESM0 | esm_pls_event1 | 132 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 12 | J784S4_DEV_WKUP_ESM0 | esm_pls_event2 | 140 |
| J784S4_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 4 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 12 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 136 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 136 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 13 | J784S4_DEV_WKUP_ESM0 | esm_pls_event0 | 125 |
| J784S4_DEV_WKUP_ESM0 | esm_pls_event1 | 133 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 13 | J784S4_DEV_WKUP_ESM0 | esm_pls_event2 | 141 |
| J784S4_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 5 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 13 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 137 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 137 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 14 | J784S4_DEV_WKUP_ESM0 | esm_pls_event0 | 126 |
| J784S4_DEV_WKUP_ESM0 | esm_pls_event1 | 134 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 14 | J784S4_DEV_WKUP_ESM0 | esm_pls_event2 | 142 |
| J784S4_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 6 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 14 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 138 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 138 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 15 | J784S4_DEV_WKUP_ESM0 | esm_pls_event0 | 127 |
| J784S4_DEV_WKUP_ESM0 | esm_pls_event1 | 135 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 15 | J784S4_DEV_WKUP_ESM0 | esm_pls_event2 | 143 |
| J784S4_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 7 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 15 | J784S4_DEV_MCU_R5FSS0_CORE0 | intr | 139 |
| J784S4_DEV_MCU_R5FSS0_CORE1 | intr | 139 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 16 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 960 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 960 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 16 | J784S4_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 8 |
| J784S4_DEV_R5FSS0_CORE0 | intr | 488 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 16 | J784S4_DEV_R5FSS0_CORE1 | intr | 488 |
| J784S4_DEV_R5FSS1_CORE0 | intr | 488 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 16 | J784S4_DEV_R5FSS1_CORE1 | intr | 488 |
| J784S4_DEV_R5FSS2_CORE0 | intr | 488 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 16 | J784S4_DEV_R5FSS2_CORE1 | intr | 488 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 17 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 961 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 961 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 17 | J784S4_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 9 |
| J784S4_DEV_R5FSS0_CORE0 | intr | 489 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 17 | J784S4_DEV_R5FSS0_CORE1 | intr | 489 |
| J784S4_DEV_R5FSS1_CORE0 | intr | 489 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 17 | J784S4_DEV_R5FSS1_CORE1 | intr | 489 |
| J784S4_DEV_R5FSS2_CORE0 | intr | 489 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 17 | J784S4_DEV_R5FSS2_CORE1 | intr | 489 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 18 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 962 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 962 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 18 | J784S4_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 10 |
| J784S4_DEV_R5FSS0_CORE0 | intr | 490 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 18 | J784S4_DEV_R5FSS0_CORE1 | intr | 490 |
| J784S4_DEV_R5FSS1_CORE0 | intr | 490 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 18 | J784S4_DEV_R5FSS1_CORE1 | intr | 490 |
| J784S4_DEV_R5FSS2_CORE0 | intr | 490 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 18 | J784S4_DEV_R5FSS2_CORE1 | intr | 490 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 19 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 963 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 963 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 19 | J784S4_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 11 |
| J784S4_DEV_R5FSS0_CORE0 | intr | 491 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 19 | J784S4_DEV_R5FSS0_CORE1 | intr | 491 |
| J784S4_DEV_R5FSS1_CORE0 | intr | 491 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 19 | J784S4_DEV_R5FSS1_CORE1 | intr | 491 |
| J784S4_DEV_R5FSS2_CORE0 | intr | 491 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 19 | J784S4_DEV_R5FSS2_CORE1 | intr | 491 |
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 20 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 964 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 964 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 20 | J784S4_DEV_R5FSS0_CORE0 | intr | 492 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 492 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 20 | J784S4_DEV_R5FSS1_CORE0 | intr | 492 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 492 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 20 | J784S4_DEV_R5FSS2_CORE0 | intr | 492 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 492 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 21 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 965 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 965 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 21 | J784S4_DEV_R5FSS0_CORE0 | intr | 493 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 493 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 21 | J784S4_DEV_R5FSS1_CORE0 | intr | 493 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 493 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 21 | J784S4_DEV_R5FSS2_CORE0 | intr | 493 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 493 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 22 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 966 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 966 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 22 | J784S4_DEV_R5FSS0_CORE0 | intr | 494 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 494 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 22 | J784S4_DEV_R5FSS1_CORE0 | intr | 494 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 494 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 22 | J784S4_DEV_R5FSS2_CORE0 | intr | 494 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 494 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 23 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 967 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 967 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 23 | J784S4_DEV_R5FSS0_CORE0 | intr | 495 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 495 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 23 | J784S4_DEV_R5FSS1_CORE0 | intr | 495 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 495 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 23 | J784S4_DEV_R5FSS2_CORE0 | intr | 495 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 495 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 24 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 968 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 968 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 24 | J784S4_DEV_R5FSS0_CORE0 | intr | 496 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 496 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 24 | J784S4_DEV_R5FSS1_CORE0 | intr | 496 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 496 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 24 | J784S4_DEV_R5FSS2_CORE0 | intr | 496 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 496 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 25 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 969 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 969 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 25 | J784S4_DEV_R5FSS0_CORE0 | intr | 497 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 497 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 25 | J784S4_DEV_R5FSS1_CORE0 | intr | 497 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 497 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 25 | J784S4_DEV_R5FSS2_CORE0 | intr | 497 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 497 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 26 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 970 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 970 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 26 | J784S4_DEV_R5FSS0_CORE0 | intr | 498 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 498 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 26 | J784S4_DEV_R5FSS1_CORE0 | intr | 498 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 498 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 26 | J784S4_DEV_R5FSS2_CORE0 | intr | 498 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 498 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 27 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 971 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 971 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 27 | J784S4_DEV_R5FSS0_CORE0 | intr | 499 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 499 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 27 | J784S4_DEV_R5FSS1_CORE0 | intr | 499 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 499 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 27 | J784S4_DEV_R5FSS2_CORE0 | intr | 499 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 499 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 28 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 972 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 972 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 28 | J784S4_DEV_R5FSS0_CORE0 | intr | 500 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 500 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 28 | J784S4_DEV_R5FSS1_CORE0 | intr | 500 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 500 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 28 | J784S4_DEV_R5FSS2_CORE0 | intr | 500 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 500 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 29 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 973 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 973 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 29 | J784S4_DEV_R5FSS0_CORE0 | intr | 501 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 501 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 29 | J784S4_DEV_R5FSS1_CORE0 | intr | 501 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 501 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 29 | J784S4_DEV_R5FSS2_CORE0 | intr | 501 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 501 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 30 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 974 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 974 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 30 | J784S4_DEV_R5FSS0_CORE0 | intr | 502 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 502 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 30 | J784S4_DEV_R5FSS1_CORE0 | intr | 502 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 502 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 30 | J784S4_DEV_R5FSS2_CORE0 | intr | 502 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 502 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 31 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 975 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 975 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 31 | J784S4_DEV_R5FSS0_CORE0 | intr | 503 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 503 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 31 | J784S4_DEV_R5FSS1_CORE0 | intr | 503 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 503 | |||
| J784S4_DEV_WKUP_GPIOMUX_INTRTR0 | 177 | 31 | J784S4_DEV_R5FSS2_CORE0 | intr | 503 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 503 |
GPIOMUX_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 0 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 1 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 2 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 3 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 4 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 5 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 6 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 7 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 8 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 9 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 10 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 11 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 12 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 13 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 14 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 15 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 16 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 17 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 18 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 19 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 20 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 21 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 22 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 23 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 24 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 25 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 26 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 27 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 28 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 29 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 30 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 31 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 32 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 33 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 34 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 35 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 36 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 37 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 38 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 39 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 40 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 41 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 42 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 43 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 44 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 45 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 46 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 47 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 48 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 49 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 50 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 51 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 52 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 53 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 54 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 55 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 56 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 57 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 58 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 59 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 60 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 61 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 62 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 63 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 64 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 65 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 66 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 67 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 68 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 69 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 70 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 71 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 72 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 73 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 74 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 75 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 76 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 77 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 78 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 79 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 80 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 81 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 82 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 83 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 84 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 85 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 86 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 87 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 88 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 89 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 90 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 91 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 92 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 93 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 94 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 95 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 96 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 97 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 98 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 99 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 100 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 101 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 102 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 103 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 104 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 105 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 106 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 107 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 108 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 109 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 110 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 111 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 112 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 113 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 114 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 115 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 116 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 117 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 118 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 119 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 120 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 121 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 122 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 123 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 124 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 125 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 126 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 127 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 128 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 129 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 130 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 131 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 132 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 133 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 134 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 135 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 136 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 137 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 138 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 139 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 140 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 141 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 142 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 143 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 144 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 145 | J784S4_DEV_GPIO0 | gpio_bank | 0 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 146 | J784S4_DEV_GPIO0 | gpio_bank | 1 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 147 | J784S4_DEV_GPIO0 | gpio_bank | 2 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 148 | J784S4_DEV_GPIO0 | gpio_bank | 3 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 149 | J784S4_DEV_GPIO0 | gpio_bank | 4 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 150 | J784S4_DEV_GPIO0 | gpio_bank | 5 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 151 | J784S4_DEV_GPIO0 | gpio_bank | 6 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 152 | J784S4_DEV_GPIO0 | gpio_bank | 7 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 153 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 154 | J784S4_DEV_GPIO2 | gpio_bank | 0 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 155 | J784S4_DEV_GPIO2 | gpio_bank | 1 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 156 | J784S4_DEV_GPIO2 | gpio_bank | 2 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 157 | J784S4_DEV_GPIO2 | gpio_bank | 3 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 158 | J784S4_DEV_GPIO2 | gpio_bank | 4 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 159 | J784S4_DEV_GPIO2 | gpio_bank | 5 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 160 | J784S4_DEV_GPIO2 | gpio_bank | 6 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 161 | J784S4_DEV_GPIO2 | gpio_bank | 7 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 162 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 163 | J784S4_DEV_GPIO4 | gpio_bank | 0 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 164 | J784S4_DEV_GPIO4 | gpio_bank | 1 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 165 | J784S4_DEV_GPIO4 | gpio_bank | 2 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 166 | J784S4_DEV_GPIO4 | gpio_bank | 3 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 167 | J784S4_DEV_GPIO4 | gpio_bank | 4 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 168 | J784S4_DEV_GPIO4 | gpio_bank | 5 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 169 | J784S4_DEV_GPIO4 | gpio_bank | 6 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 170 | J784S4_DEV_GPIO4 | gpio_bank | 7 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 171 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 172 | J784S4_DEV_GPIO6 | gpio_bank | 0 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 173 | J784S4_DEV_GPIO6 | gpio_bank | 1 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 174 | J784S4_DEV_GPIO6 | gpio_bank | 2 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 175 | J784S4_DEV_GPIO6 | gpio_bank | 3 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 176 | J784S4_DEV_GPIO6 | gpio_bank | 4 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 177 | J784S4_DEV_GPIO6 | gpio_bank | 5 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 178 | J784S4_DEV_GPIO6 | gpio_bank | 6 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 179 | J784S4_DEV_GPIO6 | gpio_bank | 7 |
GPIOMUX_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 0 | J784S4_DEV_ESM0 | esm_pls_event0 | 664 |
| J784S4_DEV_ESM0 | esm_pls_event1 | 672 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 0 | J784S4_DEV_ESM0 | esm_pls_event2 | 680 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 64 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 0 | J784S4_DEV_R5FSS0_CORE0 | intr | 396 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 396 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 0 | J784S4_DEV_R5FSS1_CORE0 | intr | 396 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 396 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 0 | J784S4_DEV_R5FSS2_CORE0 | intr | 396 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 396 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 1 | J784S4_DEV_ESM0 | esm_pls_event0 | 665 |
| J784S4_DEV_ESM0 | esm_pls_event1 | 673 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 1 | J784S4_DEV_ESM0 | esm_pls_event2 | 681 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 65 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 1 | J784S4_DEV_R5FSS0_CORE0 | intr | 397 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 397 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 1 | J784S4_DEV_R5FSS1_CORE0 | intr | 397 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 397 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 1 | J784S4_DEV_R5FSS2_CORE0 | intr | 397 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 397 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 2 | J784S4_DEV_ESM0 | esm_pls_event0 | 666 |
| J784S4_DEV_ESM0 | esm_pls_event1 | 674 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 2 | J784S4_DEV_ESM0 | esm_pls_event2 | 682 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 66 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 2 | J784S4_DEV_R5FSS0_CORE0 | intr | 398 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 398 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 2 | J784S4_DEV_R5FSS1_CORE0 | intr | 398 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 398 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 2 | J784S4_DEV_R5FSS2_CORE0 | intr | 398 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 398 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 3 | J784S4_DEV_ESM0 | esm_pls_event0 | 667 |
| J784S4_DEV_ESM0 | esm_pls_event1 | 675 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 3 | J784S4_DEV_ESM0 | esm_pls_event2 | 683 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 67 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 3 | J784S4_DEV_R5FSS0_CORE0 | intr | 399 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 399 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 3 | J784S4_DEV_R5FSS1_CORE0 | intr | 399 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 399 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 3 | J784S4_DEV_R5FSS2_CORE0 | intr | 399 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 399 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 4 | J784S4_DEV_ESM0 | esm_pls_event0 | 668 |
| J784S4_DEV_ESM0 | esm_pls_event1 | 676 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 4 | J784S4_DEV_ESM0 | esm_pls_event2 | 684 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 68 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 4 | J784S4_DEV_R5FSS0_CORE0 | intr | 400 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 400 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 4 | J784S4_DEV_R5FSS1_CORE0 | intr | 400 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 400 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 4 | J784S4_DEV_R5FSS2_CORE0 | intr | 400 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 400 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 5 | J784S4_DEV_ESM0 | esm_pls_event0 | 669 |
| J784S4_DEV_ESM0 | esm_pls_event1 | 677 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 5 | J784S4_DEV_ESM0 | esm_pls_event2 | 685 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 69 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 5 | J784S4_DEV_R5FSS0_CORE0 | intr | 401 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 401 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 5 | J784S4_DEV_R5FSS1_CORE0 | intr | 401 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 401 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 5 | J784S4_DEV_R5FSS2_CORE0 | intr | 401 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 401 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 6 | J784S4_DEV_ESM0 | esm_pls_event0 | 670 |
| J784S4_DEV_ESM0 | esm_pls_event1 | 678 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 6 | J784S4_DEV_ESM0 | esm_pls_event2 | 686 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 70 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 6 | J784S4_DEV_R5FSS0_CORE0 | intr | 402 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 402 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 6 | J784S4_DEV_R5FSS1_CORE0 | intr | 402 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 402 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 6 | J784S4_DEV_R5FSS2_CORE0 | intr | 402 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 402 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 7 | J784S4_DEV_ESM0 | esm_pls_event0 | 671 |
| J784S4_DEV_ESM0 | esm_pls_event1 | 679 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 7 | J784S4_DEV_ESM0 | esm_pls_event2 | 687 |
| J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 71 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 7 | J784S4_DEV_R5FSS0_CORE0 | intr | 403 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 403 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 7 | J784S4_DEV_R5FSS1_CORE0 | intr | 403 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 403 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 7 | J784S4_DEV_R5FSS2_CORE0 | intr | 403 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 403 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 8 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 392 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 392 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 8 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 72 |
| J784S4_DEV_R5FSS0_CORE0 | intr | 404 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 8 | J784S4_DEV_R5FSS0_CORE1 | intr | 404 |
| J784S4_DEV_R5FSS1_CORE0 | intr | 404 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 8 | J784S4_DEV_R5FSS1_CORE1 | intr | 404 |
| J784S4_DEV_R5FSS2_CORE0 | intr | 404 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 8 | J784S4_DEV_R5FSS2_CORE1 | intr | 404 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 9 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 393 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 393 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 9 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 73 |
| J784S4_DEV_R5FSS0_CORE0 | intr | 405 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 9 | J784S4_DEV_R5FSS0_CORE1 | intr | 405 |
| J784S4_DEV_R5FSS1_CORE0 | intr | 405 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 9 | J784S4_DEV_R5FSS1_CORE1 | intr | 405 |
| J784S4_DEV_R5FSS2_CORE0 | intr | 405 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 9 | J784S4_DEV_R5FSS2_CORE1 | intr | 405 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 10 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 394 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 394 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 10 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 74 |
| J784S4_DEV_R5FSS0_CORE0 | intr | 406 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 10 | J784S4_DEV_R5FSS0_CORE1 | intr | 406 |
| J784S4_DEV_R5FSS1_CORE0 | intr | 406 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 10 | J784S4_DEV_R5FSS1_CORE1 | intr | 406 |
| J784S4_DEV_R5FSS2_CORE0 | intr | 406 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 10 | J784S4_DEV_R5FSS2_CORE1 | intr | 406 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 11 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 395 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 395 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 11 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 75 |
| J784S4_DEV_R5FSS0_CORE0 | intr | 407 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 11 | J784S4_DEV_R5FSS0_CORE1 | intr | 407 |
| J784S4_DEV_R5FSS1_CORE0 | intr | 407 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 11 | J784S4_DEV_R5FSS1_CORE1 | intr | 407 |
| J784S4_DEV_R5FSS2_CORE0 | intr | 407 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 11 | J784S4_DEV_R5FSS2_CORE1 | intr | 407 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 12 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 396 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 396 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 12 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 76 |
| J784S4_DEV_R5FSS0_CORE0 | intr | 408 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 12 | J784S4_DEV_R5FSS0_CORE1 | intr | 408 |
| J784S4_DEV_R5FSS1_CORE0 | intr | 408 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 12 | J784S4_DEV_R5FSS1_CORE1 | intr | 408 |
| J784S4_DEV_R5FSS2_CORE0 | intr | 408 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 12 | J784S4_DEV_R5FSS2_CORE1 | intr | 408 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 13 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 397 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 397 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 13 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 77 |
| J784S4_DEV_R5FSS0_CORE0 | intr | 409 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 13 | J784S4_DEV_R5FSS0_CORE1 | intr | 409 |
| J784S4_DEV_R5FSS1_CORE0 | intr | 409 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 13 | J784S4_DEV_R5FSS1_CORE1 | intr | 409 |
| J784S4_DEV_R5FSS2_CORE0 | intr | 409 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 13 | J784S4_DEV_R5FSS2_CORE1 | intr | 409 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 14 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 398 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 398 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 14 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 78 |
| J784S4_DEV_R5FSS0_CORE0 | intr | 410 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 14 | J784S4_DEV_R5FSS0_CORE1 | intr | 410 |
| J784S4_DEV_R5FSS1_CORE0 | intr | 410 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 14 | J784S4_DEV_R5FSS1_CORE1 | intr | 410 |
| J784S4_DEV_R5FSS2_CORE0 | intr | 410 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 14 | J784S4_DEV_R5FSS2_CORE1 | intr | 410 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 15 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 399 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 399 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 15 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 79 |
| J784S4_DEV_R5FSS0_CORE0 | intr | 411 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 15 | J784S4_DEV_R5FSS0_CORE1 | intr | 411 |
| J784S4_DEV_R5FSS1_CORE0 | intr | 411 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 15 | J784S4_DEV_R5FSS1_CORE1 | intr | 411 |
| J784S4_DEV_R5FSS2_CORE0 | intr | 411 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 15 | J784S4_DEV_R5FSS2_CORE1 | intr | 411 |
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 16 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 400 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 400 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 16 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 80 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 116 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 16 | J784S4_DEV_R5FSS0_CORE0 | intr | 176 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 176 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 16 | J784S4_DEV_R5FSS1_CORE0 | intr | 176 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 176 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 16 | J784S4_DEV_R5FSS2_CORE0 | intr | 176 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 176 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 17 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 401 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 401 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 17 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 81 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 117 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 17 | J784S4_DEV_R5FSS0_CORE0 | intr | 177 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 177 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 17 | J784S4_DEV_R5FSS1_CORE0 | intr | 177 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 177 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 17 | J784S4_DEV_R5FSS2_CORE0 | intr | 177 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 177 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 18 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 402 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 402 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 18 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 82 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 118 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 18 | J784S4_DEV_R5FSS0_CORE0 | intr | 178 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 178 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 18 | J784S4_DEV_R5FSS1_CORE0 | intr | 178 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 178 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 18 | J784S4_DEV_R5FSS2_CORE0 | intr | 178 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 178 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 19 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 403 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 403 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 19 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 83 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 119 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 19 | J784S4_DEV_R5FSS0_CORE0 | intr | 179 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 179 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 19 | J784S4_DEV_R5FSS1_CORE0 | intr | 179 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 179 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 19 | J784S4_DEV_R5FSS2_CORE0 | intr | 179 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 179 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 20 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 404 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 404 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 20 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 84 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 120 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 20 | J784S4_DEV_R5FSS0_CORE0 | intr | 180 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 180 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 20 | J784S4_DEV_R5FSS1_CORE0 | intr | 180 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 180 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 20 | J784S4_DEV_R5FSS2_CORE0 | intr | 180 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 180 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 21 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 405 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 405 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 21 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 85 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 121 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 21 | J784S4_DEV_R5FSS0_CORE0 | intr | 181 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 181 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 21 | J784S4_DEV_R5FSS1_CORE0 | intr | 181 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 181 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 21 | J784S4_DEV_R5FSS2_CORE0 | intr | 181 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 181 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 22 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 406 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 406 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 22 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 86 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 122 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 22 | J784S4_DEV_R5FSS0_CORE0 | intr | 182 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 182 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 22 | J784S4_DEV_R5FSS1_CORE0 | intr | 182 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 182 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 22 | J784S4_DEV_R5FSS2_CORE0 | intr | 182 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 182 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 23 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 407 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 407 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 23 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 87 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 123 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 23 | J784S4_DEV_R5FSS0_CORE0 | intr | 183 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 183 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 23 | J784S4_DEV_R5FSS1_CORE0 | intr | 183 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 183 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 23 | J784S4_DEV_R5FSS2_CORE0 | intr | 183 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 183 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 24 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 408 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 408 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 24 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 88 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 124 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 24 | J784S4_DEV_R5FSS0_CORE0 | intr | 184 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 184 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 24 | J784S4_DEV_R5FSS1_CORE0 | intr | 184 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 184 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 24 | J784S4_DEV_R5FSS2_CORE0 | intr | 184 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 184 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 25 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 409 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 409 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 25 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 89 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 125 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 25 | J784S4_DEV_R5FSS0_CORE0 | intr | 185 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 185 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 25 | J784S4_DEV_R5FSS1_CORE0 | intr | 185 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 185 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 25 | J784S4_DEV_R5FSS2_CORE0 | intr | 185 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 185 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 26 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 410 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 410 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 26 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 90 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 126 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 26 | J784S4_DEV_R5FSS0_CORE0 | intr | 186 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 186 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 26 | J784S4_DEV_R5FSS1_CORE0 | intr | 186 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 186 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 26 | J784S4_DEV_R5FSS2_CORE0 | intr | 186 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 186 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 27 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 411 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 411 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 27 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 91 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 127 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 27 | J784S4_DEV_R5FSS0_CORE0 | intr | 187 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 187 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 27 | J784S4_DEV_R5FSS1_CORE0 | intr | 187 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 187 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 27 | J784S4_DEV_R5FSS2_CORE0 | intr | 187 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 187 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 28 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 412 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 412 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 28 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 92 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 128 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 28 | J784S4_DEV_R5FSS0_CORE0 | intr | 188 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 188 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 28 | J784S4_DEV_R5FSS1_CORE0 | intr | 188 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 188 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 28 | J784S4_DEV_R5FSS2_CORE0 | intr | 188 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 188 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 29 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 413 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 413 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 29 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 93 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 129 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 29 | J784S4_DEV_R5FSS0_CORE0 | intr | 189 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 189 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 29 | J784S4_DEV_R5FSS1_CORE0 | intr | 189 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 189 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 29 | J784S4_DEV_R5FSS2_CORE0 | intr | 189 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 189 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 30 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 414 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 414 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 30 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 94 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 130 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 30 | J784S4_DEV_R5FSS0_CORE0 | intr | 190 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 190 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 30 | J784S4_DEV_R5FSS1_CORE0 | intr | 190 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 190 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 30 | J784S4_DEV_R5FSS2_CORE0 | intr | 190 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 190 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 31 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 415 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 415 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 31 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 95 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 131 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 31 | J784S4_DEV_R5FSS0_CORE0 | intr | 191 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 191 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 31 | J784S4_DEV_R5FSS1_CORE0 | intr | 191 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 191 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 31 | J784S4_DEV_R5FSS2_CORE0 | intr | 191 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 191 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 32 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 416 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 416 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 33 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 417 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 417 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 34 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 418 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 418 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 35 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 419 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 419 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 36 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 420 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 420 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 37 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 421 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 421 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 38 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 422 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 422 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 39 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 423 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 423 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 40 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 424 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 424 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 41 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 425 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 425 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 42 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 426 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 426 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 43 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 427 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 427 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 44 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 428 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 428 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 45 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 429 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 429 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 46 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 430 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 430 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 47 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 431 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 431 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 48 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 432 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 432 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 49 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 433 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 433 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 50 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 434 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 434 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 51 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 435 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 435 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 52 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 436 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 436 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 53 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 437 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 437 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 54 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 438 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 438 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 55 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 439 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 439 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 56 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 440 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 440 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 57 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 441 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 441 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 58 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 442 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 442 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 59 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 443 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 443 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 60 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 444 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 444 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 61 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 445 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 445 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 62 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 446 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 446 | |||
| J784S4_DEV_GPIOMUX_INTRTR0 | 10 | 63 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 447 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 447 |
CMPEVENT_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 0 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 1 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 2 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 3 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 4 | J784S4_DEV_PCIE0 | pcie_cpts_comp | 0 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 5 | J784S4_DEV_PCIE1 | pcie_cpts_comp | 0 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 6 | J784S4_DEV_PCIE2 | pcie_cpts_comp | 0 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 7 | J784S4_DEV_PCIE3 | pcie_cpts_comp | 0 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 8 | J784S4_DEV_NAVSS0 | cpts0_comp | 0 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 9 | J784S4_DEV_CPSW_9XUSS_J7AM0 | cpts_comp | 0 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 10 | J784S4_DEV_MCU_CPSW0 | cpts_comp | 0 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 11 | J784S4_DEV_CPSW1 | cpts_comp | 0 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 12 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 13 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 14 | Use TRM - Not managed by TISCI | ||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 15 | Use TRM - Not managed by TISCI |
CMPEVENT_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 0 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 544 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 544 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 1 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 545 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 545 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 2 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 546 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 546 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 3 | J784S4_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 547 |
| J784S4_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 547 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 4 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 96 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 5 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 97 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 6 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 98 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 7 | J784S4_DEV_MAIN2MCU_PLS_INTRTR0 | in | 99 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 8 | J784S4_DEV_R5FSS0_CORE0 | intr | 326 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 326 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 8 | J784S4_DEV_R5FSS1_CORE0 | intr | 326 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 326 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 8 | J784S4_DEV_R5FSS2_CORE0 | intr | 326 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 326 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 9 | J784S4_DEV_R5FSS0_CORE0 | intr | 327 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 327 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 9 | J784S4_DEV_R5FSS1_CORE0 | intr | 327 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 327 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 9 | J784S4_DEV_R5FSS2_CORE0 | intr | 327 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 327 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 10 | J784S4_DEV_R5FSS0_CORE0 | intr | 328 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 328 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 10 | J784S4_DEV_R5FSS1_CORE0 | intr | 328 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 328 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 10 | J784S4_DEV_R5FSS2_CORE0 | intr | 328 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 328 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 11 | J784S4_DEV_R5FSS0_CORE0 | intr | 329 |
| J784S4_DEV_R5FSS0_CORE1 | intr | 329 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 11 | J784S4_DEV_R5FSS1_CORE0 | intr | 329 |
| J784S4_DEV_R5FSS1_CORE1 | intr | 329 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 11 | J784S4_DEV_R5FSS2_CORE0 | intr | 329 |
| J784S4_DEV_R5FSS2_CORE1 | intr | 329 | |||
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 12 | J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 108 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 13 | J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 109 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 14 | J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 110 |
| J784S4_DEV_CMPEVENT_INTRTR0 | 11 | 15 | J784S4_DEV_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 111 |
Interrupt Aggregator Device IDs¶
Some System Firmware TISCI message APIs require the Interrupt Aggregator device ID be provided as part of the request. Based on J784S4 Device IDs these are the valid Interrupt Aggregator device IDs.
| Interrupt Aggregator Device Name | Interrupt Aggregator Device ID |
|---|---|
| J784S4_DEV_NAVSS0_MODSS_INTA_0 | 310 |
| J784S4_DEV_NAVSS0_MODSS_INTA_1 | 311 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | 321 |
| J784S4_DEV_MCU_NAVSS0_UDMASS_INTA_0 | 331 |
Interrupt Aggregator Virtual Interrupts¶
This section describes Interrupt Aggregator virtual interrupts. The virtual interrupts are used in interrupt management based TISCI messages.
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| Interrupt Aggregator Name | Virtual Interrupt Range |
|---|---|
| J784S4_DEV_NAVSS0_MODSS_INTA_0 | 0 to 63 |
| J784S4_DEV_NAVSS0_MODSS_INTA_1 | 0 to 63 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 (RESERVED BY SYSTEM FIRMWARE) | 0 to 55 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | 56 to 255 |
| J784S4_DEV_MCU_NAVSS0_UDMASS_INTA_0 (RESERVED BY SYSTEM FIRMWARE) | 0 to 21 |
| J784S4_DEV_MCU_NAVSS0_UDMASS_INTA_0 | 22 to 255 |
Global Events¶
This section describes J784S4 global events. The global events are used in interrupt management based TISCI messages.
Warning
Resources marked as reserved for use by TIFS cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| Global Event Name | Global Event Range |
|---|---|
| NAVSS0_UDMASS_INTA_0 SEVT (RESERVED BY SYSTEM FIRMWARE) | 0 to 55 |
| NAVSS0_UDMASS_INTA_0 SEVT | 56 to 4607 |
| MCU_NAVSS0_UDMASS_INTA_0 SEVT (RESERVED BY SYSTEM FIRMWARE) | 16384 to 16405 |
| MCU_NAVSS0_UDMASS_INTA_0 SEVT | 16406 to 17919 |
| NAVSS0_MODSS_INTA_0 SEVT | 20480 to 21503 |
| NAVSS0_MODSS_INTA_1 SEVT | 22528 to 23551 |
| NAVSS0_UDMASS_INTA_0 MEVT | 32768 to 33279 |
| MCU_NAVSS0_UDMASS_INTA_0 MEVT | 34816 to 34943 |
| NAVSS0_UDMASS_INTA_0 GEVT | 36864 to 37375 |
| MCU_NAVSS0_UDMASS_INTA_0 GEVT | 39936 to 40191 |
| NAVSS0_UDMAP_0 TRIGGER | 49152 to 50175 |
| NAVSS0_BCDMA_0 TRIGGER | 50176 to 50271 |
| MCU_NAVSS0_UDMAP_0 TRIGGER | 56320 to 56575 |
Event-Based Interrupt Source IDs¶
| Device Name | Device ID | Interrupt Source Name | Interrupt Source Index |
|---|---|---|---|
| J784S4_DEV_NAVSS0_RINGACC_0 | 315 | Ring events | 0 to 767 |
| J784S4_DEV_NAVSS0_RINGACC_0 | 315 | Ring events | 878 to 1023 |
| J784S4_DEV_MCU_NAVSS0_RINGACC0 | 328 | Ring events | 0 to 255 |
| J784S4_DEV_NAVSS0_RINGACC_0 | 315 | Ring monitor events | 1024 to 1055 |
| J784S4_DEV_MCU_NAVSS0_RINGACC0 | 328 | Ring monitor events | 1024 to 1055 |
| J784S4_DEV_NAVSS0_RINGACC_0 | 315 | Ring global error event | 2048 |
| J784S4_DEV_MCU_NAVSS0_RINGACC0 | 328 | Ring global error event | 2048 |
| J784S4_DEV_NAVSS0_UDMAP_0 | 319 | UDMA transmit channel OES events | 0 to 340 |
| J784S4_DEV_NAVSS0_UDMAP_0 | 319 | UDMA transmit channel EOES events | 512 to 852 |
| J784S4_DEV_NAVSS0_UDMAP_0 | 319 | UDMA receive channel OES events | 1024 to 1105 |
| J784S4_DEV_NAVSS0_UDMAP_0 | 319 | UDMA receive channel EOES events | 1152 to 1233 |
| J784S4_DEV_NAVSS0_UDMAP_0 | 319 | UDMA global configuration invalid flow event | 1280 |
| J784S4_DEV_MCU_NAVSS0_UDMAP_0 | 329 | UDMA transmit channel OES events | 0 to 47 |
| J784S4_DEV_MCU_NAVSS0_UDMAP_0 | 329 | UDMA transmit channel EOES events | 512 to 559 |
| J784S4_DEV_MCU_NAVSS0_UDMAP_0 | 329 | UDMA receive channel OES events | 1024 to 1071 |
| J784S4_DEV_MCU_NAVSS0_UDMAP_0 | 329 | UDMA receive channel EOES events | 1152 to 1199 |
| J784S4_DEV_MCU_NAVSS0_UDMAP_0 | 329 | UDMA global configuration invalid flow event | 1280 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | 321 | NAVSS0_UDMASS_INTA_0 mapped bcdma_tx_chan_error events | 1536 to 1551 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | 321 | NAVSS0_UDMASS_INTA_0 mapped bcdma_tx_chan_data_completion events | 2048 to 2063 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | 321 | NAVSS0_UDMASS_INTA_0 mapped bcdma_tx_chan_ring_completion events | 2560 to 2575 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | 321 | NAVSS0_UDMASS_INTA_0 mapped bcdma_rx_chan_error events | 3072 to 3103 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | 321 | NAVSS0_UDMASS_INTA_0 mapped bcdma_rx_chan_data_completion events | 3584 to 3615 |
| J784S4_DEV_NAVSS0_UDMASS_INTA_0 | 321 | NAVSS0_UDMASS_INTA_0 mapped bcdma_rx_chan_ring_completion events | 4096 to 4127 |