J784S4 Host Descriptions

Introduction

This chapter provides information on the set of HostIDs permitted in this J784S4 SoC. HostIDs uniquely identify each logically distinct high level software entity. A software entity identification number (HostID) can be assigned to an OS either native or virtualized, or a firmware/native application. The HostID is used to select the set of Secure Proxy channels for which this software entity should use to communicate with the System Firmware.

As an example with an R5 core, then there could be 0, 1, or n number of R5 related hosts. The only limit is the number of available Secure Proxy Channels. Typically though, an R5 core will be assigned one secure host as well as one non secure host, but may be assigned additional hosts for certain usecases. As for other cores, some will only use secure hosts, and others will only use non secure hosts. Since the hosts are tied to Secure Proxy Channels, hosts are just a way of sectioning off data for a designated purpose.

System Firmware also checks that the used HostID comes from software running on the correct core (as implied by Host Name in the below table) and with the correct security level (Security Status column).

Additionally, one of the key reasons why HostID is tied in with Secure Proxy channels is because it prevents spoofing. When a message is received by System Firmware, the Secure Proxy channel tied to the HostID in the message is verified against the Secure Proxy channel on which the message was received. Specifically, only the HostID listed in the “Host Name” column can use the Secure Proxy channel associated with it.

Enumeration of Host IDs

Host ID Host Name Security Status Description
0 TIFS Secure Security Controller
3 MCU_0_R5_0 Non Secure Cortex R5 context 0 on MCU island
4 MCU_0_R5_1 Secure Cortex R5 context 1 on MCU island(Boot)
5 MCU_0_R5_2 Non Secure Cortex R5 context 2 on MCU island
6 MCU_0_R5_3 Secure Cortex R5 context 3 on MCU island
10 A72_0 Secure Cortex A72 context 0 on Main island
11 A72_1 Secure Cortex A72 context 1 on Main island
12 A72_2 Non Secure Cortex A72 context 2 on Main island
13 A72_3 Non Secure Cortex A72 context 3 on Main island
14 A72_4 Non Secure Cortex A72 context 4 on Main island
15 A72_5 Non Secure Cortex A72 context 5 on Main island
16 A72_6 Non Secure Cortex A72 context 6 on Main island
17 A72_7 Non Secure Cortex A72 context 7 on Main island
20 C7X_0_0 Secure C7x_0 Context 0 on Main island
21 C7X_0_1 Non Secure C7x_0 context 1 on Main island
22 C7X_1_0 Secure C7x_1 Context 0 on Main island
23 C7X_1_1 Non Secure C7x_1 context 1 on Main island
24 C7X_2_0 Secure C7x_2 Context 0 on Main island
25 C7X_2_1 Non Secure C7x_2 context 1 on Main island
26 C7X_3_0 Secure C7x_2 Context 0 on Main island
27 C7X_3_1 Non Secure C7x_3 context 1 on Main island
30 GPU_0 Non Secure BXS context 0 on Main island
35 MAIN_0_R5_0 Non Secure Cortex R5_0 context 0 on Main island
36 MAIN_0_R5_1 Secure Cortex R5_0 context 1 on Main island
37 MAIN_0_R5_2 Non Secure Cortex R5_0 context 2 on Main island
38 MAIN_0_R5_3 Secure Cortex R5_0 context 3 on Main island
40 MAIN_1_R5_0 Non Secure Cortex R5_1 context 0 on Main island
41 MAIN_1_R5_1 Secure Cortex R5_1 context 1 on Main island
42 MAIN_1_R5_2 Non Secure Cortex R5_1 context 2 on Main island
43 MAIN_1_R5_3 Secure Cortex R5_1 context 3 on Main island
45 MAIN_2_R5_0 Non Secure Cortex R5_2 context 0 on Main island
46 MAIN_2_R5_1 Secure Cortex R5_2 context 1 on Main island
47 MAIN_2_R5_2 Non Secure Cortex R5_2 context 2 on Main island
48 MAIN_2_R5_3 Secure Cortex R5_2 context 3 on Main island
250 DM2TIFS Secure DM to TIFS communication
251 TIFS2DM Non Secure TIFS to DM communication
253 HSM Secure HSM Controller
254 DM Non Secure Device Management

Note

  • Description provides an intended purpose of the host ID, though on some systems, this might be used differently, backing memory and link allocations are made with the specified purpose in mind
  • Security Status provides an intended purpose for the Host context